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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s3 4; The following tests is to check the correctness of reversing input operand5; of vext by enumerating all cases of using two undefs in shuffle masks.6 7define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {8; CHECK-LABEL: vext_6701_0:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #411; CHECK-NEXT: ret12entry:13 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>14 ret <4 x i16> %x15}16 17define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {18; CHECK-LABEL: vext_6701_12:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: // kill: def $d0 killed $d0 def $q021; CHECK-NEXT: dup v0.2s, v0.s[0]22; CHECK-NEXT: ret23entry:24 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>25 ret <4 x i16> %x26}27 28define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {29; CHECK-LABEL: vext_6701_13:30; CHECK: // %bb.0: // %entry31; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #432; CHECK-NEXT: ret33entry:34 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>35 ret <4 x i16> %x36}37 38define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {39; CHECK-LABEL: vext_6701_14:40; CHECK: // %bb.0: // %entry41; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #442; CHECK-NEXT: ret43entry:44 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>45 ret <4 x i16> %x46}47 48define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {49; CHECK-LABEL: vext_6701_23:50; CHECK: // %bb.0: // %entry51; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #452; CHECK-NEXT: ret53entry:54 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>55 ret <4 x i16> %x56}57 58define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {59; CHECK-LABEL: vext_6701_24:60; CHECK: // %bb.0: // %entry61; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #462; CHECK-NEXT: ret63entry:64 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>65 ret <4 x i16> %x66}67 68define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {69; CHECK-LABEL: vext_6701_34:70; CHECK: // %bb.0: // %entry71; CHECK-NEXT: // kill: def $d1 killed $d1 def $q172; CHECK-NEXT: dup v0.2s, v1.s[1]73; CHECK-NEXT: ret74entry:75 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>76 ret <4 x i16> %x77}78 79define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {80; CHECK-LABEL: vext_5670_0:81; CHECK: // %bb.0: // %entry82; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #283; CHECK-NEXT: ret84entry:85 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>86 ret <4 x i16> %x87}88 89define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {90; CHECK-LABEL: vext_5670_12:91; CHECK: // %bb.0: // %entry92; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #293; CHECK-NEXT: ret94entry:95 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>96 ret <4 x i16> %x97}98 99define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {100; CHECK-LABEL: vext_5670_13:101; CHECK: // %bb.0: // %entry102; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2103; CHECK-NEXT: ret104entry:105 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>106 ret <4 x i16> %x107}108 109define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {110; CHECK-LABEL: vext_5670_14:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2113; CHECK-NEXT: ret114entry:115 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>116 ret <4 x i16> %x117}118 119define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {120; CHECK-LABEL: vext_5670_23:121; CHECK: // %bb.0: // %entry122; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2123; CHECK-NEXT: ret124entry:125 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>126 ret <4 x i16> %x127}128 129define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {130; CHECK-LABEL: vext_5670_24:131; CHECK: // %bb.0: // %entry132; CHECK-NEXT: rev32 v0.4h, v1.4h133; CHECK-NEXT: ret134entry:135 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>136 ret <4 x i16> %x137}138 139define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {140; CHECK-LABEL: vext_5670_34:141; CHECK: // %bb.0: // %entry142; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2143; CHECK-NEXT: ret144entry:145 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>146 ret <4 x i16> %x147}148 149define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {150; CHECK-LABEL: vext_7012_0:151; CHECK: // %bb.0: // %entry152; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6153; CHECK-NEXT: ret154entry:155 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>156 ret <4 x i16> %x157}158 159define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {160; CHECK-LABEL: vext_7012_12:161; CHECK: // %bb.0: // %entry162; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6163; CHECK-NEXT: ret164entry:165 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>166 ret <4 x i16> %x167}168 169define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {170; CHECK-LABEL: vext_7012_13:171; CHECK: // %bb.0: // %entry172; CHECK-NEXT: rev32 v0.4h, v0.4h173; CHECK-NEXT: ret174entry:175 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>176 ret <4 x i16> %x177}178 179define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {180; CHECK-LABEL: vext_7012_14:181; CHECK: // %bb.0: // %entry182; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6183; CHECK-NEXT: ret184entry:185 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>186 ret <4 x i16> %x187}188 189define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {190; CHECK-LABEL: vext_7012_23:191; CHECK: // %bb.0: // %entry192; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6193; CHECK-NEXT: ret194entry:195 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>196 ret <4 x i16> %x197}198 199define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {200; CHECK-LABEL: vext_7012_24:201; CHECK: // %bb.0: // %entry202; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6203; CHECK-NEXT: ret204entry:205 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>206 ret <4 x i16> %x207}208 209define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {210; CHECK-LABEL: vext_7012_34:211; CHECK: // %bb.0: // %entry212; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6213; CHECK-NEXT: ret214entry:215 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>216 ret <4 x i16> %x217}218