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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s2 3define <8 x i8> @shsub8b(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: shsub8b:5;CHECK: shsub.8b6 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <16 x i8> @shsub16b(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: shsub16b:14;CHECK: shsub.16b15 %tmp1 = load <16 x i8>, ptr %A16 %tmp2 = load <16 x i8>, ptr %B17 %tmp3 = call <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)18 ret <16 x i8> %tmp319}20 21define <4 x i16> @shsub4h(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: shsub4h:23;CHECK: shsub.4h24 %tmp1 = load <4 x i16>, ptr %A25 %tmp2 = load <4 x i16>, ptr %B26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)27 ret <4 x i16> %tmp328}29 30define <8 x i16> @shsub8h(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: shsub8h:32;CHECK: shsub.8h33 %tmp1 = load <8 x i16>, ptr %A34 %tmp2 = load <8 x i16>, ptr %B35 %tmp3 = call <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)36 ret <8 x i16> %tmp337}38 39define <2 x i32> @shsub2s(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: shsub2s:41;CHECK: shsub.2s42 %tmp1 = load <2 x i32>, ptr %A43 %tmp2 = load <2 x i32>, ptr %B44 %tmp3 = call <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)45 ret <2 x i32> %tmp346}47 48define <4 x i32> @shsub4s(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: shsub4s:50;CHECK: shsub.4s51 %tmp1 = load <4 x i32>, ptr %A52 %tmp2 = load <4 x i32>, ptr %B53 %tmp3 = call <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)54 ret <4 x i32> %tmp355}56 57define <8 x i8> @uhsub8b(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: uhsub8b:59;CHECK: uhsub.8b60 %tmp1 = load <8 x i8>, ptr %A61 %tmp2 = load <8 x i8>, ptr %B62 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)63 ret <8 x i8> %tmp364}65 66define <16 x i8> @uhsub16b(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: uhsub16b:68;CHECK: uhsub.16b69 %tmp1 = load <16 x i8>, ptr %A70 %tmp2 = load <16 x i8>, ptr %B71 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)72 ret <16 x i8> %tmp373}74 75define <4 x i16> @uhsub4h(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: uhsub4h:77;CHECK: uhsub.4h78 %tmp1 = load <4 x i16>, ptr %A79 %tmp2 = load <4 x i16>, ptr %B80 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)81 ret <4 x i16> %tmp382}83 84define <8 x i16> @uhsub8h(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: uhsub8h:86;CHECK: uhsub.8h87 %tmp1 = load <8 x i16>, ptr %A88 %tmp2 = load <8 x i16>, ptr %B89 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)90 ret <8 x i16> %tmp391}92 93define <2 x i32> @uhsub2s(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: uhsub2s:95;CHECK: uhsub.2s96 %tmp1 = load <2 x i32>, ptr %A97 %tmp2 = load <2 x i32>, ptr %B98 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)99 ret <2 x i32> %tmp3100}101 102define <4 x i32> @uhsub4s(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: uhsub4s:104;CHECK: uhsub.4s105 %tmp1 = load <4 x i32>, ptr %A106 %tmp2 = load <4 x i32>, ptr %B107 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)108 ret <4 x i32> %tmp3109}110 111declare <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone112declare <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone113declare <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone114 115declare <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone116declare <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone117declare <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone118 119declare <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone120declare <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone121declare <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone122 123declare <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone124declare <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone125declare <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone126