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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {6; CHECK-LABEL: xtn8b:7; CHECK: // %bb.0:8; CHECK-NEXT: xtn.8b v0, v09; CHECK-NEXT: ret10 %tmp3 = trunc <8 x i16> %A to <8 x i8>11 ret <8 x i8> %tmp312}13 14define <4 x i16> @xtn4h(<4 x i32> %A) nounwind {15; CHECK-LABEL: xtn4h:16; CHECK: // %bb.0:17; CHECK-NEXT: xtn.4h v0, v018; CHECK-NEXT: ret19 %tmp3 = trunc <4 x i32> %A to <4 x i16>20 ret <4 x i16> %tmp321}22 23define <2 x i32> @xtn2s(<2 x i64> %A) nounwind {24; CHECK-LABEL: xtn2s:25; CHECK: // %bb.0:26; CHECK-NEXT: xtn.2s v0, v027; CHECK-NEXT: ret28 %tmp3 = trunc <2 x i64> %A to <2 x i32>29 ret <2 x i32> %tmp330}31 32define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {33; CHECK-LABEL: xtn2_16b:34; CHECK: // %bb.0:35; CHECK-NEXT: // kill: def $d0 killed $d0 def $q036; CHECK-NEXT: xtn2.16b v0, v137; CHECK-NEXT: ret38 %tmp3 = trunc <8 x i16> %A to <8 x i8>39 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>40 ret <16 x i8> %res41}42 43define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {44; CHECK-LABEL: xtn2_8h:45; CHECK: // %bb.0:46; CHECK-NEXT: // kill: def $d0 killed $d0 def $q047; CHECK-NEXT: xtn2.8h v0, v148; CHECK-NEXT: ret49 %tmp3 = trunc <4 x i32> %A to <4 x i16>50 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>51 ret <8 x i16> %res52}53 54define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {55; CHECK-LABEL: xtn2_4s:56; CHECK: // %bb.0:57; CHECK-NEXT: // kill: def $d0 killed $d0 def $q058; CHECK-NEXT: xtn2.4s v0, v159; CHECK-NEXT: ret60 %tmp3 = trunc <2 x i64> %A to <2 x i32>61 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>62 ret <4 x i32> %res63}64 65define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind {66; CHECK-LABEL: sqxtn8b:67; CHECK: // %bb.0:68; CHECK-NEXT: sqxtn.8b v0, v069; CHECK-NEXT: ret70 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)71 ret <8 x i8> %tmp372}73 74define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind {75; CHECK-LABEL: sqxtn4h:76; CHECK: // %bb.0:77; CHECK-NEXT: sqxtn.4h v0, v078; CHECK-NEXT: ret79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)80 ret <4 x i16> %tmp381}82 83define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind {84; CHECK-LABEL: sqxtn2s:85; CHECK: // %bb.0:86; CHECK-NEXT: sqxtn.2s v0, v087; CHECK-NEXT: ret88 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)89 ret <2 x i32> %tmp390}91 92define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {93; CHECK-LABEL: sqxtn2_16b:94; CHECK: // %bb.0:95; CHECK-NEXT: // kill: def $d0 killed $d0 def $q096; CHECK-NEXT: sqxtn2.16b v0, v197; CHECK-NEXT: ret98 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)99 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>100 ret <16 x i8> %res101}102 103define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {104; CHECK-LABEL: sqxtn2_8h:105; CHECK: // %bb.0:106; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0107; CHECK-NEXT: sqxtn2.8h v0, v1108; CHECK-NEXT: ret109 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)110 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>111 ret <8 x i16> %res112}113 114define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {115; CHECK-LABEL: sqxtn2_4s:116; CHECK: // %bb.0:117; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0118; CHECK-NEXT: sqxtn2.4s v0, v1119; CHECK-NEXT: ret120 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)121 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>122 ret <4 x i32> %res123}124 125declare <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone126declare <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone127declare <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone128 129define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind {130; CHECK-LABEL: uqxtn8b:131; CHECK: // %bb.0:132; CHECK-NEXT: uqxtn.8b v0, v0133; CHECK-NEXT: ret134 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)135 ret <8 x i8> %tmp3136}137 138define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind {139; CHECK-LABEL: uqxtn4h:140; CHECK: // %bb.0:141; CHECK-NEXT: uqxtn.4h v0, v0142; CHECK-NEXT: ret143 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)144 ret <4 x i16> %tmp3145}146 147define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind {148; CHECK-LABEL: uqxtn2s:149; CHECK: // %bb.0:150; CHECK-NEXT: uqxtn.2s v0, v0151; CHECK-NEXT: ret152 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)153 ret <2 x i32> %tmp3154}155 156define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {157; CHECK-LABEL: uqxtn2_16b:158; CHECK: // %bb.0:159; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0160; CHECK-NEXT: uqxtn2.16b v0, v1161; CHECK-NEXT: ret162 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)163 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>164 ret <16 x i8> %res165}166 167define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {168; CHECK-LABEL: uqxtn2_8h:169; CHECK: // %bb.0:170; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0171; CHECK-NEXT: uqxtn2.8h v0, v1172; CHECK-NEXT: ret173 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)174 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>175 ret <8 x i16> %res176}177 178define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {179; CHECK-LABEL: uqxtn2_4s:180; CHECK: // %bb.0:181; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0182; CHECK-NEXT: uqxtn2.4s v0, v1183; CHECK-NEXT: ret184 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)185 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>186 ret <4 x i32> %res187}188 189declare <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone190declare <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone191declare <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone192 193define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind {194; CHECK-LABEL: sqxtun8b:195; CHECK: // %bb.0:196; CHECK-NEXT: sqxtun.8b v0, v0197; CHECK-NEXT: ret198 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)199 ret <8 x i8> %tmp3200}201 202define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind {203; CHECK-LABEL: sqxtun4h:204; CHECK: // %bb.0:205; CHECK-NEXT: sqxtun.4h v0, v0206; CHECK-NEXT: ret207 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)208 ret <4 x i16> %tmp3209}210 211define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind {212; CHECK-LABEL: sqxtun2s:213; CHECK: // %bb.0:214; CHECK-NEXT: sqxtun.2s v0, v0215; CHECK-NEXT: ret216 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)217 ret <2 x i32> %tmp3218}219 220define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {221; CHECK-LABEL: sqxtun2_16b:222; CHECK: // %bb.0:223; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0224; CHECK-NEXT: sqxtun2.16b v0, v1225; CHECK-NEXT: ret226 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)227 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>228 ret <16 x i8> %res229}230 231define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {232; CHECK-LABEL: sqxtun2_8h:233; CHECK: // %bb.0:234; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0235; CHECK-NEXT: sqxtun2.8h v0, v1236; CHECK-NEXT: ret237 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)238 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>239 ret <8 x i16> %res240}241 242define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {243; CHECK-LABEL: sqxtun2_4s:244; CHECK: // %bb.0:245; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0246; CHECK-NEXT: sqxtun2.4s v0, v1247; CHECK-NEXT: ret248 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)249 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>250 ret <4 x i32> %res251}252 253declare <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone254declare <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone255declare <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone256 257;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:258; CHECK-GI: {{.*}}259; CHECK-SD: {{.*}}260