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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s3 4define <8 x i8> @sqadd8b(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: sqadd8b:6; CHECK: // %bb.0:7; CHECK-NEXT: ldr d0, [x0]8; CHECK-NEXT: ldr d1, [x1]9; CHECK-NEXT: sqadd.8b v0, v0, v110; CHECK-NEXT: ret11 %tmp1 = load <8 x i8>, ptr %A12 %tmp2 = load <8 x i8>, ptr %B13 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)14 ret <8 x i8> %tmp315}16 17define <4 x i16> @sqadd4h(ptr %A, ptr %B) nounwind {18; CHECK-LABEL: sqadd4h:19; CHECK: // %bb.0:20; CHECK-NEXT: ldr d0, [x0]21; CHECK-NEXT: ldr d1, [x1]22; CHECK-NEXT: sqadd.4h v0, v0, v123; CHECK-NEXT: ret24 %tmp1 = load <4 x i16>, ptr %A25 %tmp2 = load <4 x i16>, ptr %B26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)27 ret <4 x i16> %tmp328}29 30define <2 x i32> @sqadd2s(ptr %A, ptr %B) nounwind {31; CHECK-LABEL: sqadd2s:32; CHECK: // %bb.0:33; CHECK-NEXT: ldr d0, [x0]34; CHECK-NEXT: ldr d1, [x1]35; CHECK-NEXT: sqadd.2s v0, v0, v136; CHECK-NEXT: ret37 %tmp1 = load <2 x i32>, ptr %A38 %tmp2 = load <2 x i32>, ptr %B39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)40 ret <2 x i32> %tmp341}42 43define <1 x i64> @sqadd1d(ptr %A, ptr %B) nounwind {44; CHECK-LABEL: sqadd1d:45; CHECK: // %bb.0:46; CHECK-NEXT: ldr d0, [x0]47; CHECK-NEXT: ldr d1, [x1]48; CHECK-NEXT: sqadd d0, d0, d149; CHECK-NEXT: ret50 %tmp1 = load <1 x i64>, ptr %A51 %tmp2 = load <1 x i64>, ptr %B52 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)53 ret <1 x i64> %tmp354}55 56 57define <8 x i8> @uqadd8b(ptr %A, ptr %B) nounwind {58; CHECK-LABEL: uqadd8b:59; CHECK: // %bb.0:60; CHECK-NEXT: ldr d0, [x0]61; CHECK-NEXT: ldr d1, [x1]62; CHECK-NEXT: uqadd.8b v0, v0, v163; CHECK-NEXT: ret64 %tmp1 = load <8 x i8>, ptr %A65 %tmp2 = load <8 x i8>, ptr %B66 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)67 ret <8 x i8> %tmp368}69 70define <4 x i16> @uqadd4h(ptr %A, ptr %B) nounwind {71; CHECK-LABEL: uqadd4h:72; CHECK: // %bb.0:73; CHECK-NEXT: ldr d0, [x0]74; CHECK-NEXT: ldr d1, [x1]75; CHECK-NEXT: uqadd.4h v0, v0, v176; CHECK-NEXT: ret77 %tmp1 = load <4 x i16>, ptr %A78 %tmp2 = load <4 x i16>, ptr %B79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)80 ret <4 x i16> %tmp381}82 83define <2 x i32> @uqadd2s(ptr %A, ptr %B) nounwind {84; CHECK-LABEL: uqadd2s:85; CHECK: // %bb.0:86; CHECK-NEXT: ldr d0, [x0]87; CHECK-NEXT: ldr d1, [x1]88; CHECK-NEXT: uqadd.2s v0, v0, v189; CHECK-NEXT: ret90 %tmp1 = load <2 x i32>, ptr %A91 %tmp2 = load <2 x i32>, ptr %B92 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)93 ret <2 x i32> %tmp394}95 96define <1 x i64> @uqadd1d(ptr %A, ptr %B) nounwind {97; CHECK-LABEL: uqadd1d:98; CHECK: // %bb.0:99; CHECK-NEXT: ldr d0, [x0]100; CHECK-NEXT: ldr d1, [x1]101; CHECK-NEXT: uqadd d0, d0, d1102; CHECK-NEXT: ret103 %tmp1 = load <1 x i64>, ptr %A104 %tmp2 = load <1 x i64>, ptr %B105 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)106 ret <1 x i64> %tmp3107}108 109 110define <16 x i8> @sqadd16b(ptr %A, ptr %B) nounwind {111; CHECK-LABEL: sqadd16b:112; CHECK: // %bb.0:113; CHECK-NEXT: ldr q0, [x0]114; CHECK-NEXT: ldr q1, [x1]115; CHECK-NEXT: sqadd.16b v0, v0, v1116; CHECK-NEXT: ret117 %tmp1 = load <16 x i8>, ptr %A118 %tmp2 = load <16 x i8>, ptr %B119 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)120 ret <16 x i8> %tmp3121}122 123define <8 x i16> @sqadd8h(ptr %A, ptr %B) nounwind {124; CHECK-LABEL: sqadd8h:125; CHECK: // %bb.0:126; CHECK-NEXT: ldr q0, [x0]127; CHECK-NEXT: ldr q1, [x1]128; CHECK-NEXT: sqadd.8h v0, v0, v1129; CHECK-NEXT: ret130 %tmp1 = load <8 x i16>, ptr %A131 %tmp2 = load <8 x i16>, ptr %B132 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)133 ret <8 x i16> %tmp3134}135 136define <4 x i32> @sqadd4s(ptr %A, ptr %B) nounwind {137; CHECK-LABEL: sqadd4s:138; CHECK: // %bb.0:139; CHECK-NEXT: ldr q0, [x0]140; CHECK-NEXT: ldr q1, [x1]141; CHECK-NEXT: sqadd.4s v0, v0, v1142; CHECK-NEXT: ret143 %tmp1 = load <4 x i32>, ptr %A144 %tmp2 = load <4 x i32>, ptr %B145 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)146 ret <4 x i32> %tmp3147}148 149define <2 x i64> @sqadd2d(ptr %A, ptr %B) nounwind {150; CHECK-LABEL: sqadd2d:151; CHECK: // %bb.0:152; CHECK-NEXT: ldr q0, [x0]153; CHECK-NEXT: ldr q1, [x1]154; CHECK-NEXT: sqadd.2d v0, v0, v1155; CHECK-NEXT: ret156 %tmp1 = load <2 x i64>, ptr %A157 %tmp2 = load <2 x i64>, ptr %B158 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)159 ret <2 x i64> %tmp3160}161 162 163define <16 x i8> @uqadd16b(ptr %A, ptr %B) nounwind {164; CHECK-LABEL: uqadd16b:165; CHECK: // %bb.0:166; CHECK-NEXT: ldr q0, [x0]167; CHECK-NEXT: ldr q1, [x1]168; CHECK-NEXT: uqadd.16b v0, v0, v1169; CHECK-NEXT: ret170 %tmp1 = load <16 x i8>, ptr %A171 %tmp2 = load <16 x i8>, ptr %B172 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)173 ret <16 x i8> %tmp3174}175 176define <8 x i16> @uqadd8h(ptr %A, ptr %B) nounwind {177; CHECK-LABEL: uqadd8h:178; CHECK: // %bb.0:179; CHECK-NEXT: ldr q0, [x0]180; CHECK-NEXT: ldr q1, [x1]181; CHECK-NEXT: uqadd.8h v0, v0, v1182; CHECK-NEXT: ret183 %tmp1 = load <8 x i16>, ptr %A184 %tmp2 = load <8 x i16>, ptr %B185 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)186 ret <8 x i16> %tmp3187}188 189define <4 x i32> @uqadd4s(ptr %A, ptr %B) nounwind {190; CHECK-LABEL: uqadd4s:191; CHECK: // %bb.0:192; CHECK-NEXT: ldr q0, [x0]193; CHECK-NEXT: ldr q1, [x1]194; CHECK-NEXT: uqadd.4s v0, v0, v1195; CHECK-NEXT: ret196 %tmp1 = load <4 x i32>, ptr %A197 %tmp2 = load <4 x i32>, ptr %B198 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)199 ret <4 x i32> %tmp3200}201 202define <2 x i64> @uqadd2d(ptr %A, ptr %B) nounwind {203; CHECK-LABEL: uqadd2d:204; CHECK: // %bb.0:205; CHECK-NEXT: ldr q0, [x0]206; CHECK-NEXT: ldr q1, [x1]207; CHECK-NEXT: uqadd.2d v0, v0, v1208; CHECK-NEXT: ret209 %tmp1 = load <2 x i64>, ptr %A210 %tmp2 = load <2 x i64>, ptr %B211 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)212 ret <2 x i64> %tmp3213}214 215declare <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone216declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone217declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone218declare <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone219 220declare <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone221declare <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone222declare <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone223declare <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone224 225declare <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone226declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone227declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone228declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone229 230declare <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone231declare <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone232declare <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone233declare <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone234 235define <8 x i8> @usqadd8b(ptr %A, ptr %B) nounwind {236; CHECK-LABEL: usqadd8b:237; CHECK: // %bb.0:238; CHECK-NEXT: ldr d0, [x0]239; CHECK-NEXT: ldr d1, [x1]240; CHECK-NEXT: usqadd.8b v0, v1241; CHECK-NEXT: ret242 %tmp1 = load <8 x i8>, ptr %A243 %tmp2 = load <8 x i8>, ptr %B244 %tmp3 = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)245 ret <8 x i8> %tmp3246}247 248define <4 x i16> @usqadd4h(ptr %A, ptr %B) nounwind {249; CHECK-LABEL: usqadd4h:250; CHECK: // %bb.0:251; CHECK-NEXT: ldr d0, [x0]252; CHECK-NEXT: ldr d1, [x1]253; CHECK-NEXT: usqadd.4h v0, v1254; CHECK-NEXT: ret255 %tmp1 = load <4 x i16>, ptr %A256 %tmp2 = load <4 x i16>, ptr %B257 %tmp3 = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)258 ret <4 x i16> %tmp3259}260 261define <2 x i32> @usqadd2s(ptr %A, ptr %B) nounwind {262; CHECK-LABEL: usqadd2s:263; CHECK: // %bb.0:264; CHECK-NEXT: ldr d0, [x0]265; CHECK-NEXT: ldr d1, [x1]266; CHECK-NEXT: usqadd.2s v0, v1267; CHECK-NEXT: ret268 %tmp1 = load <2 x i32>, ptr %A269 %tmp2 = load <2 x i32>, ptr %B270 %tmp3 = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)271 ret <2 x i32> %tmp3272}273 274define <1 x i64> @usqadd1d(ptr %A, ptr %B) nounwind {275; CHECK-LABEL: usqadd1d:276; CHECK: // %bb.0:277; CHECK-NEXT: ldr d0, [x0]278; CHECK-NEXT: ldr d1, [x1]279; CHECK-NEXT: usqadd d0, d1280; CHECK-NEXT: ret281 %tmp1 = load <1 x i64>, ptr %A282 %tmp2 = load <1 x i64>, ptr %B283 %tmp3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)284 ret <1 x i64> %tmp3285}286 287 288define <16 x i8> @usqadd16b(ptr %A, ptr %B) nounwind {289; CHECK-LABEL: usqadd16b:290; CHECK: // %bb.0:291; CHECK-NEXT: ldr q0, [x0]292; CHECK-NEXT: ldr q1, [x1]293; CHECK-NEXT: usqadd.16b v0, v1294; CHECK-NEXT: ret295 %tmp1 = load <16 x i8>, ptr %A296 %tmp2 = load <16 x i8>, ptr %B297 %tmp3 = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)298 ret <16 x i8> %tmp3299}300 301define <8 x i16> @usqadd8h(ptr %A, ptr %B) nounwind {302; CHECK-LABEL: usqadd8h:303; CHECK: // %bb.0:304; CHECK-NEXT: ldr q0, [x0]305; CHECK-NEXT: ldr q1, [x1]306; CHECK-NEXT: usqadd.8h v0, v1307; CHECK-NEXT: ret308 %tmp1 = load <8 x i16>, ptr %A309 %tmp2 = load <8 x i16>, ptr %B310 %tmp3 = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)311 ret <8 x i16> %tmp3312}313 314define <4 x i32> @usqadd4s(ptr %A, ptr %B) nounwind {315; CHECK-LABEL: usqadd4s:316; CHECK: // %bb.0:317; CHECK-NEXT: ldr q0, [x0]318; CHECK-NEXT: ldr q1, [x1]319; CHECK-NEXT: usqadd.4s v0, v1320; CHECK-NEXT: ret321 %tmp1 = load <4 x i32>, ptr %A322 %tmp2 = load <4 x i32>, ptr %B323 %tmp3 = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)324 ret <4 x i32> %tmp3325}326 327define <2 x i64> @usqadd2d(ptr %A, ptr %B) nounwind {328; CHECK-LABEL: usqadd2d:329; CHECK: // %bb.0:330; CHECK-NEXT: ldr q0, [x0]331; CHECK-NEXT: ldr q1, [x1]332; CHECK-NEXT: usqadd.2d v0, v1333; CHECK-NEXT: ret334 %tmp1 = load <2 x i64>, ptr %A335 %tmp2 = load <2 x i64>, ptr %B336 %tmp3 = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)337 ret <2 x i64> %tmp3338}339 340define i64 @usqadd_d(i64 %l, i64 %r) nounwind {341; CHECK-LABEL: usqadd_d:342; CHECK: // %bb.0:343; CHECK-NEXT: fmov d0, x0344; CHECK-NEXT: fmov d1, x1345; CHECK-NEXT: usqadd d0, d1346; CHECK-NEXT: fmov x0, d0347; CHECK-NEXT: ret348 %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %l, i64 %r)349 ret i64 %sum350}351 352define i32 @usqadd_s(i32 %l, i32 %r) nounwind {353; CHECK-LABEL: usqadd_s:354; CHECK: // %bb.0:355; CHECK-NEXT: fmov s0, w0356; CHECK-NEXT: fmov s1, w1357; CHECK-NEXT: usqadd s0, s1358; CHECK-NEXT: fmov w0, s0359; CHECK-NEXT: ret360 %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %l, i32 %r)361 ret i32 %sum362}363 364declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone365declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone366declare <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone367declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone368declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) nounwind readnone369declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) nounwind readnone370 371declare <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone372declare <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone373declare <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone374declare <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone375 376 377define <8 x i8> @suqadd8b(ptr %A, ptr %B) nounwind {378; CHECK-LABEL: suqadd8b:379; CHECK: // %bb.0:380; CHECK-NEXT: ldr d0, [x0]381; CHECK-NEXT: ldr d1, [x1]382; CHECK-NEXT: suqadd.8b v0, v1383; CHECK-NEXT: ret384 %tmp1 = load <8 x i8>, ptr %A385 %tmp2 = load <8 x i8>, ptr %B386 %tmp3 = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)387 ret <8 x i8> %tmp3388}389 390define <4 x i16> @suqadd4h(ptr %A, ptr %B) nounwind {391; CHECK-LABEL: suqadd4h:392; CHECK: // %bb.0:393; CHECK-NEXT: ldr d0, [x0]394; CHECK-NEXT: ldr d1, [x1]395; CHECK-NEXT: suqadd.4h v0, v1396; CHECK-NEXT: ret397 %tmp1 = load <4 x i16>, ptr %A398 %tmp2 = load <4 x i16>, ptr %B399 %tmp3 = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)400 ret <4 x i16> %tmp3401}402 403define <2 x i32> @suqadd2s(ptr %A, ptr %B) nounwind {404; CHECK-LABEL: suqadd2s:405; CHECK: // %bb.0:406; CHECK-NEXT: ldr d0, [x0]407; CHECK-NEXT: ldr d1, [x1]408; CHECK-NEXT: suqadd.2s v0, v1409; CHECK-NEXT: ret410 %tmp1 = load <2 x i32>, ptr %A411 %tmp2 = load <2 x i32>, ptr %B412 %tmp3 = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)413 ret <2 x i32> %tmp3414}415 416define <1 x i64> @suqadd1d(ptr %A, ptr %B) nounwind {417; CHECK-LABEL: suqadd1d:418; CHECK: // %bb.0:419; CHECK-NEXT: ldr d0, [x0]420; CHECK-NEXT: ldr d1, [x1]421; CHECK-NEXT: suqadd d0, d1422; CHECK-NEXT: ret423 %tmp1 = load <1 x i64>, ptr %A424 %tmp2 = load <1 x i64>, ptr %B425 %tmp3 = call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)426 ret <1 x i64> %tmp3427}428 429 430define <16 x i8> @suqadd16b(ptr %A, ptr %B) nounwind {431; CHECK-LABEL: suqadd16b:432; CHECK: // %bb.0:433; CHECK-NEXT: ldr q0, [x0]434; CHECK-NEXT: ldr q1, [x1]435; CHECK-NEXT: suqadd.16b v0, v1436; CHECK-NEXT: ret437 %tmp1 = load <16 x i8>, ptr %A438 %tmp2 = load <16 x i8>, ptr %B439 %tmp3 = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)440 ret <16 x i8> %tmp3441}442 443define <8 x i16> @suqadd8h(ptr %A, ptr %B) nounwind {444; CHECK-LABEL: suqadd8h:445; CHECK: // %bb.0:446; CHECK-NEXT: ldr q0, [x0]447; CHECK-NEXT: ldr q1, [x1]448; CHECK-NEXT: suqadd.8h v0, v1449; CHECK-NEXT: ret450 %tmp1 = load <8 x i16>, ptr %A451 %tmp2 = load <8 x i16>, ptr %B452 %tmp3 = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)453 ret <8 x i16> %tmp3454}455 456define <4 x i32> @suqadd4s(ptr %A, ptr %B) nounwind {457; CHECK-LABEL: suqadd4s:458; CHECK: // %bb.0:459; CHECK-NEXT: ldr q0, [x0]460; CHECK-NEXT: ldr q1, [x1]461; CHECK-NEXT: suqadd.4s v0, v1462; CHECK-NEXT: ret463 %tmp1 = load <4 x i32>, ptr %A464 %tmp2 = load <4 x i32>, ptr %B465 %tmp3 = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)466 ret <4 x i32> %tmp3467}468 469define <2 x i64> @suqadd2d(ptr %A, ptr %B) nounwind {470; CHECK-LABEL: suqadd2d:471; CHECK: // %bb.0:472; CHECK-NEXT: ldr q0, [x0]473; CHECK-NEXT: ldr q1, [x1]474; CHECK-NEXT: suqadd.2d v0, v1475; CHECK-NEXT: ret476 %tmp1 = load <2 x i64>, ptr %A477 %tmp2 = load <2 x i64>, ptr %B478 %tmp3 = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)479 ret <2 x i64> %tmp3480}481 482define i64 @suqadd_d(i64 %l, i64 %r) nounwind {483; CHECK-LABEL: suqadd_d:484; CHECK: // %bb.0:485; CHECK-NEXT: fmov d0, x0486; CHECK-NEXT: fmov d1, x1487; CHECK-NEXT: suqadd d0, d1488; CHECK-NEXT: fmov x0, d0489; CHECK-NEXT: ret490 %sum = call i64 @llvm.aarch64.neon.suqadd.i64(i64 %l, i64 %r)491 ret i64 %sum492}493 494define i32 @suqadd_s(i32 %l, i32 %r) nounwind {495; CHECK-LABEL: suqadd_s:496; CHECK: // %bb.0:497; CHECK-NEXT: fmov s0, w0498; CHECK-NEXT: fmov s1, w1499; CHECK-NEXT: suqadd s0, s1500; CHECK-NEXT: fmov w0, s0501; CHECK-NEXT: ret502 %sum = call i32 @llvm.aarch64.neon.suqadd.i32(i32 %l, i32 %r)503 ret i32 %sum504}505 506declare <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone507declare <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone508declare <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone509declare <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone510declare i64 @llvm.aarch64.neon.suqadd.i64(i64, i64) nounwind readnone511declare i32 @llvm.aarch64.neon.suqadd.i32(i32, i32) nounwind readnone512 513declare <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone514declare <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone515declare <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone516declare <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone517