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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s3 4define <8 x i8> @sqsub8b(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: sqsub8b:6; CHECK: // %bb.0:7; CHECK-NEXT: ldr d0, [x0]8; CHECK-NEXT: ldr d1, [x1]9; CHECK-NEXT: sqsub.8b v0, v0, v110; CHECK-NEXT: ret11 %tmp1 = load <8 x i8>, ptr %A12 %tmp2 = load <8 x i8>, ptr %B13 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)14 ret <8 x i8> %tmp315}16 17define <4 x i16> @sqsub4h(ptr %A, ptr %B) nounwind {18; CHECK-LABEL: sqsub4h:19; CHECK: // %bb.0:20; CHECK-NEXT: ldr d0, [x0]21; CHECK-NEXT: ldr d1, [x1]22; CHECK-NEXT: sqsub.4h v0, v0, v123; CHECK-NEXT: ret24 %tmp1 = load <4 x i16>, ptr %A25 %tmp2 = load <4 x i16>, ptr %B26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)27 ret <4 x i16> %tmp328}29 30define <2 x i32> @sqsub2s(ptr %A, ptr %B) nounwind {31; CHECK-LABEL: sqsub2s:32; CHECK: // %bb.0:33; CHECK-NEXT: ldr d0, [x0]34; CHECK-NEXT: ldr d1, [x1]35; CHECK-NEXT: sqsub.2s v0, v0, v136; CHECK-NEXT: ret37 %tmp1 = load <2 x i32>, ptr %A38 %tmp2 = load <2 x i32>, ptr %B39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)40 ret <2 x i32> %tmp341}42 43define <1 x i64> @sqsub1d(ptr %A, ptr %B) nounwind {44; CHECK-LABEL: sqsub1d:45; CHECK: // %bb.0:46; CHECK-NEXT: ldr d0, [x0]47; CHECK-NEXT: ldr d1, [x1]48; CHECK-NEXT: sqsub d0, d0, d149; CHECK-NEXT: ret50 %tmp1 = load <1 x i64>, ptr %A51 %tmp2 = load <1 x i64>, ptr %B52 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)53 ret <1 x i64> %tmp354}55 56 57define <8 x i8> @uqsub8b(ptr %A, ptr %B) nounwind {58; CHECK-LABEL: uqsub8b:59; CHECK: // %bb.0:60; CHECK-NEXT: ldr d0, [x0]61; CHECK-NEXT: ldr d1, [x1]62; CHECK-NEXT: uqsub.8b v0, v0, v163; CHECK-NEXT: ret64 %tmp1 = load <8 x i8>, ptr %A65 %tmp2 = load <8 x i8>, ptr %B66 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)67 ret <8 x i8> %tmp368}69 70define <4 x i16> @uqsub4h(ptr %A, ptr %B) nounwind {71; CHECK-LABEL: uqsub4h:72; CHECK: // %bb.0:73; CHECK-NEXT: ldr d0, [x0]74; CHECK-NEXT: ldr d1, [x1]75; CHECK-NEXT: uqsub.4h v0, v0, v176; CHECK-NEXT: ret77 %tmp1 = load <4 x i16>, ptr %A78 %tmp2 = load <4 x i16>, ptr %B79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)80 ret <4 x i16> %tmp381}82 83define <2 x i32> @uqsub2s(ptr %A, ptr %B) nounwind {84; CHECK-LABEL: uqsub2s:85; CHECK: // %bb.0:86; CHECK-NEXT: ldr d0, [x0]87; CHECK-NEXT: ldr d1, [x1]88; CHECK-NEXT: uqsub.2s v0, v0, v189; CHECK-NEXT: ret90 %tmp1 = load <2 x i32>, ptr %A91 %tmp2 = load <2 x i32>, ptr %B92 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)93 ret <2 x i32> %tmp394}95 96define <1 x i64> @uqsub1d(ptr %A, ptr %B) nounwind {97; CHECK-LABEL: uqsub1d:98; CHECK: // %bb.0:99; CHECK-NEXT: ldr d0, [x0]100; CHECK-NEXT: ldr d1, [x1]101; CHECK-NEXT: uqsub d0, d0, d1102; CHECK-NEXT: ret103 %tmp1 = load <1 x i64>, ptr %A104 %tmp2 = load <1 x i64>, ptr %B105 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)106 ret <1 x i64> %tmp3107}108 109 110define <16 x i8> @sqsub16b(ptr %A, ptr %B) nounwind {111; CHECK-LABEL: sqsub16b:112; CHECK: // %bb.0:113; CHECK-NEXT: ldr q0, [x0]114; CHECK-NEXT: ldr q1, [x1]115; CHECK-NEXT: sqsub.16b v0, v0, v1116; CHECK-NEXT: ret117 %tmp1 = load <16 x i8>, ptr %A118 %tmp2 = load <16 x i8>, ptr %B119 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)120 ret <16 x i8> %tmp3121}122 123define <8 x i16> @sqsub8h(ptr %A, ptr %B) nounwind {124; CHECK-LABEL: sqsub8h:125; CHECK: // %bb.0:126; CHECK-NEXT: ldr q0, [x0]127; CHECK-NEXT: ldr q1, [x1]128; CHECK-NEXT: sqsub.8h v0, v0, v1129; CHECK-NEXT: ret130 %tmp1 = load <8 x i16>, ptr %A131 %tmp2 = load <8 x i16>, ptr %B132 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)133 ret <8 x i16> %tmp3134}135 136define <4 x i32> @sqsub4s(ptr %A, ptr %B) nounwind {137; CHECK-LABEL: sqsub4s:138; CHECK: // %bb.0:139; CHECK-NEXT: ldr q0, [x0]140; CHECK-NEXT: ldr q1, [x1]141; CHECK-NEXT: sqsub.4s v0, v0, v1142; CHECK-NEXT: ret143 %tmp1 = load <4 x i32>, ptr %A144 %tmp2 = load <4 x i32>, ptr %B145 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)146 ret <4 x i32> %tmp3147}148 149define <2 x i64> @sqsub2d(ptr %A, ptr %B) nounwind {150; CHECK-LABEL: sqsub2d:151; CHECK: // %bb.0:152; CHECK-NEXT: ldr q0, [x0]153; CHECK-NEXT: ldr q1, [x1]154; CHECK-NEXT: sqsub.2d v0, v0, v1155; CHECK-NEXT: ret156 %tmp1 = load <2 x i64>, ptr %A157 %tmp2 = load <2 x i64>, ptr %B158 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)159 ret <2 x i64> %tmp3160}161 162 163define <16 x i8> @uqsub16b(ptr %A, ptr %B) nounwind {164; CHECK-LABEL: uqsub16b:165; CHECK: // %bb.0:166; CHECK-NEXT: ldr q0, [x0]167; CHECK-NEXT: ldr q1, [x1]168; CHECK-NEXT: uqsub.16b v0, v0, v1169; CHECK-NEXT: ret170 %tmp1 = load <16 x i8>, ptr %A171 %tmp2 = load <16 x i8>, ptr %B172 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)173 ret <16 x i8> %tmp3174}175 176define <8 x i16> @uqsub8h(ptr %A, ptr %B) nounwind {177; CHECK-LABEL: uqsub8h:178; CHECK: // %bb.0:179; CHECK-NEXT: ldr q0, [x0]180; CHECK-NEXT: ldr q1, [x1]181; CHECK-NEXT: uqsub.8h v0, v0, v1182; CHECK-NEXT: ret183 %tmp1 = load <8 x i16>, ptr %A184 %tmp2 = load <8 x i16>, ptr %B185 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)186 ret <8 x i16> %tmp3187}188 189define <4 x i32> @uqsub4s(ptr %A, ptr %B) nounwind {190; CHECK-LABEL: uqsub4s:191; CHECK: // %bb.0:192; CHECK-NEXT: ldr q0, [x0]193; CHECK-NEXT: ldr q1, [x1]194; CHECK-NEXT: uqsub.4s v0, v0, v1195; CHECK-NEXT: ret196 %tmp1 = load <4 x i32>, ptr %A197 %tmp2 = load <4 x i32>, ptr %B198 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)199 ret <4 x i32> %tmp3200}201 202define <2 x i64> @uqsub2d(ptr %A, ptr %B) nounwind {203; CHECK-LABEL: uqsub2d:204; CHECK: // %bb.0:205; CHECK-NEXT: ldr q0, [x0]206; CHECK-NEXT: ldr q1, [x1]207; CHECK-NEXT: uqsub.2d v0, v0, v1208; CHECK-NEXT: ret209 %tmp1 = load <2 x i64>, ptr %A210 %tmp2 = load <2 x i64>, ptr %B211 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)212 ret <2 x i64> %tmp3213}214 215declare <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone216declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone217declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone218declare <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone219 220declare <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone221declare <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone222declare <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone223declare <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone224 225declare <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone226declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone227declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone228declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone229 230declare <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone231declare <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone232declare <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone233declare <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone234