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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI:       warning: Instruction selection used fallback path for sqshl1d6; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl1d_constant7; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl_scalar8; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl_scalar_constant9; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl1d10; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl1d_constant11; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl_scalar12; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl_scalar_constant13; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshl1d14; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshl1d_constant15; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshl_scalar16; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshl_scalar_constant17; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshl1d18; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshl1d_constant19; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshl_scalar20; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshl_scalar_constant21; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshl1d22; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshl1d_constant23; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshl_scalar24; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshl_scalar_constant25; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshl1d26; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshl1d_constant27; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshl_scalar28; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshl_scalar_constant29; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshr1d30; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for urshr_scalar31; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshr1d32; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srshr_scalar33; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu8b34; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu4h35; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu2s36; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu16b37; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu8h38; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu4s39; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu2d40; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu1d_constant41; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu_i64_constant42; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu_i32_constant43; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn1s44; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn8b45; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn4h46; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn2s47; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn16b48; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn8h49; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrn4s50; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun1s51; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun8b52; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun4h53; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun2s54; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun16b55; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun8h56; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshrun4s57; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn1s58; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn8b59; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn4h60; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn2s61; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn16b62; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn8h63; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrn4s64; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun1s65; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun8b66; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun4h67; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun2s68; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun16b69; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun8h70; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqrshrun4s71; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn1s72; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn8b73; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn4h74; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn2s75; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn16b76; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn8h77; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqrshrn4s78; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn1s79; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn8b80; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn4h81; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn2s82; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn16b83; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn8h84; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshrn4s85; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for neon_ushl_vscalar_constant_shift86; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for neon_ushl_scalar_constant_shift87; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for neon_sshll_vscalar_constant_shift88; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift89; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift_m190; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for ursra1d91; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for ursra_scalar92; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srsra1d93; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for srsra_scalar94; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli8b95; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli4h96; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli2s97; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli1d98; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli1d_imm099; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli16b100; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli8h101; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli4s102; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sli2d103; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshlu_zero_shift_amount104 105define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {106; CHECK-LABEL: sqshl8b:107; CHECK:       // %bb.0:108; CHECK-NEXT:    ldr d0, [x0]109; CHECK-NEXT:    ldr d1, [x1]110; CHECK-NEXT:    sqshl v0.8b, v0.8b, v1.8b111; CHECK-NEXT:    ret112  %tmp1 = load <8 x i8>, ptr %A113  %tmp2 = load <8 x i8>, ptr %B114  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)115  ret <8 x i8> %tmp3116}117 118define <4 x i16> @sqshl4h(ptr %A, ptr %B) nounwind {119; CHECK-LABEL: sqshl4h:120; CHECK:       // %bb.0:121; CHECK-NEXT:    ldr d0, [x0]122; CHECK-NEXT:    ldr d1, [x1]123; CHECK-NEXT:    sqshl v0.4h, v0.4h, v1.4h124; CHECK-NEXT:    ret125  %tmp1 = load <4 x i16>, ptr %A126  %tmp2 = load <4 x i16>, ptr %B127  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)128  ret <4 x i16> %tmp3129}130 131define <2 x i32> @sqshl2s(ptr %A, ptr %B) nounwind {132; CHECK-LABEL: sqshl2s:133; CHECK:       // %bb.0:134; CHECK-NEXT:    ldr d0, [x0]135; CHECK-NEXT:    ldr d1, [x1]136; CHECK-NEXT:    sqshl v0.2s, v0.2s, v1.2s137; CHECK-NEXT:    ret138  %tmp1 = load <2 x i32>, ptr %A139  %tmp2 = load <2 x i32>, ptr %B140  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)141  ret <2 x i32> %tmp3142}143 144define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind {145; CHECK-LABEL: sqshl1d:146; CHECK:       // %bb.0:147; CHECK-NEXT:    ldr d0, [x0]148; CHECK-NEXT:    ldr d1, [x1]149; CHECK-NEXT:    sqshl d0, d0, d1150; CHECK-NEXT:    ret151  %tmp1 = load <1 x i64>, ptr %A152  %tmp2 = load <1 x i64>, ptr %B153  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)154  ret <1 x i64> %tmp3155}156 157define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {158; CHECK-LABEL: sqshl1d_constant:159; CHECK:       // %bb.0:160; CHECK-NEXT:    ldr d0, [x0]161; CHECK-NEXT:    sqshl d0, d0, #1162; CHECK-NEXT:    ret163  %tmp1 = load <1 x i64>, ptr %A164  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)165  ret <1 x i64> %tmp3166}167 168define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {169; CHECK-LABEL: sqshl_scalar:170; CHECK:       // %bb.0:171; CHECK-NEXT:    ldr x8, [x0]172; CHECK-NEXT:    ldr x9, [x1]173; CHECK-NEXT:    fmov d0, x8174; CHECK-NEXT:    fmov d1, x9175; CHECK-NEXT:    sqshl d0, d0, d1176; CHECK-NEXT:    fmov x0, d0177; CHECK-NEXT:    ret178  %tmp1 = load i64, ptr %A179  %tmp2 = load i64, ptr %B180  %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)181  ret i64 %tmp3182}183 184define i64 @sqshl_scalar_constant(ptr %A) nounwind {185; CHECK-LABEL: sqshl_scalar_constant:186; CHECK:       // %bb.0:187; CHECK-NEXT:    ldr d0, [x0]188; CHECK-NEXT:    sqshl d0, d0, #1189; CHECK-NEXT:    fmov x0, d0190; CHECK-NEXT:    ret191  %tmp1 = load i64, ptr %A192  %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)193  ret i64 %tmp3194}195 196define <8 x i8> @uqshl8b(ptr %A, ptr %B) nounwind {197; CHECK-LABEL: uqshl8b:198; CHECK:       // %bb.0:199; CHECK-NEXT:    ldr d0, [x0]200; CHECK-NEXT:    ldr d1, [x1]201; CHECK-NEXT:    uqshl v0.8b, v0.8b, v1.8b202; CHECK-NEXT:    ret203  %tmp1 = load <8 x i8>, ptr %A204  %tmp2 = load <8 x i8>, ptr %B205  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)206  ret <8 x i8> %tmp3207}208 209define <4 x i16> @uqshl4h(ptr %A, ptr %B) nounwind {210; CHECK-LABEL: uqshl4h:211; CHECK:       // %bb.0:212; CHECK-NEXT:    ldr d0, [x0]213; CHECK-NEXT:    ldr d1, [x1]214; CHECK-NEXT:    uqshl v0.4h, v0.4h, v1.4h215; CHECK-NEXT:    ret216  %tmp1 = load <4 x i16>, ptr %A217  %tmp2 = load <4 x i16>, ptr %B218  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)219  ret <4 x i16> %tmp3220}221 222define <2 x i32> @uqshl2s(ptr %A, ptr %B) nounwind {223; CHECK-LABEL: uqshl2s:224; CHECK:       // %bb.0:225; CHECK-NEXT:    ldr d0, [x0]226; CHECK-NEXT:    ldr d1, [x1]227; CHECK-NEXT:    uqshl v0.2s, v0.2s, v1.2s228; CHECK-NEXT:    ret229  %tmp1 = load <2 x i32>, ptr %A230  %tmp2 = load <2 x i32>, ptr %B231  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)232  ret <2 x i32> %tmp3233}234 235define <16 x i8> @sqshl16b(ptr %A, ptr %B) nounwind {236; CHECK-LABEL: sqshl16b:237; CHECK:       // %bb.0:238; CHECK-NEXT:    ldr q0, [x0]239; CHECK-NEXT:    ldr q1, [x1]240; CHECK-NEXT:    sqshl v0.16b, v0.16b, v1.16b241; CHECK-NEXT:    ret242  %tmp1 = load <16 x i8>, ptr %A243  %tmp2 = load <16 x i8>, ptr %B244  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)245  ret <16 x i8> %tmp3246}247 248define <8 x i16> @sqshl8h(ptr %A, ptr %B) nounwind {249; CHECK-LABEL: sqshl8h:250; CHECK:       // %bb.0:251; CHECK-NEXT:    ldr q0, [x0]252; CHECK-NEXT:    ldr q1, [x1]253; CHECK-NEXT:    sqshl v0.8h, v0.8h, v1.8h254; CHECK-NEXT:    ret255  %tmp1 = load <8 x i16>, ptr %A256  %tmp2 = load <8 x i16>, ptr %B257  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)258  ret <8 x i16> %tmp3259}260 261define <4 x i32> @sqshl4s(ptr %A, ptr %B) nounwind {262; CHECK-LABEL: sqshl4s:263; CHECK:       // %bb.0:264; CHECK-NEXT:    ldr q0, [x0]265; CHECK-NEXT:    ldr q1, [x1]266; CHECK-NEXT:    sqshl v0.4s, v0.4s, v1.4s267; CHECK-NEXT:    ret268  %tmp1 = load <4 x i32>, ptr %A269  %tmp2 = load <4 x i32>, ptr %B270  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)271  ret <4 x i32> %tmp3272}273 274define <2 x i64> @sqshl2d(ptr %A, ptr %B) nounwind {275; CHECK-LABEL: sqshl2d:276; CHECK:       // %bb.0:277; CHECK-NEXT:    ldr q0, [x0]278; CHECK-NEXT:    ldr q1, [x1]279; CHECK-NEXT:    sqshl v0.2d, v0.2d, v1.2d280; CHECK-NEXT:    ret281  %tmp1 = load <2 x i64>, ptr %A282  %tmp2 = load <2 x i64>, ptr %B283  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)284  ret <2 x i64> %tmp3285}286 287define <16 x i8> @uqshl16b(ptr %A, ptr %B) nounwind {288; CHECK-LABEL: uqshl16b:289; CHECK:       // %bb.0:290; CHECK-NEXT:    ldr q0, [x0]291; CHECK-NEXT:    ldr q1, [x1]292; CHECK-NEXT:    uqshl v0.16b, v0.16b, v1.16b293; CHECK-NEXT:    ret294  %tmp1 = load <16 x i8>, ptr %A295  %tmp2 = load <16 x i8>, ptr %B296  %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)297  ret <16 x i8> %tmp3298}299 300define <8 x i16> @uqshl8h(ptr %A, ptr %B) nounwind {301; CHECK-LABEL: uqshl8h:302; CHECK:       // %bb.0:303; CHECK-NEXT:    ldr q0, [x0]304; CHECK-NEXT:    ldr q1, [x1]305; CHECK-NEXT:    uqshl v0.8h, v0.8h, v1.8h306; CHECK-NEXT:    ret307  %tmp1 = load <8 x i16>, ptr %A308  %tmp2 = load <8 x i16>, ptr %B309  %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)310  ret <8 x i16> %tmp3311}312 313define <4 x i32> @uqshl4s(ptr %A, ptr %B) nounwind {314; CHECK-LABEL: uqshl4s:315; CHECK:       // %bb.0:316; CHECK-NEXT:    ldr q0, [x0]317; CHECK-NEXT:    ldr q1, [x1]318; CHECK-NEXT:    uqshl v0.4s, v0.4s, v1.4s319; CHECK-NEXT:    ret320  %tmp1 = load <4 x i32>, ptr %A321  %tmp2 = load <4 x i32>, ptr %B322  %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)323  ret <4 x i32> %tmp3324}325 326define <2 x i64> @uqshl2d(ptr %A, ptr %B) nounwind {327; CHECK-LABEL: uqshl2d:328; CHECK:       // %bb.0:329; CHECK-NEXT:    ldr q0, [x0]330; CHECK-NEXT:    ldr q1, [x1]331; CHECK-NEXT:    uqshl v0.2d, v0.2d, v1.2d332; CHECK-NEXT:    ret333  %tmp1 = load <2 x i64>, ptr %A334  %tmp2 = load <2 x i64>, ptr %B335  %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)336  ret <2 x i64> %tmp3337}338 339define <1 x i64> @uqshl1d(ptr %A, ptr %B) nounwind {340; CHECK-LABEL: uqshl1d:341; CHECK:       // %bb.0:342; CHECK-NEXT:    ldr d0, [x0]343; CHECK-NEXT:    ldr d1, [x1]344; CHECK-NEXT:    uqshl d0, d0, d1345; CHECK-NEXT:    ret346  %tmp1 = load <1 x i64>, ptr %A347  %tmp2 = load <1 x i64>, ptr %B348  %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)349  ret <1 x i64> %tmp3350}351 352define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {353; CHECK-LABEL: uqshl1d_constant:354; CHECK:       // %bb.0:355; CHECK-NEXT:    ldr d0, [x0]356; CHECK-NEXT:    uqshl d0, d0, #1357; CHECK-NEXT:    ret358  %tmp1 = load <1 x i64>, ptr %A359  %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)360  ret <1 x i64> %tmp3361}362 363define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {364; CHECK-LABEL: uqshl_scalar:365; CHECK:       // %bb.0:366; CHECK-NEXT:    ldr x8, [x0]367; CHECK-NEXT:    ldr x9, [x1]368; CHECK-NEXT:    fmov d0, x8369; CHECK-NEXT:    fmov d1, x9370; CHECK-NEXT:    uqshl d0, d0, d1371; CHECK-NEXT:    fmov x0, d0372; CHECK-NEXT:    ret373  %tmp1 = load i64, ptr %A374  %tmp2 = load i64, ptr %B375  %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)376  ret i64 %tmp3377}378 379define i64 @uqshl_scalar_constant(ptr %A) nounwind {380; CHECK-LABEL: uqshl_scalar_constant:381; CHECK:       // %bb.0:382; CHECK-NEXT:    ldr d0, [x0]383; CHECK-NEXT:    uqshl d0, d0, #1384; CHECK-NEXT:    fmov x0, d0385; CHECK-NEXT:    ret386  %tmp1 = load i64, ptr %A387  %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 1)388  ret i64 %tmp3389}390 391declare <8 x i8>  @llvm.aarch64.neon.sqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone392declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone393declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone394declare <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone395declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64) nounwind readnone396 397 398declare <8 x i8>  @llvm.aarch64.neon.uqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone399declare <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone400declare <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone401declare <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone402declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64) nounwind readnone403 404declare <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone405declare <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone406declare <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone407declare <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone408 409declare <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone410declare <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone411declare <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone412declare <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone413 414define <8 x i8> @srshl8b(ptr %A, ptr %B) nounwind {415; CHECK-LABEL: srshl8b:416; CHECK:       // %bb.0:417; CHECK-NEXT:    ldr d0, [x0]418; CHECK-NEXT:    ldr d1, [x1]419; CHECK-NEXT:    srshl v0.8b, v0.8b, v1.8b420; CHECK-NEXT:    ret421  %tmp1 = load <8 x i8>, ptr %A422  %tmp2 = load <8 x i8>, ptr %B423  %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)424  ret <8 x i8> %tmp3425}426 427define <4 x i16> @srshl4h(ptr %A, ptr %B) nounwind {428; CHECK-LABEL: srshl4h:429; CHECK:       // %bb.0:430; CHECK-NEXT:    ldr d0, [x0]431; CHECK-NEXT:    ldr d1, [x1]432; CHECK-NEXT:    srshl v0.4h, v0.4h, v1.4h433; CHECK-NEXT:    ret434  %tmp1 = load <4 x i16>, ptr %A435  %tmp2 = load <4 x i16>, ptr %B436  %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)437  ret <4 x i16> %tmp3438}439 440define <2 x i32> @srshl2s(ptr %A, ptr %B) nounwind {441; CHECK-LABEL: srshl2s:442; CHECK:       // %bb.0:443; CHECK-NEXT:    ldr d0, [x0]444; CHECK-NEXT:    ldr d1, [x1]445; CHECK-NEXT:    srshl v0.2s, v0.2s, v1.2s446; CHECK-NEXT:    ret447  %tmp1 = load <2 x i32>, ptr %A448  %tmp2 = load <2 x i32>, ptr %B449  %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)450  ret <2 x i32> %tmp3451}452 453define <1 x i64> @srshl1d(ptr %A, ptr %B) nounwind {454; CHECK-LABEL: srshl1d:455; CHECK:       // %bb.0:456; CHECK-NEXT:    ldr d0, [x0]457; CHECK-NEXT:    ldr d1, [x1]458; CHECK-NEXT:    srshl d0, d0, d1459; CHECK-NEXT:    ret460  %tmp1 = load <1 x i64>, ptr %A461  %tmp2 = load <1 x i64>, ptr %B462  %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)463  ret <1 x i64> %tmp3464}465 466define <1 x i64> @srshl1d_constant(ptr %A) nounwind {467; CHECK-LABEL: srshl1d_constant:468; CHECK:       // %bb.0:469; CHECK-NEXT:    mov w8, #1 // =0x1470; CHECK-NEXT:    ldr d0, [x0]471; CHECK-NEXT:    fmov d1, x8472; CHECK-NEXT:    srshl d0, d0, d1473; CHECK-NEXT:    ret474  %tmp1 = load <1 x i64>, ptr %A475  %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)476  ret <1 x i64> %tmp3477}478 479define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {480; CHECK-LABEL: srshl_scalar:481; CHECK:       // %bb.0:482; CHECK-NEXT:    ldr x8, [x0]483; CHECK-NEXT:    ldr x9, [x1]484; CHECK-NEXT:    fmov d0, x8485; CHECK-NEXT:    fmov d1, x9486; CHECK-NEXT:    srshl d0, d0, d1487; CHECK-NEXT:    fmov x0, d0488; CHECK-NEXT:    ret489  %tmp1 = load i64, ptr %A490  %tmp2 = load i64, ptr %B491  %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 %tmp2)492  ret i64 %tmp3493}494 495define i64 @srshl_scalar_constant(ptr %A) nounwind {496; CHECK-LABEL: srshl_scalar_constant:497; CHECK:       // %bb.0:498; CHECK-NEXT:    ldr x9, [x0]499; CHECK-NEXT:    mov w8, #1 // =0x1500; CHECK-NEXT:    fmov d1, x8501; CHECK-NEXT:    fmov d0, x9502; CHECK-NEXT:    srshl d0, d0, d1503; CHECK-NEXT:    fmov x0, d0504; CHECK-NEXT:    ret505  %tmp1 = load i64, ptr %A506  %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 1)507  ret i64 %tmp3508}509 510define <8 x i8> @urshl8b(ptr %A, ptr %B) nounwind {511; CHECK-LABEL: urshl8b:512; CHECK:       // %bb.0:513; CHECK-NEXT:    ldr d0, [x0]514; CHECK-NEXT:    ldr d1, [x1]515; CHECK-NEXT:    urshl v0.8b, v0.8b, v1.8b516; CHECK-NEXT:    ret517  %tmp1 = load <8 x i8>, ptr %A518  %tmp2 = load <8 x i8>, ptr %B519  %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)520  ret <8 x i8> %tmp3521}522 523define <4 x i16> @urshl4h(ptr %A, ptr %B) nounwind {524; CHECK-LABEL: urshl4h:525; CHECK:       // %bb.0:526; CHECK-NEXT:    ldr d0, [x0]527; CHECK-NEXT:    ldr d1, [x1]528; CHECK-NEXT:    urshl v0.4h, v0.4h, v1.4h529; CHECK-NEXT:    ret530  %tmp1 = load <4 x i16>, ptr %A531  %tmp2 = load <4 x i16>, ptr %B532  %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)533  ret <4 x i16> %tmp3534}535 536define <2 x i32> @urshl2s(ptr %A, ptr %B) nounwind {537; CHECK-LABEL: urshl2s:538; CHECK:       // %bb.0:539; CHECK-NEXT:    ldr d0, [x0]540; CHECK-NEXT:    ldr d1, [x1]541; CHECK-NEXT:    urshl v0.2s, v0.2s, v1.2s542; CHECK-NEXT:    ret543  %tmp1 = load <2 x i32>, ptr %A544  %tmp2 = load <2 x i32>, ptr %B545  %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)546  ret <2 x i32> %tmp3547}548 549define <1 x i64> @urshl1d(ptr %A, ptr %B) nounwind {550; CHECK-LABEL: urshl1d:551; CHECK:       // %bb.0:552; CHECK-NEXT:    ldr d0, [x0]553; CHECK-NEXT:    ldr d1, [x1]554; CHECK-NEXT:    urshl d0, d0, d1555; CHECK-NEXT:    ret556  %tmp1 = load <1 x i64>, ptr %A557  %tmp2 = load <1 x i64>, ptr %B558  %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)559  ret <1 x i64> %tmp3560}561 562define <1 x i64> @urshl1d_constant(ptr %A) nounwind {563; CHECK-LABEL: urshl1d_constant:564; CHECK:       // %bb.0:565; CHECK-NEXT:    mov w8, #1 // =0x1566; CHECK-NEXT:    ldr d0, [x0]567; CHECK-NEXT:    fmov d1, x8568; CHECK-NEXT:    urshl d0, d0, d1569; CHECK-NEXT:    ret570  %tmp1 = load <1 x i64>, ptr %A571  %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)572  ret <1 x i64> %tmp3573}574 575define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {576; CHECK-LABEL: urshl_scalar:577; CHECK:       // %bb.0:578; CHECK-NEXT:    ldr x8, [x0]579; CHECK-NEXT:    ldr x9, [x1]580; CHECK-NEXT:    fmov d0, x8581; CHECK-NEXT:    fmov d1, x9582; CHECK-NEXT:    urshl d0, d0, d1583; CHECK-NEXT:    fmov x0, d0584; CHECK-NEXT:    ret585  %tmp1 = load i64, ptr %A586  %tmp2 = load i64, ptr %B587  %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 %tmp2)588  ret i64 %tmp3589}590 591define i64 @urshl_scalar_constant(ptr %A) nounwind {592; CHECK-LABEL: urshl_scalar_constant:593; CHECK:       // %bb.0:594; CHECK-NEXT:    ldr x9, [x0]595; CHECK-NEXT:    mov w8, #1 // =0x1596; CHECK-NEXT:    fmov d1, x8597; CHECK-NEXT:    fmov d0, x9598; CHECK-NEXT:    urshl d0, d0, d1599; CHECK-NEXT:    fmov x0, d0600; CHECK-NEXT:    ret601  %tmp1 = load i64, ptr %A602  %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 1)603  ret i64 %tmp3604}605 606define <16 x i8> @srshl16b(ptr %A, ptr %B) nounwind {607; CHECK-LABEL: srshl16b:608; CHECK:       // %bb.0:609; CHECK-NEXT:    ldr q0, [x0]610; CHECK-NEXT:    ldr q1, [x1]611; CHECK-NEXT:    srshl v0.16b, v0.16b, v1.16b612; CHECK-NEXT:    ret613  %tmp1 = load <16 x i8>, ptr %A614  %tmp2 = load <16 x i8>, ptr %B615  %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)616  ret <16 x i8> %tmp3617}618 619define <8 x i16> @srshl8h(ptr %A, ptr %B) nounwind {620; CHECK-LABEL: srshl8h:621; CHECK:       // %bb.0:622; CHECK-NEXT:    ldr q0, [x0]623; CHECK-NEXT:    ldr q1, [x1]624; CHECK-NEXT:    srshl v0.8h, v0.8h, v1.8h625; CHECK-NEXT:    ret626  %tmp1 = load <8 x i16>, ptr %A627  %tmp2 = load <8 x i16>, ptr %B628  %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)629  ret <8 x i16> %tmp3630}631 632define <4 x i32> @srshl4s(ptr %A, ptr %B) nounwind {633; CHECK-LABEL: srshl4s:634; CHECK:       // %bb.0:635; CHECK-NEXT:    ldr q0, [x0]636; CHECK-NEXT:    ldr q1, [x1]637; CHECK-NEXT:    srshl v0.4s, v0.4s, v1.4s638; CHECK-NEXT:    ret639  %tmp1 = load <4 x i32>, ptr %A640  %tmp2 = load <4 x i32>, ptr %B641  %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)642  ret <4 x i32> %tmp3643}644 645define <2 x i64> @srshl2d(ptr %A, ptr %B) nounwind {646; CHECK-LABEL: srshl2d:647; CHECK:       // %bb.0:648; CHECK-NEXT:    ldr q0, [x0]649; CHECK-NEXT:    ldr q1, [x1]650; CHECK-NEXT:    srshl v0.2d, v0.2d, v1.2d651; CHECK-NEXT:    ret652  %tmp1 = load <2 x i64>, ptr %A653  %tmp2 = load <2 x i64>, ptr %B654  %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)655  ret <2 x i64> %tmp3656}657 658define <16 x i8> @urshl16b(ptr %A, ptr %B) nounwind {659; CHECK-LABEL: urshl16b:660; CHECK:       // %bb.0:661; CHECK-NEXT:    ldr q0, [x0]662; CHECK-NEXT:    ldr q1, [x1]663; CHECK-NEXT:    urshl v0.16b, v0.16b, v1.16b664; CHECK-NEXT:    ret665  %tmp1 = load <16 x i8>, ptr %A666  %tmp2 = load <16 x i8>, ptr %B667  %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)668  ret <16 x i8> %tmp3669}670 671define <8 x i16> @urshl8h(ptr %A, ptr %B) nounwind {672; CHECK-LABEL: urshl8h:673; CHECK:       // %bb.0:674; CHECK-NEXT:    ldr q0, [x0]675; CHECK-NEXT:    ldr q1, [x1]676; CHECK-NEXT:    urshl v0.8h, v0.8h, v1.8h677; CHECK-NEXT:    ret678  %tmp1 = load <8 x i16>, ptr %A679  %tmp2 = load <8 x i16>, ptr %B680  %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)681  ret <8 x i16> %tmp3682}683 684define <4 x i32> @urshl4s(ptr %A, ptr %B) nounwind {685; CHECK-LABEL: urshl4s:686; CHECK:       // %bb.0:687; CHECK-NEXT:    ldr q0, [x0]688; CHECK-NEXT:    ldr q1, [x1]689; CHECK-NEXT:    urshl v0.4s, v0.4s, v1.4s690; CHECK-NEXT:    ret691  %tmp1 = load <4 x i32>, ptr %A692  %tmp2 = load <4 x i32>, ptr %B693  %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)694  ret <4 x i32> %tmp3695}696 697define <2 x i64> @urshl2d(ptr %A, ptr %B) nounwind {698; CHECK-LABEL: urshl2d:699; CHECK:       // %bb.0:700; CHECK-NEXT:    ldr q0, [x0]701; CHECK-NEXT:    ldr q1, [x1]702; CHECK-NEXT:    urshl v0.2d, v0.2d, v1.2d703; CHECK-NEXT:    ret704  %tmp1 = load <2 x i64>, ptr %A705  %tmp2 = load <2 x i64>, ptr %B706  %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)707  ret <2 x i64> %tmp3708}709 710declare <8 x i8>  @llvm.aarch64.neon.srshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone711declare <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone712declare <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone713declare <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone714declare i64 @llvm.aarch64.neon.srshl.i64(i64, i64) nounwind readnone715 716declare <8 x i8>  @llvm.aarch64.neon.urshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone717declare <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone718declare <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone719declare <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone720declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64) nounwind readnone721 722declare <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone723declare <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone724declare <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone725declare <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone726 727declare <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone728declare <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone729declare <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone730declare <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone731 732define <8 x i8> @sqrshl8b(ptr %A, ptr %B) nounwind {733; CHECK-LABEL: sqrshl8b:734; CHECK:       // %bb.0:735; CHECK-NEXT:    ldr d0, [x0]736; CHECK-NEXT:    ldr d1, [x1]737; CHECK-NEXT:    sqrshl v0.8b, v0.8b, v1.8b738; CHECK-NEXT:    ret739  %tmp1 = load <8 x i8>, ptr %A740  %tmp2 = load <8 x i8>, ptr %B741  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)742  ret <8 x i8> %tmp3743}744 745define <4 x i16> @sqrshl4h(ptr %A, ptr %B) nounwind {746; CHECK-LABEL: sqrshl4h:747; CHECK:       // %bb.0:748; CHECK-NEXT:    ldr d0, [x0]749; CHECK-NEXT:    ldr d1, [x1]750; CHECK-NEXT:    sqrshl v0.4h, v0.4h, v1.4h751; CHECK-NEXT:    ret752  %tmp1 = load <4 x i16>, ptr %A753  %tmp2 = load <4 x i16>, ptr %B754  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)755  ret <4 x i16> %tmp3756}757 758define <2 x i32> @sqrshl2s(ptr %A, ptr %B) nounwind {759; CHECK-LABEL: sqrshl2s:760; CHECK:       // %bb.0:761; CHECK-NEXT:    ldr d0, [x0]762; CHECK-NEXT:    ldr d1, [x1]763; CHECK-NEXT:    sqrshl v0.2s, v0.2s, v1.2s764; CHECK-NEXT:    ret765  %tmp1 = load <2 x i32>, ptr %A766  %tmp2 = load <2 x i32>, ptr %B767  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)768  ret <2 x i32> %tmp3769}770 771define <8 x i8> @uqrshl8b(ptr %A, ptr %B) nounwind {772; CHECK-LABEL: uqrshl8b:773; CHECK:       // %bb.0:774; CHECK-NEXT:    ldr d0, [x0]775; CHECK-NEXT:    ldr d1, [x1]776; CHECK-NEXT:    uqrshl v0.8b, v0.8b, v1.8b777; CHECK-NEXT:    ret778  %tmp1 = load <8 x i8>, ptr %A779  %tmp2 = load <8 x i8>, ptr %B780  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)781  ret <8 x i8> %tmp3782}783 784define <4 x i16> @uqrshl4h(ptr %A, ptr %B) nounwind {785; CHECK-LABEL: uqrshl4h:786; CHECK:       // %bb.0:787; CHECK-NEXT:    ldr d0, [x0]788; CHECK-NEXT:    ldr d1, [x1]789; CHECK-NEXT:    uqrshl v0.4h, v0.4h, v1.4h790; CHECK-NEXT:    ret791  %tmp1 = load <4 x i16>, ptr %A792  %tmp2 = load <4 x i16>, ptr %B793  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)794  ret <4 x i16> %tmp3795}796 797define <2 x i32> @uqrshl2s(ptr %A, ptr %B) nounwind {798; CHECK-LABEL: uqrshl2s:799; CHECK:       // %bb.0:800; CHECK-NEXT:    ldr d0, [x0]801; CHECK-NEXT:    ldr d1, [x1]802; CHECK-NEXT:    uqrshl v0.2s, v0.2s, v1.2s803; CHECK-NEXT:    ret804  %tmp1 = load <2 x i32>, ptr %A805  %tmp2 = load <2 x i32>, ptr %B806  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)807  ret <2 x i32> %tmp3808}809 810define <16 x i8> @sqrshl16b(ptr %A, ptr %B) nounwind {811; CHECK-LABEL: sqrshl16b:812; CHECK:       // %bb.0:813; CHECK-NEXT:    ldr q0, [x0]814; CHECK-NEXT:    ldr q1, [x1]815; CHECK-NEXT:    sqrshl v0.16b, v0.16b, v1.16b816; CHECK-NEXT:    ret817  %tmp1 = load <16 x i8>, ptr %A818  %tmp2 = load <16 x i8>, ptr %B819  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)820  ret <16 x i8> %tmp3821}822 823define <8 x i16> @sqrshl8h(ptr %A, ptr %B) nounwind {824; CHECK-LABEL: sqrshl8h:825; CHECK:       // %bb.0:826; CHECK-NEXT:    ldr q0, [x0]827; CHECK-NEXT:    ldr q1, [x1]828; CHECK-NEXT:    sqrshl v0.8h, v0.8h, v1.8h829; CHECK-NEXT:    ret830  %tmp1 = load <8 x i16>, ptr %A831  %tmp2 = load <8 x i16>, ptr %B832  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)833  ret <8 x i16> %tmp3834}835 836define <4 x i32> @sqrshl4s(ptr %A, ptr %B) nounwind {837; CHECK-LABEL: sqrshl4s:838; CHECK:       // %bb.0:839; CHECK-NEXT:    ldr q0, [x0]840; CHECK-NEXT:    ldr q1, [x1]841; CHECK-NEXT:    sqrshl v0.4s, v0.4s, v1.4s842; CHECK-NEXT:    ret843  %tmp1 = load <4 x i32>, ptr %A844  %tmp2 = load <4 x i32>, ptr %B845  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)846  ret <4 x i32> %tmp3847}848 849define <2 x i64> @sqrshl2d(ptr %A, ptr %B) nounwind {850; CHECK-LABEL: sqrshl2d:851; CHECK:       // %bb.0:852; CHECK-NEXT:    ldr q0, [x0]853; CHECK-NEXT:    ldr q1, [x1]854; CHECK-NEXT:    sqrshl v0.2d, v0.2d, v1.2d855; CHECK-NEXT:    ret856  %tmp1 = load <2 x i64>, ptr %A857  %tmp2 = load <2 x i64>, ptr %B858  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)859  ret <2 x i64> %tmp3860}861 862define <1 x i64> @sqrshl1d(ptr %A, ptr %B) nounwind {863; CHECK-LABEL: sqrshl1d:864; CHECK:       // %bb.0:865; CHECK-NEXT:    ldr d0, [x0]866; CHECK-NEXT:    ldr d1, [x1]867; CHECK-NEXT:    sqrshl d0, d0, d1868; CHECK-NEXT:    ret869  %tmp1 = load <1 x i64>, ptr %A870  %tmp2 = load <1 x i64>, ptr %B871  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)872  ret <1 x i64> %tmp3873}874 875define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind {876; CHECK-LABEL: sqrshl1d_constant:877; CHECK:       // %bb.0:878; CHECK-NEXT:    mov w8, #1 // =0x1879; CHECK-NEXT:    ldr d0, [x0]880; CHECK-NEXT:    fmov d1, x8881; CHECK-NEXT:    sqrshl d0, d0, d1882; CHECK-NEXT:    ret883  %tmp1 = load <1 x i64>, ptr %A884  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)885  ret <1 x i64> %tmp3886}887 888define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {889; CHECK-LABEL: sqrshl_scalar:890; CHECK:       // %bb.0:891; CHECK-NEXT:    ldr x8, [x0]892; CHECK-NEXT:    ldr x9, [x1]893; CHECK-NEXT:    fmov d0, x8894; CHECK-NEXT:    fmov d1, x9895; CHECK-NEXT:    sqrshl d0, d0, d1896; CHECK-NEXT:    fmov x0, d0897; CHECK-NEXT:    ret898  %tmp1 = load i64, ptr %A899  %tmp2 = load i64, ptr %B900  %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)901  ret i64 %tmp3902}903 904define i64 @sqrshl_scalar_constant(ptr %A) nounwind {905; CHECK-LABEL: sqrshl_scalar_constant:906; CHECK:       // %bb.0:907; CHECK-NEXT:    ldr x9, [x0]908; CHECK-NEXT:    mov w8, #1 // =0x1909; CHECK-NEXT:    fmov d1, x8910; CHECK-NEXT:    fmov d0, x9911; CHECK-NEXT:    sqrshl d0, d0, d1912; CHECK-NEXT:    fmov x0, d0913; CHECK-NEXT:    ret914  %tmp1 = load i64, ptr %A915  %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 1)916  ret i64 %tmp3917}918 919define <16 x i8> @uqrshl16b(ptr %A, ptr %B) nounwind {920; CHECK-LABEL: uqrshl16b:921; CHECK:       // %bb.0:922; CHECK-NEXT:    ldr q0, [x0]923; CHECK-NEXT:    ldr q1, [x1]924; CHECK-NEXT:    uqrshl v0.16b, v0.16b, v1.16b925; CHECK-NEXT:    ret926  %tmp1 = load <16 x i8>, ptr %A927  %tmp2 = load <16 x i8>, ptr %B928  %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)929  ret <16 x i8> %tmp3930}931 932define <8 x i16> @uqrshl8h(ptr %A, ptr %B) nounwind {933; CHECK-LABEL: uqrshl8h:934; CHECK:       // %bb.0:935; CHECK-NEXT:    ldr q0, [x0]936; CHECK-NEXT:    ldr q1, [x1]937; CHECK-NEXT:    uqrshl v0.8h, v0.8h, v1.8h938; CHECK-NEXT:    ret939  %tmp1 = load <8 x i16>, ptr %A940  %tmp2 = load <8 x i16>, ptr %B941  %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)942  ret <8 x i16> %tmp3943}944 945define <4 x i32> @uqrshl4s(ptr %A, ptr %B) nounwind {946; CHECK-LABEL: uqrshl4s:947; CHECK:       // %bb.0:948; CHECK-NEXT:    ldr q0, [x0]949; CHECK-NEXT:    ldr q1, [x1]950; CHECK-NEXT:    uqrshl v0.4s, v0.4s, v1.4s951; CHECK-NEXT:    ret952  %tmp1 = load <4 x i32>, ptr %A953  %tmp2 = load <4 x i32>, ptr %B954  %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)955  ret <4 x i32> %tmp3956}957 958define <2 x i64> @uqrshl2d(ptr %A, ptr %B) nounwind {959; CHECK-LABEL: uqrshl2d:960; CHECK:       // %bb.0:961; CHECK-NEXT:    ldr q0, [x0]962; CHECK-NEXT:    ldr q1, [x1]963; CHECK-NEXT:    uqrshl v0.2d, v0.2d, v1.2d964; CHECK-NEXT:    ret965  %tmp1 = load <2 x i64>, ptr %A966  %tmp2 = load <2 x i64>, ptr %B967  %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)968  ret <2 x i64> %tmp3969}970 971define <1 x i64> @uqrshl1d(ptr %A, ptr %B) nounwind {972; CHECK-LABEL: uqrshl1d:973; CHECK:       // %bb.0:974; CHECK-NEXT:    ldr d0, [x0]975; CHECK-NEXT:    ldr d1, [x1]976; CHECK-NEXT:    uqrshl d0, d0, d1977; CHECK-NEXT:    ret978  %tmp1 = load <1 x i64>, ptr %A979  %tmp2 = load <1 x i64>, ptr %B980  %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)981  ret <1 x i64> %tmp3982}983 984define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind {985; CHECK-LABEL: uqrshl1d_constant:986; CHECK:       // %bb.0:987; CHECK-NEXT:    mov w8, #1 // =0x1988; CHECK-NEXT:    ldr d0, [x0]989; CHECK-NEXT:    fmov d1, x8990; CHECK-NEXT:    uqrshl d0, d0, d1991; CHECK-NEXT:    ret992  %tmp1 = load <1 x i64>, ptr %A993  %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)994  ret <1 x i64> %tmp3995}996 997define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {998; CHECK-LABEL: uqrshl_scalar:999; CHECK:       // %bb.0:1000; CHECK-NEXT:    ldr x8, [x0]1001; CHECK-NEXT:    ldr x9, [x1]1002; CHECK-NEXT:    fmov d0, x81003; CHECK-NEXT:    fmov d1, x91004; CHECK-NEXT:    uqrshl d0, d0, d11005; CHECK-NEXT:    fmov x0, d01006; CHECK-NEXT:    ret1007  %tmp1 = load i64, ptr %A1008  %tmp2 = load i64, ptr %B1009  %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)1010  ret i64 %tmp31011}1012 1013define i64 @uqrshl_scalar_constant(ptr %A) nounwind {1014; CHECK-LABEL: uqrshl_scalar_constant:1015; CHECK:       // %bb.0:1016; CHECK-NEXT:    ldr x9, [x0]1017; CHECK-NEXT:    mov w8, #1 // =0x11018; CHECK-NEXT:    fmov d1, x81019; CHECK-NEXT:    fmov d0, x91020; CHECK-NEXT:    uqrshl d0, d0, d11021; CHECK-NEXT:    fmov x0, d01022; CHECK-NEXT:    ret1023  %tmp1 = load i64, ptr %A1024  %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 1)1025  ret i64 %tmp31026}1027 1028declare <8 x i8>  @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1029declare <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1030declare <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1031declare <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone1032declare i64 @llvm.aarch64.neon.sqrshl.i64(i64, i64) nounwind readnone1033 1034declare <8 x i8>  @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1035declare <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1036declare <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1037declare <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone1038declare i64 @llvm.aarch64.neon.uqrshl.i64(i64, i64) nounwind readnone1039 1040declare <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1041declare <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1042declare <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1043declare <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone1044 1045declare <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1046declare <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1047declare <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1048declare <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone1049 1050define <8 x i8> @urshr8b(ptr %A) nounwind {1051; CHECK-SD-LABEL: urshr8b:1052; CHECK-SD:       // %bb.0:1053; CHECK-SD-NEXT:    ldr d0, [x0]1054; CHECK-SD-NEXT:    urshr v0.8b, v0.8b, #11055; CHECK-SD-NEXT:    ret1056;1057; CHECK-GI-LABEL: urshr8b:1058; CHECK-GI:       // %bb.0:1059; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1060; CHECK-GI-NEXT:    ldr d1, [x0]1061; CHECK-GI-NEXT:    urshl v0.8b, v1.8b, v0.8b1062; CHECK-GI-NEXT:    ret1063  %tmp1 = load <8 x i8>, ptr %A1064  %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)1065  ret <8 x i8> %tmp31066}1067 1068define <4 x i16> @urshr4h(ptr %A) nounwind {1069; CHECK-SD-LABEL: urshr4h:1070; CHECK-SD:       // %bb.0:1071; CHECK-SD-NEXT:    ldr d0, [x0]1072; CHECK-SD-NEXT:    urshr v0.4h, v0.4h, #11073; CHECK-SD-NEXT:    ret1074;1075; CHECK-GI-LABEL: urshr4h:1076; CHECK-GI:       // %bb.0:1077; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1078; CHECK-GI-NEXT:    ldr d1, [x0]1079; CHECK-GI-NEXT:    urshl v0.4h, v1.4h, v0.4h1080; CHECK-GI-NEXT:    ret1081  %tmp1 = load <4 x i16>, ptr %A1082  %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)1083  ret <4 x i16> %tmp31084}1085 1086define <2 x i32> @urshr2s(ptr %A) nounwind {1087; CHECK-SD-LABEL: urshr2s:1088; CHECK-SD:       // %bb.0:1089; CHECK-SD-NEXT:    ldr d0, [x0]1090; CHECK-SD-NEXT:    urshr v0.2s, v0.2s, #11091; CHECK-SD-NEXT:    ret1092;1093; CHECK-GI-LABEL: urshr2s:1094; CHECK-GI:       // %bb.0:1095; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1096; CHECK-GI-NEXT:    ldr d1, [x0]1097; CHECK-GI-NEXT:    urshl v0.2s, v1.2s, v0.2s1098; CHECK-GI-NEXT:    ret1099  %tmp1 = load <2 x i32>, ptr %A1100  %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)1101  ret <2 x i32> %tmp31102}1103 1104define <16 x i8> @urshr16b(ptr %A) nounwind {1105; CHECK-SD-LABEL: urshr16b:1106; CHECK-SD:       // %bb.0:1107; CHECK-SD-NEXT:    ldr q0, [x0]1108; CHECK-SD-NEXT:    urshr v0.16b, v0.16b, #11109; CHECK-SD-NEXT:    ret1110;1111; CHECK-GI-LABEL: urshr16b:1112; CHECK-GI:       // %bb.0:1113; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1114; CHECK-GI-NEXT:    ldr q1, [x0]1115; CHECK-GI-NEXT:    urshl v0.16b, v1.16b, v0.16b1116; CHECK-GI-NEXT:    ret1117  %tmp1 = load <16 x i8>, ptr %A1118  %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)1119  ret <16 x i8> %tmp31120}1121 1122define <8 x i16> @urshr8h(ptr %A) nounwind {1123; CHECK-SD-LABEL: urshr8h:1124; CHECK-SD:       // %bb.0:1125; CHECK-SD-NEXT:    ldr q0, [x0]1126; CHECK-SD-NEXT:    urshr v0.8h, v0.8h, #11127; CHECK-SD-NEXT:    ret1128;1129; CHECK-GI-LABEL: urshr8h:1130; CHECK-GI:       // %bb.0:1131; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1132; CHECK-GI-NEXT:    ldr q1, [x0]1133; CHECK-GI-NEXT:    urshl v0.8h, v1.8h, v0.8h1134; CHECK-GI-NEXT:    ret1135  %tmp1 = load <8 x i16>, ptr %A1136  %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)1137  ret <8 x i16> %tmp31138}1139 1140define <4 x i32> @urshr4s(ptr %A) nounwind {1141; CHECK-SD-LABEL: urshr4s:1142; CHECK-SD:       // %bb.0:1143; CHECK-SD-NEXT:    ldr q0, [x0]1144; CHECK-SD-NEXT:    urshr v0.4s, v0.4s, #11145; CHECK-SD-NEXT:    ret1146;1147; CHECK-GI-LABEL: urshr4s:1148; CHECK-GI:       // %bb.0:1149; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1150; CHECK-GI-NEXT:    ldr q1, [x0]1151; CHECK-GI-NEXT:    urshl v0.4s, v1.4s, v0.4s1152; CHECK-GI-NEXT:    ret1153  %tmp1 = load <4 x i32>, ptr %A1154  %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)1155  ret <4 x i32> %tmp31156}1157 1158define <2 x i64> @urshr2d(ptr %A) nounwind {1159; CHECK-SD-LABEL: urshr2d:1160; CHECK-SD:       // %bb.0:1161; CHECK-SD-NEXT:    ldr q0, [x0]1162; CHECK-SD-NEXT:    urshr v0.2d, v0.2d, #11163; CHECK-SD-NEXT:    ret1164;1165; CHECK-GI-LABEL: urshr2d:1166; CHECK-GI:       // %bb.0:1167; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1168; CHECK-GI-NEXT:    ldr q1, [x0]1169; CHECK-GI-NEXT:    urshl v0.2d, v1.2d, v0.2d1170; CHECK-GI-NEXT:    ret1171  %tmp1 = load <2 x i64>, ptr %A1172  %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)1173  ret <2 x i64> %tmp31174}1175 1176define <1 x i64> @urshr1d(ptr %A) nounwind {1177; CHECK-LABEL: urshr1d:1178; CHECK:       // %bb.0:1179; CHECK-NEXT:    ldr d0, [x0]1180; CHECK-NEXT:    urshr d0, d0, #11181; CHECK-NEXT:    ret1182  %tmp1 = load <1 x i64>, ptr %A1183  %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)1184  ret <1 x i64> %tmp31185}1186 1187define i64 @urshr_scalar(ptr %A) nounwind {1188; CHECK-LABEL: urshr_scalar:1189; CHECK:       // %bb.0:1190; CHECK-NEXT:    ldr d0, [x0]1191; CHECK-NEXT:    urshr d0, d0, #11192; CHECK-NEXT:    fmov x0, d01193; CHECK-NEXT:    ret1194  %tmp1 = load i64, ptr %A1195  %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)1196  ret i64 %tmp31197}1198 1199define <8 x i8> @srshr8b(ptr %A) nounwind {1200; CHECK-SD-LABEL: srshr8b:1201; CHECK-SD:       // %bb.0:1202; CHECK-SD-NEXT:    ldr d0, [x0]1203; CHECK-SD-NEXT:    srshr v0.8b, v0.8b, #11204; CHECK-SD-NEXT:    ret1205;1206; CHECK-GI-LABEL: srshr8b:1207; CHECK-GI:       // %bb.0:1208; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1209; CHECK-GI-NEXT:    ldr d1, [x0]1210; CHECK-GI-NEXT:    srshl v0.8b, v1.8b, v0.8b1211; CHECK-GI-NEXT:    ret1212  %tmp1 = load <8 x i8>, ptr %A1213  %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)1214  ret <8 x i8> %tmp31215}1216 1217define <4 x i16> @srshr4h(ptr %A) nounwind {1218; CHECK-SD-LABEL: srshr4h:1219; CHECK-SD:       // %bb.0:1220; CHECK-SD-NEXT:    ldr d0, [x0]1221; CHECK-SD-NEXT:    srshr v0.4h, v0.4h, #11222; CHECK-SD-NEXT:    ret1223;1224; CHECK-GI-LABEL: srshr4h:1225; CHECK-GI:       // %bb.0:1226; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1227; CHECK-GI-NEXT:    ldr d1, [x0]1228; CHECK-GI-NEXT:    srshl v0.4h, v1.4h, v0.4h1229; CHECK-GI-NEXT:    ret1230  %tmp1 = load <4 x i16>, ptr %A1231  %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)1232  ret <4 x i16> %tmp31233}1234 1235define <2 x i32> @srshr2s(ptr %A) nounwind {1236; CHECK-SD-LABEL: srshr2s:1237; CHECK-SD:       // %bb.0:1238; CHECK-SD-NEXT:    ldr d0, [x0]1239; CHECK-SD-NEXT:    srshr v0.2s, v0.2s, #11240; CHECK-SD-NEXT:    ret1241;1242; CHECK-GI-LABEL: srshr2s:1243; CHECK-GI:       // %bb.0:1244; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff1245; CHECK-GI-NEXT:    ldr d1, [x0]1246; CHECK-GI-NEXT:    srshl v0.2s, v1.2s, v0.2s1247; CHECK-GI-NEXT:    ret1248  %tmp1 = load <2 x i32>, ptr %A1249  %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)1250  ret <2 x i32> %tmp31251}1252 1253define <16 x i8> @srshr16b(ptr %A) nounwind {1254; CHECK-SD-LABEL: srshr16b:1255; CHECK-SD:       // %bb.0:1256; CHECK-SD-NEXT:    ldr q0, [x0]1257; CHECK-SD-NEXT:    srshr v0.16b, v0.16b, #11258; CHECK-SD-NEXT:    ret1259;1260; CHECK-GI-LABEL: srshr16b:1261; CHECK-GI:       // %bb.0:1262; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1263; CHECK-GI-NEXT:    ldr q1, [x0]1264; CHECK-GI-NEXT:    srshl v0.16b, v1.16b, v0.16b1265; CHECK-GI-NEXT:    ret1266  %tmp1 = load <16 x i8>, ptr %A1267  %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)1268  ret <16 x i8> %tmp31269}1270 1271define <8 x i16> @srshr8h(ptr %A) nounwind {1272; CHECK-SD-LABEL: srshr8h:1273; CHECK-SD:       // %bb.0:1274; CHECK-SD-NEXT:    ldr q0, [x0]1275; CHECK-SD-NEXT:    srshr v0.8h, v0.8h, #11276; CHECK-SD-NEXT:    ret1277;1278; CHECK-GI-LABEL: srshr8h:1279; CHECK-GI:       // %bb.0:1280; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1281; CHECK-GI-NEXT:    ldr q1, [x0]1282; CHECK-GI-NEXT:    srshl v0.8h, v1.8h, v0.8h1283; CHECK-GI-NEXT:    ret1284  %tmp1 = load <8 x i16>, ptr %A1285  %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)1286  ret <8 x i16> %tmp31287}1288 1289define <4 x i32> @srshr4s(ptr %A) nounwind {1290; CHECK-SD-LABEL: srshr4s:1291; CHECK-SD:       // %bb.0:1292; CHECK-SD-NEXT:    ldr q0, [x0]1293; CHECK-SD-NEXT:    srshr v0.4s, v0.4s, #11294; CHECK-SD-NEXT:    ret1295;1296; CHECK-GI-LABEL: srshr4s:1297; CHECK-GI:       // %bb.0:1298; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1299; CHECK-GI-NEXT:    ldr q1, [x0]1300; CHECK-GI-NEXT:    srshl v0.4s, v1.4s, v0.4s1301; CHECK-GI-NEXT:    ret1302  %tmp1 = load <4 x i32>, ptr %A1303  %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)1304  ret <4 x i32> %tmp31305}1306 1307define <2 x i64> @srshr2d(ptr %A) nounwind {1308; CHECK-SD-LABEL: srshr2d:1309; CHECK-SD:       // %bb.0:1310; CHECK-SD-NEXT:    ldr q0, [x0]1311; CHECK-SD-NEXT:    srshr v0.2d, v0.2d, #11312; CHECK-SD-NEXT:    ret1313;1314; CHECK-GI-LABEL: srshr2d:1315; CHECK-GI:       // %bb.0:1316; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff1317; CHECK-GI-NEXT:    ldr q1, [x0]1318; CHECK-GI-NEXT:    srshl v0.2d, v1.2d, v0.2d1319; CHECK-GI-NEXT:    ret1320  %tmp1 = load <2 x i64>, ptr %A1321  %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)1322  ret <2 x i64> %tmp31323}1324 1325define <1 x i64> @srshr1d(ptr %A) nounwind {1326; CHECK-LABEL: srshr1d:1327; CHECK:       // %bb.0:1328; CHECK-NEXT:    ldr d0, [x0]1329; CHECK-NEXT:    srshr d0, d0, #11330; CHECK-NEXT:    ret1331  %tmp1 = load <1 x i64>, ptr %A1332  %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)1333  ret <1 x i64> %tmp31334}1335 1336define i64 @srshr_scalar(ptr %A) nounwind {1337; CHECK-LABEL: srshr_scalar:1338; CHECK:       // %bb.0:1339; CHECK-NEXT:    ldr d0, [x0]1340; CHECK-NEXT:    srshr d0, d0, #11341; CHECK-NEXT:    fmov x0, d01342; CHECK-NEXT:    ret1343  %tmp1 = load i64, ptr %A1344  %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)1345  ret i64 %tmp31346}1347 1348define <8 x i8> @sqshlu8b(ptr %A) nounwind {1349; CHECK-LABEL: sqshlu8b:1350; CHECK:       // %bb.0:1351; CHECK-NEXT:    ldr d0, [x0]1352; CHECK-NEXT:    sqshlu v0.8b, v0.8b, #11353; CHECK-NEXT:    ret1354  %tmp1 = load <8 x i8>, ptr %A1355  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)1356  ret <8 x i8> %tmp31357}1358 1359define <4 x i16> @sqshlu4h(ptr %A) nounwind {1360; CHECK-LABEL: sqshlu4h:1361; CHECK:       // %bb.0:1362; CHECK-NEXT:    ldr d0, [x0]1363; CHECK-NEXT:    sqshlu v0.4h, v0.4h, #11364; CHECK-NEXT:    ret1365  %tmp1 = load <4 x i16>, ptr %A1366  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)1367  ret <4 x i16> %tmp31368}1369 1370define <2 x i32> @sqshlu2s(ptr %A) nounwind {1371; CHECK-LABEL: sqshlu2s:1372; CHECK:       // %bb.0:1373; CHECK-NEXT:    ldr d0, [x0]1374; CHECK-NEXT:    sqshlu v0.2s, v0.2s, #11375; CHECK-NEXT:    ret1376  %tmp1 = load <2 x i32>, ptr %A1377  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)1378  ret <2 x i32> %tmp31379}1380 1381define <16 x i8> @sqshlu16b(ptr %A) nounwind {1382; CHECK-LABEL: sqshlu16b:1383; CHECK:       // %bb.0:1384; CHECK-NEXT:    ldr q0, [x0]1385; CHECK-NEXT:    sqshlu v0.16b, v0.16b, #11386; CHECK-NEXT:    ret1387  %tmp1 = load <16 x i8>, ptr %A1388  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)1389  ret <16 x i8> %tmp31390}1391 1392define <8 x i16> @sqshlu8h(ptr %A) nounwind {1393; CHECK-LABEL: sqshlu8h:1394; CHECK:       // %bb.0:1395; CHECK-NEXT:    ldr q0, [x0]1396; CHECK-NEXT:    sqshlu v0.8h, v0.8h, #11397; CHECK-NEXT:    ret1398  %tmp1 = load <8 x i16>, ptr %A1399  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)1400  ret <8 x i16> %tmp31401}1402 1403define <4 x i32> @sqshlu4s(ptr %A) nounwind {1404; CHECK-LABEL: sqshlu4s:1405; CHECK:       // %bb.0:1406; CHECK-NEXT:    ldr q0, [x0]1407; CHECK-NEXT:    sqshlu v0.4s, v0.4s, #11408; CHECK-NEXT:    ret1409  %tmp1 = load <4 x i32>, ptr %A1410  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)1411  ret <4 x i32> %tmp31412}1413 1414define <2 x i64> @sqshlu2d(ptr %A) nounwind {1415; CHECK-LABEL: sqshlu2d:1416; CHECK:       // %bb.0:1417; CHECK-NEXT:    ldr q0, [x0]1418; CHECK-NEXT:    sqshlu v0.2d, v0.2d, #11419; CHECK-NEXT:    ret1420  %tmp1 = load <2 x i64>, ptr %A1421  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)1422  ret <2 x i64> %tmp31423}1424 1425define <1 x i64> @sqshlu1d_constant(ptr %A) nounwind {1426; CHECK-LABEL: sqshlu1d_constant:1427; CHECK:       // %bb.0:1428; CHECK-NEXT:    ldr d0, [x0]1429; CHECK-NEXT:    sqshlu d0, d0, #11430; CHECK-NEXT:    ret1431  %tmp1 = load <1 x i64>, ptr %A1432  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)1433  ret <1 x i64> %tmp31434}1435 1436define i64 @sqshlu_i64_constant(ptr %A) nounwind {1437; CHECK-LABEL: sqshlu_i64_constant:1438; CHECK:       // %bb.0:1439; CHECK-NEXT:    ldr d0, [x0]1440; CHECK-NEXT:    sqshlu d0, d0, #11441; CHECK-NEXT:    fmov x0, d01442; CHECK-NEXT:    ret1443  %tmp1 = load i64, ptr %A1444  %tmp3 = call i64 @llvm.aarch64.neon.sqshlu.i64(i64 %tmp1, i64 1)1445  ret i64 %tmp31446}1447 1448define i32 @sqshlu_i32_constant(ptr %A) nounwind {1449; CHECK-LABEL: sqshlu_i32_constant:1450; CHECK:       // %bb.0:1451; CHECK-NEXT:    ldr w8, [x0]1452; CHECK-NEXT:    fmov s0, w81453; CHECK-NEXT:    sqshlu s0, s0, #11454; CHECK-NEXT:    fmov w0, s01455; CHECK-NEXT:    ret1456  %tmp1 = load i32, ptr %A1457  %tmp3 = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 %tmp1, i32 1)1458  ret i32 %tmp31459}1460 1461declare <8 x i8>  @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1462declare <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1463declare <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1464declare <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone1465declare i64 @llvm.aarch64.neon.sqshlu.i64(i64, i64) nounwind readnone1466declare i32 @llvm.aarch64.neon.sqshlu.i32(i32, i32) nounwind readnone1467 1468declare <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1469declare <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1470declare <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1471declare <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone1472 1473define <8 x i8> @rshrn8b(ptr %A) nounwind {1474; CHECK-LABEL: rshrn8b:1475; CHECK:       // %bb.0:1476; CHECK-NEXT:    ldr q0, [x0]1477; CHECK-NEXT:    rshrn v0.8b, v0.8h, #11478; CHECK-NEXT:    ret1479  %tmp1 = load <8 x i16>, ptr %A1480  %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)1481  ret <8 x i8> %tmp31482}1483 1484define <4 x i16> @rshrn4h(ptr %A) nounwind {1485; CHECK-LABEL: rshrn4h:1486; CHECK:       // %bb.0:1487; CHECK-NEXT:    ldr q0, [x0]1488; CHECK-NEXT:    rshrn v0.4h, v0.4s, #11489; CHECK-NEXT:    ret1490  %tmp1 = load <4 x i32>, ptr %A1491  %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)1492  ret <4 x i16> %tmp31493}1494 1495define <2 x i32> @rshrn2s(ptr %A) nounwind {1496; CHECK-LABEL: rshrn2s:1497; CHECK:       // %bb.0:1498; CHECK-NEXT:    ldr q0, [x0]1499; CHECK-NEXT:    rshrn v0.2s, v0.2d, #11500; CHECK-NEXT:    ret1501  %tmp1 = load <2 x i64>, ptr %A1502  %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)1503  ret <2 x i32> %tmp31504}1505 1506define <16 x i8> @rshrn16b(ptr %ret, ptr %A) nounwind {1507; CHECK-LABEL: rshrn16b:1508; CHECK:       // %bb.0:1509; CHECK-NEXT:    ldr d0, [x0]1510; CHECK-NEXT:    ldr q1, [x1]1511; CHECK-NEXT:    rshrn2 v0.16b, v1.8h, #11512; CHECK-NEXT:    ret1513  %out = load <8 x i8>, ptr %ret1514  %tmp1 = load <8 x i16>, ptr %A1515  %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)1516  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1517  ret <16 x i8> %tmp41518}1519 1520define <8 x i16> @rshrn8h(ptr %ret, ptr %A) nounwind {1521; CHECK-LABEL: rshrn8h:1522; CHECK:       // %bb.0:1523; CHECK-NEXT:    ldr d0, [x0]1524; CHECK-NEXT:    ldr q1, [x1]1525; CHECK-NEXT:    rshrn2 v0.8h, v1.4s, #11526; CHECK-NEXT:    ret1527  %out = load <4 x i16>, ptr %ret1528  %tmp1 = load <4 x i32>, ptr %A1529  %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)1530  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1531  ret <8 x i16> %tmp41532}1533 1534define <4 x i32> @rshrn4s(ptr %ret, ptr %A) nounwind {1535; CHECK-LABEL: rshrn4s:1536; CHECK:       // %bb.0:1537; CHECK-NEXT:    ldr d0, [x0]1538; CHECK-NEXT:    ldr q1, [x1]1539; CHECK-NEXT:    rshrn2 v0.4s, v1.2d, #11540; CHECK-NEXT:    ret1541  %out = load <2 x i32>, ptr %ret1542  %tmp1 = load <2 x i64>, ptr %A1543  %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)1544  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1545  ret <4 x i32> %tmp41546}1547 1548declare <8 x i8>  @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone1549declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32) nounwind readnone1550declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readnone1551 1552define <8 x i8> @shrn8b(ptr %A) nounwind {1553; CHECK-LABEL: shrn8b:1554; CHECK:       // %bb.0:1555; CHECK-NEXT:    ldr q0, [x0]1556; CHECK-NEXT:    shrn v0.8b, v0.8h, #11557; CHECK-NEXT:    ret1558  %tmp1 = load <8 x i16>, ptr %A1559  %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1560  %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>1561  ret <8 x i8> %tmp31562}1563 1564define <4 x i16> @shrn4h(ptr %A) nounwind {1565; CHECK-LABEL: shrn4h:1566; CHECK:       // %bb.0:1567; CHECK-NEXT:    ldr q0, [x0]1568; CHECK-NEXT:    shrn v0.4h, v0.4s, #11569; CHECK-NEXT:    ret1570  %tmp1 = load <4 x i32>, ptr %A1571  %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>1572  %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>1573  ret <4 x i16> %tmp31574}1575 1576define <2 x i32> @shrn2s(ptr %A) nounwind {1577; CHECK-LABEL: shrn2s:1578; CHECK:       // %bb.0:1579; CHECK-NEXT:    ldr q0, [x0]1580; CHECK-NEXT:    shrn v0.2s, v0.2d, #11581; CHECK-NEXT:    ret1582  %tmp1 = load <2 x i64>, ptr %A1583  %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>1584  %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>1585  ret <2 x i32> %tmp31586}1587 1588define <16 x i8> @shrn16b(ptr %ret, ptr %A) nounwind {1589; CHECK-LABEL: shrn16b:1590; CHECK:       // %bb.0:1591; CHECK-NEXT:    ldr d0, [x0]1592; CHECK-NEXT:    ldr q1, [x1]1593; CHECK-NEXT:    shrn2 v0.16b, v1.8h, #11594; CHECK-NEXT:    ret1595  %out = load <8 x i8>, ptr %ret1596  %tmp1 = load <8 x i16>, ptr %A1597  %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1598  %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>1599  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1600  ret <16 x i8> %tmp41601}1602 1603define <8 x i16> @shrn8h(ptr %ret, ptr %A) nounwind {1604; CHECK-LABEL: shrn8h:1605; CHECK:       // %bb.0:1606; CHECK-NEXT:    ldr d0, [x0]1607; CHECK-NEXT:    ldr q1, [x1]1608; CHECK-NEXT:    shrn2 v0.8h, v1.4s, #11609; CHECK-NEXT:    ret1610  %out = load <4 x i16>, ptr %ret1611  %tmp1 = load <4 x i32>, ptr %A1612  %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>1613  %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>1614  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1615  ret <8 x i16> %tmp41616}1617 1618define <4 x i32> @shrn4s(ptr %ret, ptr %A) nounwind {1619; CHECK-LABEL: shrn4s:1620; CHECK:       // %bb.0:1621; CHECK-NEXT:    ldr d0, [x0]1622; CHECK-NEXT:    ldr q1, [x1]1623; CHECK-NEXT:    shrn2 v0.4s, v1.2d, #11624; CHECK-NEXT:    ret1625  %out = load <2 x i32>, ptr %ret1626  %tmp1 = load <2 x i64>, ptr %A1627  %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>1628  %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>1629  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1630  ret <4 x i32> %tmp41631}1632 1633declare <8 x i8>  @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone1634declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone1635declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone1636 1637define i32 @sqshrn1s(i64 %A) nounwind {1638; CHECK-LABEL: sqshrn1s:1639; CHECK:       // %bb.0:1640; CHECK-NEXT:    fmov d0, x01641; CHECK-NEXT:    sqshrn s0, d0, #11642; CHECK-NEXT:    fmov w0, s01643; CHECK-NEXT:    ret1644  %tmp = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %A, i32 1)1645  ret i32 %tmp1646}1647 1648define <8 x i8> @sqshrn8b(ptr %A) nounwind {1649; CHECK-LABEL: sqshrn8b:1650; CHECK:       // %bb.0:1651; CHECK-NEXT:    ldr q0, [x0]1652; CHECK-NEXT:    sqshrn v0.8b, v0.8h, #11653; CHECK-NEXT:    ret1654  %tmp1 = load <8 x i16>, ptr %A1655  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)1656  ret <8 x i8> %tmp31657}1658 1659define <4 x i16> @sqshrn4h(ptr %A) nounwind {1660; CHECK-LABEL: sqshrn4h:1661; CHECK:       // %bb.0:1662; CHECK-NEXT:    ldr q0, [x0]1663; CHECK-NEXT:    sqshrn v0.4h, v0.4s, #11664; CHECK-NEXT:    ret1665  %tmp1 = load <4 x i32>, ptr %A1666  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)1667  ret <4 x i16> %tmp31668}1669 1670define <2 x i32> @sqshrn2s(ptr %A) nounwind {1671; CHECK-LABEL: sqshrn2s:1672; CHECK:       // %bb.0:1673; CHECK-NEXT:    ldr q0, [x0]1674; CHECK-NEXT:    sqshrn v0.2s, v0.2d, #11675; CHECK-NEXT:    ret1676  %tmp1 = load <2 x i64>, ptr %A1677  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)1678  ret <2 x i32> %tmp31679}1680 1681 1682define <16 x i8> @sqshrn16b(ptr %ret, ptr %A) nounwind {1683; CHECK-LABEL: sqshrn16b:1684; CHECK:       // %bb.0:1685; CHECK-NEXT:    ldr d0, [x0]1686; CHECK-NEXT:    ldr q1, [x1]1687; CHECK-NEXT:    sqshrn2 v0.16b, v1.8h, #11688; CHECK-NEXT:    ret1689  %out = load <8 x i8>, ptr %ret1690  %tmp1 = load <8 x i16>, ptr %A1691  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)1692  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1693  ret <16 x i8> %tmp41694}1695 1696define <8 x i16> @sqshrn8h(ptr %ret, ptr %A) nounwind {1697; CHECK-LABEL: sqshrn8h:1698; CHECK:       // %bb.0:1699; CHECK-NEXT:    ldr d0, [x0]1700; CHECK-NEXT:    ldr q1, [x1]1701; CHECK-NEXT:    sqshrn2 v0.8h, v1.4s, #11702; CHECK-NEXT:    ret1703  %out = load <4 x i16>, ptr %ret1704  %tmp1 = load <4 x i32>, ptr %A1705  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)1706  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1707  ret <8 x i16> %tmp41708}1709 1710define <4 x i32> @sqshrn4s(ptr %ret, ptr %A) nounwind {1711; CHECK-LABEL: sqshrn4s:1712; CHECK:       // %bb.0:1713; CHECK-NEXT:    ldr d0, [x0]1714; CHECK-NEXT:    ldr q1, [x1]1715; CHECK-NEXT:    sqshrn2 v0.4s, v1.2d, #11716; CHECK-NEXT:    ret1717  %out = load <2 x i32>, ptr %ret1718  %tmp1 = load <2 x i64>, ptr %A1719  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)1720  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1721  ret <4 x i32> %tmp41722}1723 1724declare i32  @llvm.aarch64.neon.sqshrn.i32(i64, i32) nounwind readnone1725declare <8 x i8>  @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone1726declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone1727declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone1728 1729define i32 @sqshrun1s(i64 %A) nounwind {1730; CHECK-LABEL: sqshrun1s:1731; CHECK:       // %bb.0:1732; CHECK-NEXT:    fmov d0, x01733; CHECK-NEXT:    sqshrun s0, d0, #11734; CHECK-NEXT:    fmov w0, s01735; CHECK-NEXT:    ret1736  %tmp = call i32 @llvm.aarch64.neon.sqshrun.i32(i64 %A, i32 1)1737  ret i32 %tmp1738}1739 1740define <8 x i8> @sqshrun8b(ptr %A) nounwind {1741; CHECK-LABEL: sqshrun8b:1742; CHECK:       // %bb.0:1743; CHECK-NEXT:    ldr q0, [x0]1744; CHECK-NEXT:    sqshrun v0.8b, v0.8h, #11745; CHECK-NEXT:    ret1746  %tmp1 = load <8 x i16>, ptr %A1747  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)1748  ret <8 x i8> %tmp31749}1750 1751define <4 x i16> @sqshrun4h(ptr %A) nounwind {1752; CHECK-LABEL: sqshrun4h:1753; CHECK:       // %bb.0:1754; CHECK-NEXT:    ldr q0, [x0]1755; CHECK-NEXT:    sqshrun v0.4h, v0.4s, #11756; CHECK-NEXT:    ret1757  %tmp1 = load <4 x i32>, ptr %A1758  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)1759  ret <4 x i16> %tmp31760}1761 1762define <2 x i32> @sqshrun2s(ptr %A) nounwind {1763; CHECK-LABEL: sqshrun2s:1764; CHECK:       // %bb.0:1765; CHECK-NEXT:    ldr q0, [x0]1766; CHECK-NEXT:    sqshrun v0.2s, v0.2d, #11767; CHECK-NEXT:    ret1768  %tmp1 = load <2 x i64>, ptr %A1769  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)1770  ret <2 x i32> %tmp31771}1772 1773define <16 x i8> @sqshrun16b(ptr %ret, ptr %A) nounwind {1774; CHECK-LABEL: sqshrun16b:1775; CHECK:       // %bb.0:1776; CHECK-NEXT:    ldr d0, [x0]1777; CHECK-NEXT:    ldr q1, [x1]1778; CHECK-NEXT:    sqshrun2 v0.16b, v1.8h, #11779; CHECK-NEXT:    ret1780  %out = load <8 x i8>, ptr %ret1781  %tmp1 = load <8 x i16>, ptr %A1782  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)1783  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1784  ret <16 x i8> %tmp41785}1786 1787define <8 x i16> @sqshrun8h(ptr %ret, ptr %A) nounwind {1788; CHECK-LABEL: sqshrun8h:1789; CHECK:       // %bb.0:1790; CHECK-NEXT:    ldr d0, [x0]1791; CHECK-NEXT:    ldr q1, [x1]1792; CHECK-NEXT:    sqshrun2 v0.8h, v1.4s, #11793; CHECK-NEXT:    ret1794  %out = load <4 x i16>, ptr %ret1795  %tmp1 = load <4 x i32>, ptr %A1796  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)1797  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1798  ret <8 x i16> %tmp41799}1800 1801define <4 x i32> @sqshrun4s(ptr %ret, ptr %A) nounwind {1802; CHECK-LABEL: sqshrun4s:1803; CHECK:       // %bb.0:1804; CHECK-NEXT:    ldr d0, [x0]1805; CHECK-NEXT:    ldr q1, [x1]1806; CHECK-NEXT:    sqshrun2 v0.4s, v1.2d, #11807; CHECK-NEXT:    ret1808  %out = load <2 x i32>, ptr %ret1809  %tmp1 = load <2 x i64>, ptr %A1810  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)1811  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1812  ret <4 x i32> %tmp41813}1814 1815declare i32  @llvm.aarch64.neon.sqshrun.i32(i64, i32) nounwind readnone1816declare <8 x i8>  @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, i32) nounwind readnone1817declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, i32) nounwind readnone1818declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, i32) nounwind readnone1819 1820define i32 @sqrshrn1s(i64 %A) nounwind {1821; CHECK-LABEL: sqrshrn1s:1822; CHECK:       // %bb.0:1823; CHECK-NEXT:    fmov d0, x01824; CHECK-NEXT:    sqrshrn s0, d0, #11825; CHECK-NEXT:    fmov w0, s01826; CHECK-NEXT:    ret1827  %tmp = call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 %A, i32 1)1828  ret i32 %tmp1829}1830 1831define <8 x i8> @sqrshrn8b(ptr %A) nounwind {1832; CHECK-LABEL: sqrshrn8b:1833; CHECK:       // %bb.0:1834; CHECK-NEXT:    ldr q0, [x0]1835; CHECK-NEXT:    sqrshrn v0.8b, v0.8h, #11836; CHECK-NEXT:    ret1837  %tmp1 = load <8 x i16>, ptr %A1838  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)1839  ret <8 x i8> %tmp31840}1841 1842define <4 x i16> @sqrshrn4h(ptr %A) nounwind {1843; CHECK-LABEL: sqrshrn4h:1844; CHECK:       // %bb.0:1845; CHECK-NEXT:    ldr q0, [x0]1846; CHECK-NEXT:    sqrshrn v0.4h, v0.4s, #11847; CHECK-NEXT:    ret1848  %tmp1 = load <4 x i32>, ptr %A1849  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)1850  ret <4 x i16> %tmp31851}1852 1853define <2 x i32> @sqrshrn2s(ptr %A) nounwind {1854; CHECK-LABEL: sqrshrn2s:1855; CHECK:       // %bb.0:1856; CHECK-NEXT:    ldr q0, [x0]1857; CHECK-NEXT:    sqrshrn v0.2s, v0.2d, #11858; CHECK-NEXT:    ret1859  %tmp1 = load <2 x i64>, ptr %A1860  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)1861  ret <2 x i32> %tmp31862}1863 1864define <16 x i8> @sqrshrn16b(ptr %ret, ptr %A) nounwind {1865; CHECK-LABEL: sqrshrn16b:1866; CHECK:       // %bb.0:1867; CHECK-NEXT:    ldr d0, [x0]1868; CHECK-NEXT:    ldr q1, [x1]1869; CHECK-NEXT:    sqrshrn2 v0.16b, v1.8h, #11870; CHECK-NEXT:    ret1871  %out = load <8 x i8>, ptr %ret1872  %tmp1 = load <8 x i16>, ptr %A1873  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)1874  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1875  ret <16 x i8> %tmp41876}1877 1878define <8 x i16> @sqrshrn8h(ptr %ret, ptr %A) nounwind {1879; CHECK-LABEL: sqrshrn8h:1880; CHECK:       // %bb.0:1881; CHECK-NEXT:    ldr d0, [x0]1882; CHECK-NEXT:    ldr q1, [x1]1883; CHECK-NEXT:    sqrshrn2 v0.8h, v1.4s, #11884; CHECK-NEXT:    ret1885  %out = load <4 x i16>, ptr %ret1886  %tmp1 = load <4 x i32>, ptr %A1887  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)1888  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1889  ret <8 x i16> %tmp41890}1891 1892define <4 x i32> @sqrshrn4s(ptr %ret, ptr %A) nounwind {1893; CHECK-LABEL: sqrshrn4s:1894; CHECK:       // %bb.0:1895; CHECK-NEXT:    ldr d0, [x0]1896; CHECK-NEXT:    ldr q1, [x1]1897; CHECK-NEXT:    sqrshrn2 v0.4s, v1.2d, #11898; CHECK-NEXT:    ret1899  %out = load <2 x i32>, ptr %ret1900  %tmp1 = load <2 x i64>, ptr %A1901  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)1902  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1903  ret <4 x i32> %tmp41904}1905 1906declare i32  @llvm.aarch64.neon.sqrshrn.i32(i64, i32) nounwind readnone1907declare <8 x i8>  @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32) nounwind readnone1908declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32) nounwind readnone1909declare <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64>, i32) nounwind readnone1910 1911define i32 @sqrshrun1s(i64 %A) nounwind {1912; CHECK-LABEL: sqrshrun1s:1913; CHECK:       // %bb.0:1914; CHECK-NEXT:    fmov d0, x01915; CHECK-NEXT:    sqrshrun s0, d0, #11916; CHECK-NEXT:    fmov w0, s01917; CHECK-NEXT:    ret1918  %tmp = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %A, i32 1)1919  ret i32 %tmp1920}1921 1922define <8 x i8> @sqrshrun8b(ptr %A) nounwind {1923; CHECK-LABEL: sqrshrun8b:1924; CHECK:       // %bb.0:1925; CHECK-NEXT:    ldr q0, [x0]1926; CHECK-NEXT:    sqrshrun v0.8b, v0.8h, #11927; CHECK-NEXT:    ret1928  %tmp1 = load <8 x i16>, ptr %A1929  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)1930  ret <8 x i8> %tmp31931}1932 1933define <4 x i16> @sqrshrun4h(ptr %A) nounwind {1934; CHECK-LABEL: sqrshrun4h:1935; CHECK:       // %bb.0:1936; CHECK-NEXT:    ldr q0, [x0]1937; CHECK-NEXT:    sqrshrun v0.4h, v0.4s, #11938; CHECK-NEXT:    ret1939  %tmp1 = load <4 x i32>, ptr %A1940  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)1941  ret <4 x i16> %tmp31942}1943 1944define <2 x i32> @sqrshrun2s(ptr %A) nounwind {1945; CHECK-LABEL: sqrshrun2s:1946; CHECK:       // %bb.0:1947; CHECK-NEXT:    ldr q0, [x0]1948; CHECK-NEXT:    sqrshrun v0.2s, v0.2d, #11949; CHECK-NEXT:    ret1950  %tmp1 = load <2 x i64>, ptr %A1951  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)1952  ret <2 x i32> %tmp31953}1954 1955define <16 x i8> @sqrshrun16b(ptr %ret, ptr %A) nounwind {1956; CHECK-LABEL: sqrshrun16b:1957; CHECK:       // %bb.0:1958; CHECK-NEXT:    ldr d0, [x0]1959; CHECK-NEXT:    ldr q1, [x1]1960; CHECK-NEXT:    sqrshrun2 v0.16b, v1.8h, #11961; CHECK-NEXT:    ret1962  %out = load <8 x i8>, ptr %ret1963  %tmp1 = load <8 x i16>, ptr %A1964  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)1965  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1966  ret <16 x i8> %tmp41967}1968 1969define <8 x i16> @sqrshrun8h(ptr %ret, ptr %A) nounwind {1970; CHECK-LABEL: sqrshrun8h:1971; CHECK:       // %bb.0:1972; CHECK-NEXT:    ldr d0, [x0]1973; CHECK-NEXT:    ldr q1, [x1]1974; CHECK-NEXT:    sqrshrun2 v0.8h, v1.4s, #11975; CHECK-NEXT:    ret1976  %out = load <4 x i16>, ptr %ret1977  %tmp1 = load <4 x i32>, ptr %A1978  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)1979  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1980  ret <8 x i16> %tmp41981}1982 1983define <4 x i32> @sqrshrun4s(ptr %ret, ptr %A) nounwind {1984; CHECK-LABEL: sqrshrun4s:1985; CHECK:       // %bb.0:1986; CHECK-NEXT:    ldr d0, [x0]1987; CHECK-NEXT:    ldr q1, [x1]1988; CHECK-NEXT:    sqrshrun2 v0.4s, v1.2d, #11989; CHECK-NEXT:    ret1990  %out = load <2 x i32>, ptr %ret1991  %tmp1 = load <2 x i64>, ptr %A1992  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)1993  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1994  ret <4 x i32> %tmp41995}1996 1997declare i32  @llvm.aarch64.neon.sqrshrun.i32(i64, i32) nounwind readnone1998declare <8 x i8>  @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32) nounwind readnone1999declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32) nounwind readnone2000declare <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64>, i32) nounwind readnone2001 2002define i32 @uqrshrn1s(i64 %A) nounwind {2003; CHECK-LABEL: uqrshrn1s:2004; CHECK:       // %bb.0:2005; CHECK-NEXT:    fmov d0, x02006; CHECK-NEXT:    uqrshrn s0, d0, #12007; CHECK-NEXT:    fmov w0, s02008; CHECK-NEXT:    ret2009  %tmp = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 %A, i32 1)2010  ret i32 %tmp2011}2012 2013define <8 x i8> @uqrshrn8b(ptr %A) nounwind {2014; CHECK-LABEL: uqrshrn8b:2015; CHECK:       // %bb.0:2016; CHECK-NEXT:    ldr q0, [x0]2017; CHECK-NEXT:    uqrshrn v0.8b, v0.8h, #12018; CHECK-NEXT:    ret2019  %tmp1 = load <8 x i16>, ptr %A2020  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)2021  ret <8 x i8> %tmp32022}2023 2024define <4 x i16> @uqrshrn4h(ptr %A) nounwind {2025; CHECK-LABEL: uqrshrn4h:2026; CHECK:       // %bb.0:2027; CHECK-NEXT:    ldr q0, [x0]2028; CHECK-NEXT:    uqrshrn v0.4h, v0.4s, #12029; CHECK-NEXT:    ret2030  %tmp1 = load <4 x i32>, ptr %A2031  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)2032  ret <4 x i16> %tmp32033}2034 2035define <2 x i32> @uqrshrn2s(ptr %A) nounwind {2036; CHECK-LABEL: uqrshrn2s:2037; CHECK:       // %bb.0:2038; CHECK-NEXT:    ldr q0, [x0]2039; CHECK-NEXT:    uqrshrn v0.2s, v0.2d, #12040; CHECK-NEXT:    ret2041  %tmp1 = load <2 x i64>, ptr %A2042  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)2043  ret <2 x i32> %tmp32044}2045 2046define <16 x i8> @uqrshrn16b(ptr %ret, ptr %A) nounwind {2047; CHECK-LABEL: uqrshrn16b:2048; CHECK:       // %bb.0:2049; CHECK-NEXT:    ldr d0, [x0]2050; CHECK-NEXT:    ldr q1, [x1]2051; CHECK-NEXT:    uqrshrn2 v0.16b, v1.8h, #12052; CHECK-NEXT:    ret2053  %out = load <8 x i8>, ptr %ret2054  %tmp1 = load <8 x i16>, ptr %A2055  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)2056  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2057  ret <16 x i8> %tmp42058}2059 2060define <8 x i16> @uqrshrn8h(ptr %ret, ptr %A) nounwind {2061; CHECK-LABEL: uqrshrn8h:2062; CHECK:       // %bb.0:2063; CHECK-NEXT:    ldr d0, [x0]2064; CHECK-NEXT:    ldr q1, [x1]2065; CHECK-NEXT:    uqrshrn2 v0.8h, v1.4s, #12066; CHECK-NEXT:    ret2067  %out = load <4 x i16>, ptr %ret2068  %tmp1 = load <4 x i32>, ptr %A2069  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)2070  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2071  ret <8 x i16> %tmp42072}2073 2074define <4 x i32> @uqrshrn4s(ptr %ret, ptr %A) nounwind {2075; CHECK-LABEL: uqrshrn4s:2076; CHECK:       // %bb.0:2077; CHECK-NEXT:    ldr d0, [x0]2078; CHECK-NEXT:    ldr q1, [x1]2079; CHECK-NEXT:    uqrshrn2 v0.4s, v1.2d, #12080; CHECK-NEXT:    ret2081  %out = load <2 x i32>, ptr %ret2082  %tmp1 = load <2 x i64>, ptr %A2083  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)2084  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2085  ret <4 x i32> %tmp42086}2087 2088declare i32  @llvm.aarch64.neon.uqrshrn.i32(i64, i32) nounwind readnone2089declare <8 x i8>  @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32) nounwind readnone2090declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32) nounwind readnone2091declare <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64>, i32) nounwind readnone2092 2093define i32 @uqshrn1s(i64 %A) nounwind {2094; CHECK-LABEL: uqshrn1s:2095; CHECK:       // %bb.0:2096; CHECK-NEXT:    fmov d0, x02097; CHECK-NEXT:    uqshrn s0, d0, #12098; CHECK-NEXT:    fmov w0, s02099; CHECK-NEXT:    ret2100  %tmp = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %A, i32 1)2101  ret i32 %tmp2102}2103 2104define <8 x i8> @uqshrn8b(ptr %A) nounwind {2105; CHECK-LABEL: uqshrn8b:2106; CHECK:       // %bb.0:2107; CHECK-NEXT:    ldr q0, [x0]2108; CHECK-NEXT:    uqshrn v0.8b, v0.8h, #12109; CHECK-NEXT:    ret2110  %tmp1 = load <8 x i16>, ptr %A2111  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)2112  ret <8 x i8> %tmp32113}2114 2115define <4 x i16> @uqshrn4h(ptr %A) nounwind {2116; CHECK-LABEL: uqshrn4h:2117; CHECK:       // %bb.0:2118; CHECK-NEXT:    ldr q0, [x0]2119; CHECK-NEXT:    uqshrn v0.4h, v0.4s, #12120; CHECK-NEXT:    ret2121  %tmp1 = load <4 x i32>, ptr %A2122  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)2123  ret <4 x i16> %tmp32124}2125 2126define <2 x i32> @uqshrn2s(ptr %A) nounwind {2127; CHECK-LABEL: uqshrn2s:2128; CHECK:       // %bb.0:2129; CHECK-NEXT:    ldr q0, [x0]2130; CHECK-NEXT:    uqshrn v0.2s, v0.2d, #12131; CHECK-NEXT:    ret2132  %tmp1 = load <2 x i64>, ptr %A2133  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)2134  ret <2 x i32> %tmp32135}2136 2137define <16 x i8> @uqshrn16b(ptr %ret, ptr %A) nounwind {2138; CHECK-LABEL: uqshrn16b:2139; CHECK:       // %bb.0:2140; CHECK-NEXT:    ldr d0, [x0]2141; CHECK-NEXT:    ldr q1, [x1]2142; CHECK-NEXT:    uqshrn2 v0.16b, v1.8h, #12143; CHECK-NEXT:    ret2144  %out = load <8 x i8>, ptr %ret2145  %tmp1 = load <8 x i16>, ptr %A2146  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)2147  %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2148  ret <16 x i8> %tmp42149}2150 2151define <8 x i16> @uqshrn8h(ptr %ret, ptr %A) nounwind {2152; CHECK-LABEL: uqshrn8h:2153; CHECK:       // %bb.0:2154; CHECK-NEXT:    ldr d0, [x0]2155; CHECK-NEXT:    ldr q1, [x1]2156; CHECK-NEXT:    uqshrn2 v0.8h, v1.4s, #12157; CHECK-NEXT:    ret2158  %out = load <4 x i16>, ptr %ret2159  %tmp1 = load <4 x i32>, ptr %A2160  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)2161  %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2162  ret <8 x i16> %tmp42163}2164 2165define <4 x i32> @uqshrn4s(ptr %ret, ptr %A) nounwind {2166; CHECK-LABEL: uqshrn4s:2167; CHECK:       // %bb.0:2168; CHECK-NEXT:    ldr d0, [x0]2169; CHECK-NEXT:    ldr q1, [x1]2170; CHECK-NEXT:    uqshrn2 v0.4s, v1.2d, #12171; CHECK-NEXT:    ret2172  %out = load <2 x i32>, ptr %ret2173  %tmp1 = load <2 x i64>, ptr %A2174  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)2175  %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2176  ret <4 x i32> %tmp42177}2178 2179declare i32  @llvm.aarch64.neon.uqshrn.i32(i64, i32) nounwind readnone2180declare <8 x i8>  @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32) nounwind readnone2181declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32) nounwind readnone2182declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readnone2183 2184define <8 x i16> @ushll8h(ptr %A) nounwind {2185; CHECK-LABEL: ushll8h:2186; CHECK:       // %bb.0:2187; CHECK-NEXT:    ldr d0, [x0]2188; CHECK-NEXT:    ushll v0.8h, v0.8b, #12189; CHECK-NEXT:    ret2190  %tmp1 = load <8 x i8>, ptr %A2191  %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>2192  %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2193  ret <8 x i16> %tmp32194}2195 2196define <4 x i32> @ushll4s(ptr %A) nounwind {2197; CHECK-LABEL: ushll4s:2198; CHECK:       // %bb.0:2199; CHECK-NEXT:    ldr d0, [x0]2200; CHECK-NEXT:    ushll v0.4s, v0.4h, #12201; CHECK-NEXT:    ret2202  %tmp1 = load <4 x i16>, ptr %A2203  %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>2204  %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>2205  ret <4 x i32> %tmp32206}2207 2208define <2 x i64> @ushll2d(ptr %A) nounwind {2209; CHECK-LABEL: ushll2d:2210; CHECK:       // %bb.0:2211; CHECK-NEXT:    ldr d0, [x0]2212; CHECK-NEXT:    ushll v0.2d, v0.2s, #12213; CHECK-NEXT:    ret2214  %tmp1 = load <2 x i32>, ptr %A2215  %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>2216  %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>2217  ret <2 x i64> %tmp32218}2219 2220define <8 x i16> @ushll2_8h(ptr %A) nounwind {2221; CHECK-SD-LABEL: ushll2_8h:2222; CHECK-SD:       // %bb.0:2223; CHECK-SD-NEXT:    ldr d0, [x0, #8]2224; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #12225; CHECK-SD-NEXT:    ret2226;2227; CHECK-GI-LABEL: ushll2_8h:2228; CHECK-GI:       // %bb.0:2229; CHECK-GI-NEXT:    ldr q0, [x0]2230; CHECK-GI-NEXT:    mov d0, v0.d[1]2231; CHECK-GI-NEXT:    ushll v0.8h, v0.8b, #12232; CHECK-GI-NEXT:    ret2233  %load1 = load <16 x i8>, ptr %A2234  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2235  %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>2236  %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2237  ret <8 x i16> %tmp32238}2239 2240define <4 x i32> @ushll2_4s(ptr %A) nounwind {2241; CHECK-SD-LABEL: ushll2_4s:2242; CHECK-SD:       // %bb.0:2243; CHECK-SD-NEXT:    ldr d0, [x0, #8]2244; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #12245; CHECK-SD-NEXT:    ret2246;2247; CHECK-GI-LABEL: ushll2_4s:2248; CHECK-GI:       // %bb.0:2249; CHECK-GI-NEXT:    ldr q0, [x0]2250; CHECK-GI-NEXT:    mov d0, v0.d[1]2251; CHECK-GI-NEXT:    ushll v0.4s, v0.4h, #12252; CHECK-GI-NEXT:    ret2253  %load1 = load <8 x i16>, ptr %A2254  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2255  %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>2256  %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>2257  ret <4 x i32> %tmp32258}2259 2260define <2 x i64> @ushll2_2d(ptr %A) nounwind {2261; CHECK-SD-LABEL: ushll2_2d:2262; CHECK-SD:       // %bb.0:2263; CHECK-SD-NEXT:    ldr d0, [x0, #8]2264; CHECK-SD-NEXT:    ushll v0.2d, v0.2s, #12265; CHECK-SD-NEXT:    ret2266;2267; CHECK-GI-LABEL: ushll2_2d:2268; CHECK-GI:       // %bb.0:2269; CHECK-GI-NEXT:    ldr q0, [x0]2270; CHECK-GI-NEXT:    mov d0, v0.d[1]2271; CHECK-GI-NEXT:    ushll v0.2d, v0.2s, #12272; CHECK-GI-NEXT:    ret2273  %load1 = load <4 x i32>, ptr %A2274  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2275  %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>2276  %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>2277  ret <2 x i64> %tmp32278}2279 2280declare <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8>, <16 x i8>)2281declare <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16>, <8 x i16>)2282declare <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32>, <4 x i32>)2283declare <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64>, <2 x i64>)2284declare <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64>, <1 x i64>)2285declare i64 @llvm.aarch64.neon.ushl.i64(i64, i64)2286 2287define <8 x i16> @neon_ushll8h_constant_shift(ptr %A) nounwind {2288; CHECK-SD-LABEL: neon_ushll8h_constant_shift:2289; CHECK-SD:       // %bb.0:2290; CHECK-SD-NEXT:    ldr d0, [x0]2291; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #12292; CHECK-SD-NEXT:    ret2293;2294; CHECK-GI-LABEL: neon_ushll8h_constant_shift:2295; CHECK-GI:       // %bb.0:2296; CHECK-GI-NEXT:    ldr d0, [x0]2297; CHECK-GI-NEXT:    movi v1.8h, #12298; CHECK-GI-NEXT:    ushll v0.8h, v0.8b, #02299; CHECK-GI-NEXT:    ushl v0.8h, v0.8h, v1.8h2300; CHECK-GI-NEXT:    ret2301  %tmp1 = load <8 x i8>, ptr %A2302  %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>2303  %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)2304  ret <8 x i16> %tmp32305}2306 2307define <8 x i16> @neon_ushl8h_no_constant_shift(ptr %A) nounwind {2308; CHECK-LABEL: neon_ushl8h_no_constant_shift:2309; CHECK:       // %bb.0:2310; CHECK-NEXT:    ldr d0, [x0]2311; CHECK-NEXT:    ushll v0.8h, v0.8b, #02312; CHECK-NEXT:    ushl v0.8h, v0.8h, v0.8h2313; CHECK-NEXT:    ret2314  %tmp1 = load <8 x i8>, ptr %A2315  %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>2316  %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp2)2317  ret <8 x i16> %tmp32318}2319 2320define <4 x i32> @neon_ushl8h_constant_shift_extend_not_2x(ptr %A) nounwind {2321; CHECK-SD-LABEL: neon_ushl8h_constant_shift_extend_not_2x:2322; CHECK-SD:       // %bb.0:2323; CHECK-SD-NEXT:    ldr s0, [x0]2324; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #02325; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #12326; CHECK-SD-NEXT:    ret2327;2328; CHECK-GI-LABEL: neon_ushl8h_constant_shift_extend_not_2x:2329; CHECK-GI:       // %bb.0:2330; CHECK-GI-NEXT:    ldr w8, [x0]2331; CHECK-GI-NEXT:    movi v0.4s, #12332; CHECK-GI-NEXT:    fmov s1, w82333; CHECK-GI-NEXT:    uxtb w8, w82334; CHECK-GI-NEXT:    mov b2, v1.b[2]2335; CHECK-GI-NEXT:    mov b3, v1.b[1]2336; CHECK-GI-NEXT:    mov b4, v1.b[3]2337; CHECK-GI-NEXT:    fmov s1, w82338; CHECK-GI-NEXT:    fmov w9, s22339; CHECK-GI-NEXT:    fmov w10, s32340; CHECK-GI-NEXT:    fmov w11, s42341; CHECK-GI-NEXT:    uxtb w9, w92342; CHECK-GI-NEXT:    uxtb w10, w102343; CHECK-GI-NEXT:    uxtb w11, w112344; CHECK-GI-NEXT:    fmov s2, w92345; CHECK-GI-NEXT:    mov v1.h[1], w102346; CHECK-GI-NEXT:    mov v2.h[1], w112347; CHECK-GI-NEXT:    ushll v1.4s, v1.4h, #02348; CHECK-GI-NEXT:    ushll v2.4s, v2.4h, #02349; CHECK-GI-NEXT:    mov v1.d[1], v2.d[0]2350; CHECK-GI-NEXT:    ushl v0.4s, v1.4s, v0.4s2351; CHECK-GI-NEXT:    ret2352  %tmp1 = load <4 x i8>, ptr %A2353  %tmp2 = zext <4 x i8> %tmp1 to <4 x i32>2354  %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2355  ret <4 x i32> %tmp32356}2357 2358define <8 x i16> @neon_ushl8_noext_constant_shift(ptr %A) nounwind {2359; CHECK-SD-LABEL: neon_ushl8_noext_constant_shift:2360; CHECK-SD:       // %bb.0:2361; CHECK-SD-NEXT:    ldr q0, [x0]2362; CHECK-SD-NEXT:    add v0.8h, v0.8h, v0.8h2363; CHECK-SD-NEXT:    ret2364;2365; CHECK-GI-LABEL: neon_ushl8_noext_constant_shift:2366; CHECK-GI:       // %bb.0:2367; CHECK-GI-NEXT:    movi v0.8h, #12368; CHECK-GI-NEXT:    ldr q1, [x0]2369; CHECK-GI-NEXT:    ushl v0.8h, v1.8h, v0.8h2370; CHECK-GI-NEXT:    ret2371  %tmp1 = load <8 x i16>, ptr %A2372  %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)2373  ret <8 x i16> %tmp32374}2375 2376define <4 x i32> @neon_ushll4s_constant_shift(ptr %A) nounwind {2377; CHECK-SD-LABEL: neon_ushll4s_constant_shift:2378; CHECK-SD:       // %bb.0:2379; CHECK-SD-NEXT:    ldr d0, [x0]2380; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #12381; CHECK-SD-NEXT:    ret2382;2383; CHECK-GI-LABEL: neon_ushll4s_constant_shift:2384; CHECK-GI:       // %bb.0:2385; CHECK-GI-NEXT:    ldr d0, [x0]2386; CHECK-GI-NEXT:    movi v1.4s, #12387; CHECK-GI-NEXT:    ushll v0.4s, v0.4h, #02388; CHECK-GI-NEXT:    ushl v0.4s, v0.4s, v1.4s2389; CHECK-GI-NEXT:    ret2390  %tmp1 = load <4 x i16>, ptr %A2391  %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>2392  %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2393  ret <4 x i32> %tmp32394}2395 2396; FIXME: unnecessary ushll.4s v0, v0, #0?2397define <4 x i32> @neon_ushll4s_neg_constant_shift(ptr %A) nounwind {2398; CHECK-SD-LABEL: neon_ushll4s_neg_constant_shift:2399; CHECK-SD:       // %bb.0:2400; CHECK-SD-NEXT:    ldr d0, [x0]2401; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #02402; CHECK-SD-NEXT:    ushr v0.4s, v0.4s, #12403; CHECK-SD-NEXT:    ret2404;2405; CHECK-GI-LABEL: neon_ushll4s_neg_constant_shift:2406; CHECK-GI:       // %bb.0:2407; CHECK-GI-NEXT:    ldr d0, [x0]2408; CHECK-GI-NEXT:    movi v1.2d, #0xffffffffffffffff2409; CHECK-GI-NEXT:    ushll v0.4s, v0.4h, #02410; CHECK-GI-NEXT:    ushl v0.4s, v0.4s, v1.4s2411; CHECK-GI-NEXT:    ret2412  %tmp1 = load <4 x i16>, ptr %A2413  %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>2414  %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)2415  ret <4 x i32> %tmp32416}2417 2418; FIXME: should be constant folded.2419define <4 x i32> @neon_ushll4s_constant_fold() nounwind {2420; CHECK-SD-LABEL: neon_ushll4s_constant_fold:2421; CHECK-SD:       // %bb.0:2422; CHECK-SD-NEXT:    adrp x8, .LCPI160_02423; CHECK-SD-NEXT:    ldr q0, [x8, :lo12:.LCPI160_0]2424; CHECK-SD-NEXT:    add v0.4s, v0.4s, v0.4s2425; CHECK-SD-NEXT:    ret2426;2427; CHECK-GI-LABEL: neon_ushll4s_constant_fold:2428; CHECK-GI:       // %bb.0:2429; CHECK-GI-NEXT:    movi v0.4s, #12430; CHECK-GI-NEXT:    adrp x8, .LCPI160_02431; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI160_0]2432; CHECK-GI-NEXT:    ushl v0.4s, v1.4s, v0.4s2433; CHECK-GI-NEXT:    ret2434  %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2435  ret <4 x i32> %tmp32436}2437 2438define <2 x i64> @neon_ushll2d_constant_shift(ptr %A) nounwind {2439; CHECK-SD-LABEL: neon_ushll2d_constant_shift:2440; CHECK-SD:       // %bb.0:2441; CHECK-SD-NEXT:    ldr d0, [x0]2442; CHECK-SD-NEXT:    ushll v0.2d, v0.2s, #12443; CHECK-SD-NEXT:    ret2444;2445; CHECK-GI-LABEL: neon_ushll2d_constant_shift:2446; CHECK-GI:       // %bb.0:2447; CHECK-GI-NEXT:    ldr d0, [x0]2448; CHECK-GI-NEXT:    adrp x8, .LCPI161_02449; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI161_0]2450; CHECK-GI-NEXT:    ushll v0.2d, v0.2s, #02451; CHECK-GI-NEXT:    ushl v0.2d, v0.2d, v1.2d2452; CHECK-GI-NEXT:    ret2453  %tmp1 = load <2 x i32>, ptr %A2454  %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>2455  %tmp3 = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)2456  ret <2 x i64> %tmp32457}2458 2459define <1 x i64> @neon_ushl_vscalar_constant_shift(ptr %A) nounwind {2460; CHECK-LABEL: neon_ushl_vscalar_constant_shift:2461; CHECK:       // %bb.0:2462; CHECK-NEXT:    movi v0.2d, #00000000000000002463; CHECK-NEXT:    ldr s1, [x0]2464; CHECK-NEXT:    zip1 v0.2s, v1.2s, v0.2s2465; CHECK-NEXT:    shl d0, d0, #12466; CHECK-NEXT:    ret2467  %tmp1 = load <1 x i32>, ptr %A2468  %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>2469  %tmp3 = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)2470  ret <1 x i64> %tmp32471}2472 2473define i64 @neon_ushl_scalar_constant_shift(ptr %A) nounwind {2474; CHECK-LABEL: neon_ushl_scalar_constant_shift:2475; CHECK:       // %bb.0:2476; CHECK-NEXT:    ldr w8, [x0]2477; CHECK-NEXT:    fmov d0, x82478; CHECK-NEXT:    shl d0, d0, #12479; CHECK-NEXT:    fmov x0, d02480; CHECK-NEXT:    ret2481  %tmp1 = load i32, ptr %A2482  %tmp2 = zext i32 %tmp1 to i642483  %tmp3 = call i64 @llvm.aarch64.neon.ushl.i64(i64 %tmp2, i64 1)2484  ret i64 %tmp32485}2486 2487define <8 x i16> @sshll8h(ptr %A) nounwind {2488; CHECK-LABEL: sshll8h:2489; CHECK:       // %bb.0:2490; CHECK-NEXT:    ldr d0, [x0]2491; CHECK-NEXT:    sshll v0.8h, v0.8b, #12492; CHECK-NEXT:    ret2493  %tmp1 = load <8 x i8>, ptr %A2494  %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>2495  %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2496  ret <8 x i16> %tmp32497}2498 2499define <2 x i64> @sshll2d(ptr %A) nounwind {2500; CHECK-LABEL: sshll2d:2501; CHECK:       // %bb.0:2502; CHECK-NEXT:    ldr d0, [x0]2503; CHECK-NEXT:    sshll v0.2d, v0.2s, #12504; CHECK-NEXT:    ret2505  %tmp1 = load <2 x i32>, ptr %A2506  %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>2507  %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>2508  ret <2 x i64> %tmp32509}2510 2511declare <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8>, <16 x i8>)2512declare <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16>, <8 x i16>)2513declare <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32>, <4 x i32>)2514declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)2515declare <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64>, <1 x i64>)2516declare i64 @llvm.aarch64.neon.sshl.i64(i64, i64)2517 2518define <16 x i8> @neon_sshl16b_constant_shift(ptr %A) nounwind {2519; CHECK-SD-LABEL: neon_sshl16b_constant_shift:2520; CHECK-SD:       // %bb.0:2521; CHECK-SD-NEXT:    ldr q0, [x0]2522; CHECK-SD-NEXT:    add v0.16b, v0.16b, v0.16b2523; CHECK-SD-NEXT:    ret2524;2525; CHECK-GI-LABEL: neon_sshl16b_constant_shift:2526; CHECK-GI:       // %bb.0:2527; CHECK-GI-NEXT:    movi v0.16b, #12528; CHECK-GI-NEXT:    ldr q1, [x0]2529; CHECK-GI-NEXT:    sshl v0.16b, v1.16b, v0.16b2530; CHECK-GI-NEXT:    ret2531  %tmp1 = load <16 x i8>, ptr %A2532  %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)2533  ret <16 x i8> %tmp22534}2535 2536define <16 x i8> @neon_sshl16b_non_splat_constant_shift(ptr %A) nounwind {2537; CHECK-SD-LABEL: neon_sshl16b_non_splat_constant_shift:2538; CHECK-SD:       // %bb.0:2539; CHECK-SD-NEXT:    adrp x8, .LCPI167_02540; CHECK-SD-NEXT:    ldr q0, [x0]2541; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI167_0]2542; CHECK-SD-NEXT:    sshl v0.16b, v0.16b, v1.16b2543; CHECK-SD-NEXT:    ret2544;2545; CHECK-GI-LABEL: neon_sshl16b_non_splat_constant_shift:2546; CHECK-GI:       // %bb.0:2547; CHECK-GI-NEXT:    adrp x8, .LCPI167_02548; CHECK-GI-NEXT:    ldr q1, [x0]2549; CHECK-GI-NEXT:    ldr q0, [x8, :lo12:.LCPI167_0]2550; CHECK-GI-NEXT:    sshl v0.16b, v1.16b, v0.16b2551; CHECK-GI-NEXT:    ret2552  %tmp1 = load <16 x i8>, ptr %A2553  %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 6, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)2554  ret <16 x i8> %tmp22555}2556 2557define <16 x i8> @neon_sshl16b_neg_constant_shift(ptr %A) nounwind {2558; CHECK-SD-LABEL: neon_sshl16b_neg_constant_shift:2559; CHECK-SD:       // %bb.0:2560; CHECK-SD-NEXT:    ldr q0, [x0]2561; CHECK-SD-NEXT:    sshr v0.16b, v0.16b, #22562; CHECK-SD-NEXT:    ret2563;2564; CHECK-GI-LABEL: neon_sshl16b_neg_constant_shift:2565; CHECK-GI:       // %bb.0:2566; CHECK-GI-NEXT:    movi v0.16b, #2542567; CHECK-GI-NEXT:    ldr q1, [x0]2568; CHECK-GI-NEXT:    sshl v0.16b, v1.16b, v0.16b2569; CHECK-GI-NEXT:    ret2570  %tmp1 = load <16 x i8>, ptr %A2571  %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>)2572  ret <16 x i8> %tmp22573}2574 2575define <8 x i16> @neon_sshll8h_constant_shift(ptr %A) nounwind {2576; CHECK-SD-LABEL: neon_sshll8h_constant_shift:2577; CHECK-SD:       // %bb.0:2578; CHECK-SD-NEXT:    ldr d0, [x0]2579; CHECK-SD-NEXT:    sshll v0.8h, v0.8b, #12580; CHECK-SD-NEXT:    ret2581;2582; CHECK-GI-LABEL: neon_sshll8h_constant_shift:2583; CHECK-GI:       // %bb.0:2584; CHECK-GI-NEXT:    ldr d0, [x0]2585; CHECK-GI-NEXT:    movi v1.8h, #12586; CHECK-GI-NEXT:    sshll v0.8h, v0.8b, #02587; CHECK-GI-NEXT:    sshl v0.8h, v0.8h, v1.8h2588; CHECK-GI-NEXT:    ret2589  %tmp1 = load <8 x i8>, ptr %A2590  %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>2591  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)2592  ret <8 x i16> %tmp32593}2594 2595define <4 x i32> @neon_sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {2596; CHECK-SD-LABEL: neon_sshl4s_wrong_ext_constant_shift:2597; CHECK-SD:       // %bb.0:2598; CHECK-SD-NEXT:    ldr s0, [x0]2599; CHECK-SD-NEXT:    sshll v0.8h, v0.8b, #02600; CHECK-SD-NEXT:    sshll v0.4s, v0.4h, #12601; CHECK-SD-NEXT:    ret2602;2603; CHECK-GI-LABEL: neon_sshl4s_wrong_ext_constant_shift:2604; CHECK-GI:       // %bb.0:2605; CHECK-GI-NEXT:    ldr w8, [x0]2606; CHECK-GI-NEXT:    movi v0.4s, #12607; CHECK-GI-NEXT:    fmov s1, w82608; CHECK-GI-NEXT:    sxtb w8, w82609; CHECK-GI-NEXT:    mov b2, v1.b[2]2610; CHECK-GI-NEXT:    mov b3, v1.b[1]2611; CHECK-GI-NEXT:    mov b4, v1.b[3]2612; CHECK-GI-NEXT:    fmov s1, w82613; CHECK-GI-NEXT:    fmov w9, s22614; CHECK-GI-NEXT:    fmov w10, s32615; CHECK-GI-NEXT:    fmov w11, s42616; CHECK-GI-NEXT:    sxtb w9, w92617; CHECK-GI-NEXT:    sxtb w10, w102618; CHECK-GI-NEXT:    sxtb w11, w112619; CHECK-GI-NEXT:    fmov s2, w92620; CHECK-GI-NEXT:    mov v1.h[1], w102621; CHECK-GI-NEXT:    mov v2.h[1], w112622; CHECK-GI-NEXT:    sshll v1.4s, v1.4h, #02623; CHECK-GI-NEXT:    sshll v2.4s, v2.4h, #02624; CHECK-GI-NEXT:    mov v1.d[1], v2.d[0]2625; CHECK-GI-NEXT:    sshl v0.4s, v1.4s, v0.4s2626; CHECK-GI-NEXT:    ret2627  %tmp1 = load <4 x i8>, ptr %A2628  %tmp2 = sext <4 x i8> %tmp1 to <4 x i32>2629  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2630  ret <4 x i32> %tmp32631}2632 2633define <4 x i32> @neon_sshll4s_constant_shift(ptr %A) nounwind {2634; CHECK-SD-LABEL: neon_sshll4s_constant_shift:2635; CHECK-SD:       // %bb.0:2636; CHECK-SD-NEXT:    ldr d0, [x0]2637; CHECK-SD-NEXT:    sshll v0.4s, v0.4h, #12638; CHECK-SD-NEXT:    ret2639;2640; CHECK-GI-LABEL: neon_sshll4s_constant_shift:2641; CHECK-GI:       // %bb.0:2642; CHECK-GI-NEXT:    ldr d0, [x0]2643; CHECK-GI-NEXT:    movi v1.4s, #12644; CHECK-GI-NEXT:    sshll v0.4s, v0.4h, #02645; CHECK-GI-NEXT:    sshl v0.4s, v0.4s, v1.4s2646; CHECK-GI-NEXT:    ret2647  %tmp1 = load <4 x i16>, ptr %A2648  %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>2649  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2650  ret <4 x i32> %tmp32651}2652 2653define <4 x i32> @neon_sshll4s_neg_constant_shift(ptr %A) nounwind {2654; CHECK-SD-LABEL: neon_sshll4s_neg_constant_shift:2655; CHECK-SD:       // %bb.0:2656; CHECK-SD-NEXT:    ldr d0, [x0]2657; CHECK-SD-NEXT:    sshll v0.4s, v0.4h, #02658; CHECK-SD-NEXT:    sshr v0.4s, v0.4s, #12659; CHECK-SD-NEXT:    ret2660;2661; CHECK-GI-LABEL: neon_sshll4s_neg_constant_shift:2662; CHECK-GI:       // %bb.0:2663; CHECK-GI-NEXT:    ldr d0, [x0]2664; CHECK-GI-NEXT:    movi v1.2d, #0xffffffffffffffff2665; CHECK-GI-NEXT:    sshll v0.4s, v0.4h, #02666; CHECK-GI-NEXT:    sshl v0.4s, v0.4s, v1.4s2667; CHECK-GI-NEXT:    ret2668  %tmp1 = load <4 x i16>, ptr %A2669  %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>2670  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)2671  ret <4 x i32> %tmp32672}2673 2674; FIXME: should be constant folded.2675define <4 x i32> @neon_sshl4s_constant_fold() nounwind {2676; CHECK-SD-LABEL: neon_sshl4s_constant_fold:2677; CHECK-SD:       // %bb.0:2678; CHECK-SD-NEXT:    adrp x8, .LCPI173_02679; CHECK-SD-NEXT:    ldr q0, [x8, :lo12:.LCPI173_0]2680; CHECK-SD-NEXT:    shl v0.4s, v0.4s, #22681; CHECK-SD-NEXT:    ret2682;2683; CHECK-GI-LABEL: neon_sshl4s_constant_fold:2684; CHECK-GI:       // %bb.0:2685; CHECK-GI-NEXT:    movi v0.4s, #22686; CHECK-GI-NEXT:    adrp x8, .LCPI173_02687; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI173_0]2688; CHECK-GI-NEXT:    sshl v0.4s, v1.4s, v0.4s2689; CHECK-GI-NEXT:    ret2690  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)2691  ret <4 x i32> %tmp32692}2693 2694define <4 x i32> @neon_sshl4s_no_fold(ptr %A) nounwind {2695; CHECK-SD-LABEL: neon_sshl4s_no_fold:2696; CHECK-SD:       // %bb.0:2697; CHECK-SD-NEXT:    ldr q0, [x0]2698; CHECK-SD-NEXT:    add v0.4s, v0.4s, v0.4s2699; CHECK-SD-NEXT:    ret2700;2701; CHECK-GI-LABEL: neon_sshl4s_no_fold:2702; CHECK-GI:       // %bb.0:2703; CHECK-GI-NEXT:    movi v0.4s, #12704; CHECK-GI-NEXT:    ldr q1, [x0]2705; CHECK-GI-NEXT:    sshl v0.4s, v1.4s, v0.4s2706; CHECK-GI-NEXT:    ret2707  %tmp1 = load <4 x i32>, ptr %A2708  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2709  ret <4 x i32> %tmp32710}2711 2712define <2 x i64> @neon_sshll2d_constant_shift(ptr %A) nounwind {2713; CHECK-SD-LABEL: neon_sshll2d_constant_shift:2714; CHECK-SD:       // %bb.0:2715; CHECK-SD-NEXT:    ldr d0, [x0]2716; CHECK-SD-NEXT:    sshll v0.2d, v0.2s, #12717; CHECK-SD-NEXT:    ret2718;2719; CHECK-GI-LABEL: neon_sshll2d_constant_shift:2720; CHECK-GI:       // %bb.0:2721; CHECK-GI-NEXT:    ldr d0, [x0]2722; CHECK-GI-NEXT:    adrp x8, .LCPI175_02723; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI175_0]2724; CHECK-GI-NEXT:    sshll v0.2d, v0.2s, #02725; CHECK-GI-NEXT:    sshl v0.2d, v0.2d, v1.2d2726; CHECK-GI-NEXT:    ret2727  %tmp1 = load <2 x i32>, ptr %A2728  %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>2729  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)2730  ret <2 x i64> %tmp32731}2732 2733define <1 x i64> @neon_sshll_vscalar_constant_shift(ptr %A) nounwind {2734; CHECK-LABEL: neon_sshll_vscalar_constant_shift:2735; CHECK:       // %bb.0:2736; CHECK-NEXT:    movi v0.2d, #00000000000000002737; CHECK-NEXT:    ldr s1, [x0]2738; CHECK-NEXT:    zip1 v0.2s, v1.2s, v0.2s2739; CHECK-NEXT:    shl d0, d0, #12740; CHECK-NEXT:    ret2741  %tmp1 = load <1 x i32>, ptr %A2742  %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>2743  %tmp3 = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)2744  ret <1 x i64> %tmp32745}2746 2747define i64 @neon_sshll_scalar_constant_shift(ptr %A) nounwind {2748; CHECK-LABEL: neon_sshll_scalar_constant_shift:2749; CHECK:       // %bb.0:2750; CHECK-NEXT:    ldr w8, [x0]2751; CHECK-NEXT:    fmov d0, x82752; CHECK-NEXT:    shl d0, d0, #12753; CHECK-NEXT:    fmov x0, d02754; CHECK-NEXT:    ret2755  %tmp1 = load i32, ptr %A2756  %tmp2 = zext i32 %tmp1 to i642757  %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 1)2758  ret i64 %tmp32759}2760 2761define i64 @neon_sshll_scalar_constant_shift_m1(ptr %A) nounwind {2762; CHECK-LABEL: neon_sshll_scalar_constant_shift_m1:2763; CHECK:       // %bb.0:2764; CHECK-NEXT:    ldr w8, [x0]2765; CHECK-NEXT:    fmov d0, x82766; CHECK-NEXT:    sshr d0, d0, #12767; CHECK-NEXT:    fmov x0, d02768; CHECK-NEXT:    ret2769  %tmp1 = load i32, ptr %A2770  %tmp2 = zext i32 %tmp1 to i642771  %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 -1)2772  ret i64 %tmp32773}2774 2775; FIXME: should be constant folded.2776define <2 x i64> @neon_sshl2d_constant_fold() nounwind {2777; CHECK-SD-LABEL: neon_sshl2d_constant_fold:2778; CHECK-SD:       // %bb.0:2779; CHECK-SD-NEXT:    adrp x8, .LCPI179_02780; CHECK-SD-NEXT:    ldr q0, [x8, :lo12:.LCPI179_0]2781; CHECK-SD-NEXT:    add v0.2d, v0.2d, v0.2d2782; CHECK-SD-NEXT:    ret2783;2784; CHECK-GI-LABEL: neon_sshl2d_constant_fold:2785; CHECK-GI:       // %bb.0:2786; CHECK-GI-NEXT:    adrp x8, .LCPI179_12787; CHECK-GI-NEXT:    adrp x9, .LCPI179_02788; CHECK-GI-NEXT:    ldr q0, [x8, :lo12:.LCPI179_1]2789; CHECK-GI-NEXT:    ldr q1, [x9, :lo12:.LCPI179_0]2790; CHECK-GI-NEXT:    sshl v0.2d, v0.2d, v1.2d2791; CHECK-GI-NEXT:    ret2792  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> <i64 1, i64 1>)2793  ret <2 x i64> %tmp32794}2795 2796define <2 x i64> @neon_sshl2d_no_fold(ptr %A) nounwind {2797; CHECK-SD-LABEL: neon_sshl2d_no_fold:2798; CHECK-SD:       // %bb.0:2799; CHECK-SD-NEXT:    ldr q0, [x0]2800; CHECK-SD-NEXT:    shl v0.2d, v0.2d, #22801; CHECK-SD-NEXT:    ret2802;2803; CHECK-GI-LABEL: neon_sshl2d_no_fold:2804; CHECK-GI:       // %bb.0:2805; CHECK-GI-NEXT:    adrp x8, .LCPI180_02806; CHECK-GI-NEXT:    ldr q1, [x0]2807; CHECK-GI-NEXT:    ldr q0, [x8, :lo12:.LCPI180_0]2808; CHECK-GI-NEXT:    sshl v0.2d, v1.2d, v0.2d2809; CHECK-GI-NEXT:    ret2810  %tmp2 = load <2 x i64>, ptr %A2811  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 2, i64 2>)2812  ret <2 x i64> %tmp32813}2814 2815define <8 x i16> @sshll2_8h(ptr %A) nounwind {2816; CHECK-SD-LABEL: sshll2_8h:2817; CHECK-SD:       // %bb.0:2818; CHECK-SD-NEXT:    ldr d0, [x0, #8]2819; CHECK-SD-NEXT:    sshll v0.8h, v0.8b, #12820; CHECK-SD-NEXT:    ret2821;2822; CHECK-GI-LABEL: sshll2_8h:2823; CHECK-GI:       // %bb.0:2824; CHECK-GI-NEXT:    ldr q0, [x0]2825; CHECK-GI-NEXT:    mov d0, v0.d[1]2826; CHECK-GI-NEXT:    sshll v0.8h, v0.8b, #12827; CHECK-GI-NEXT:    ret2828  %load1 = load <16 x i8>, ptr %A2829  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2830  %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>2831  %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2832  ret <8 x i16> %tmp32833}2834 2835define <4 x i32> @sshll2_4s(ptr %A) nounwind {2836; CHECK-SD-LABEL: sshll2_4s:2837; CHECK-SD:       // %bb.0:2838; CHECK-SD-NEXT:    ldr d0, [x0, #8]2839; CHECK-SD-NEXT:    sshll v0.4s, v0.4h, #12840; CHECK-SD-NEXT:    ret2841;2842; CHECK-GI-LABEL: sshll2_4s:2843; CHECK-GI:       // %bb.0:2844; CHECK-GI-NEXT:    ldr q0, [x0]2845; CHECK-GI-NEXT:    mov d0, v0.d[1]2846; CHECK-GI-NEXT:    sshll v0.4s, v0.4h, #12847; CHECK-GI-NEXT:    ret2848  %load1 = load <8 x i16>, ptr %A2849  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2850  %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>2851  %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>2852  ret <4 x i32> %tmp32853}2854 2855define <2 x i64> @sshll2_2d(ptr %A) nounwind {2856; CHECK-SD-LABEL: sshll2_2d:2857; CHECK-SD:       // %bb.0:2858; CHECK-SD-NEXT:    ldr d0, [x0, #8]2859; CHECK-SD-NEXT:    sshll v0.2d, v0.2s, #12860; CHECK-SD-NEXT:    ret2861;2862; CHECK-GI-LABEL: sshll2_2d:2863; CHECK-GI:       // %bb.0:2864; CHECK-GI-NEXT:    ldr q0, [x0]2865; CHECK-GI-NEXT:    mov d0, v0.d[1]2866; CHECK-GI-NEXT:    sshll v0.2d, v0.2s, #12867; CHECK-GI-NEXT:    ret2868  %load1 = load <4 x i32>, ptr %A2869  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2870  %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>2871  %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>2872  ret <2 x i64> %tmp32873}2874 2875define <8 x i8> @sqshli8b(ptr %A) nounwind {2876; CHECK-SD-LABEL: sqshli8b:2877; CHECK-SD:       // %bb.0:2878; CHECK-SD-NEXT:    ldr d0, [x0]2879; CHECK-SD-NEXT:    sqshl v0.8b, v0.8b, #12880; CHECK-SD-NEXT:    ret2881;2882; CHECK-GI-LABEL: sqshli8b:2883; CHECK-GI:       // %bb.0:2884; CHECK-GI-NEXT:    movi v0.8b, #12885; CHECK-GI-NEXT:    ldr d1, [x0]2886; CHECK-GI-NEXT:    sqshl v0.8b, v1.8b, v0.8b2887; CHECK-GI-NEXT:    ret2888  %tmp1 = load <8 x i8>, ptr %A2889  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)2890  ret <8 x i8> %tmp32891}2892 2893define <4 x i16> @sqshli4h(ptr %A) nounwind {2894; CHECK-SD-LABEL: sqshli4h:2895; CHECK-SD:       // %bb.0:2896; CHECK-SD-NEXT:    ldr d0, [x0]2897; CHECK-SD-NEXT:    sqshl v0.4h, v0.4h, #12898; CHECK-SD-NEXT:    ret2899;2900; CHECK-GI-LABEL: sqshli4h:2901; CHECK-GI:       // %bb.0:2902; CHECK-GI-NEXT:    movi v0.4h, #12903; CHECK-GI-NEXT:    ldr d1, [x0]2904; CHECK-GI-NEXT:    sqshl v0.4h, v1.4h, v0.4h2905; CHECK-GI-NEXT:    ret2906  %tmp1 = load <4 x i16>, ptr %A2907  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)2908  ret <4 x i16> %tmp32909}2910 2911define <2 x i32> @sqshli2s(ptr %A) nounwind {2912; CHECK-SD-LABEL: sqshli2s:2913; CHECK-SD:       // %bb.0:2914; CHECK-SD-NEXT:    ldr d0, [x0]2915; CHECK-SD-NEXT:    sqshl v0.2s, v0.2s, #12916; CHECK-SD-NEXT:    ret2917;2918; CHECK-GI-LABEL: sqshli2s:2919; CHECK-GI:       // %bb.0:2920; CHECK-GI-NEXT:    movi v0.2s, #12921; CHECK-GI-NEXT:    ldr d1, [x0]2922; CHECK-GI-NEXT:    sqshl v0.2s, v1.2s, v0.2s2923; CHECK-GI-NEXT:    ret2924  %tmp1 = load <2 x i32>, ptr %A2925  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)2926  ret <2 x i32> %tmp32927}2928 2929define <16 x i8> @sqshli16b(ptr %A) nounwind {2930; CHECK-SD-LABEL: sqshli16b:2931; CHECK-SD:       // %bb.0:2932; CHECK-SD-NEXT:    ldr q0, [x0]2933; CHECK-SD-NEXT:    sqshl v0.16b, v0.16b, #12934; CHECK-SD-NEXT:    ret2935;2936; CHECK-GI-LABEL: sqshli16b:2937; CHECK-GI:       // %bb.0:2938; CHECK-GI-NEXT:    movi v0.16b, #12939; CHECK-GI-NEXT:    ldr q1, [x0]2940; CHECK-GI-NEXT:    sqshl v0.16b, v1.16b, v0.16b2941; CHECK-GI-NEXT:    ret2942  %tmp1 = load <16 x i8>, ptr %A2943  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)2944  ret <16 x i8> %tmp32945}2946 2947define <8 x i16> @sqshli8h(ptr %A) nounwind {2948; CHECK-SD-LABEL: sqshli8h:2949; CHECK-SD:       // %bb.0:2950; CHECK-SD-NEXT:    ldr q0, [x0]2951; CHECK-SD-NEXT:    sqshl v0.8h, v0.8h, #12952; CHECK-SD-NEXT:    ret2953;2954; CHECK-GI-LABEL: sqshli8h:2955; CHECK-GI:       // %bb.0:2956; CHECK-GI-NEXT:    movi v0.8h, #12957; CHECK-GI-NEXT:    ldr q1, [x0]2958; CHECK-GI-NEXT:    sqshl v0.8h, v1.8h, v0.8h2959; CHECK-GI-NEXT:    ret2960  %tmp1 = load <8 x i16>, ptr %A2961  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)2962  ret <8 x i16> %tmp32963}2964 2965define <4 x i32> @sqshli4s(ptr %A) nounwind {2966; CHECK-SD-LABEL: sqshli4s:2967; CHECK-SD:       // %bb.0:2968; CHECK-SD-NEXT:    ldr q0, [x0]2969; CHECK-SD-NEXT:    sqshl v0.4s, v0.4s, #12970; CHECK-SD-NEXT:    ret2971;2972; CHECK-GI-LABEL: sqshli4s:2973; CHECK-GI:       // %bb.0:2974; CHECK-GI-NEXT:    movi v0.4s, #12975; CHECK-GI-NEXT:    ldr q1, [x0]2976; CHECK-GI-NEXT:    sqshl v0.4s, v1.4s, v0.4s2977; CHECK-GI-NEXT:    ret2978  %tmp1 = load <4 x i32>, ptr %A2979  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)2980  ret <4 x i32> %tmp32981}2982 2983define <2 x i64> @sqshli2d(ptr %A) nounwind {2984; CHECK-SD-LABEL: sqshli2d:2985; CHECK-SD:       // %bb.0:2986; CHECK-SD-NEXT:    ldr q0, [x0]2987; CHECK-SD-NEXT:    sqshl v0.2d, v0.2d, #12988; CHECK-SD-NEXT:    ret2989;2990; CHECK-GI-LABEL: sqshli2d:2991; CHECK-GI:       // %bb.0:2992; CHECK-GI-NEXT:    adrp x8, .LCPI190_02993; CHECK-GI-NEXT:    ldr q1, [x0]2994; CHECK-GI-NEXT:    ldr q0, [x8, :lo12:.LCPI190_0]2995; CHECK-GI-NEXT:    sqshl v0.2d, v1.2d, v0.2d2996; CHECK-GI-NEXT:    ret2997  %tmp1 = load <2 x i64>, ptr %A2998  %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)2999  ret <2 x i64> %tmp33000}3001 3002define <8 x i8> @uqshli8b(ptr %A) nounwind {3003; CHECK-SD-LABEL: uqshli8b:3004; CHECK-SD:       // %bb.0:3005; CHECK-SD-NEXT:    ldr d0, [x0]3006; CHECK-SD-NEXT:    uqshl v0.8b, v0.8b, #13007; CHECK-SD-NEXT:    ret3008;3009; CHECK-GI-LABEL: uqshli8b:3010; CHECK-GI:       // %bb.0:3011; CHECK-GI-NEXT:    movi v0.8b, #13012; CHECK-GI-NEXT:    ldr d1, [x0]3013; CHECK-GI-NEXT:    uqshl v0.8b, v1.8b, v0.8b3014; CHECK-GI-NEXT:    ret3015  %tmp1 = load <8 x i8>, ptr %A3016  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)3017  ret <8 x i8> %tmp33018}3019 3020define <8 x i8> @uqshli8b_1(ptr %A) nounwind {3021; CHECK-LABEL: uqshli8b_1:3022; CHECK:       // %bb.0:3023; CHECK-NEXT:    movi v0.8b, #83024; CHECK-NEXT:    ldr d1, [x0]3025; CHECK-NEXT:    uqshl v0.8b, v1.8b, v0.8b3026; CHECK-NEXT:    ret3027  %tmp1 = load <8 x i8>, ptr %A3028  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)3029  ret <8 x i8> %tmp33030}3031 3032define <4 x i16> @uqshli4h(ptr %A) nounwind {3033; CHECK-SD-LABEL: uqshli4h:3034; CHECK-SD:       // %bb.0:3035; CHECK-SD-NEXT:    ldr d0, [x0]3036; CHECK-SD-NEXT:    uqshl v0.4h, v0.4h, #13037; CHECK-SD-NEXT:    ret3038;3039; CHECK-GI-LABEL: uqshli4h:3040; CHECK-GI:       // %bb.0:3041; CHECK-GI-NEXT:    movi v0.4h, #13042; CHECK-GI-NEXT:    ldr d1, [x0]3043; CHECK-GI-NEXT:    uqshl v0.4h, v1.4h, v0.4h3044; CHECK-GI-NEXT:    ret3045  %tmp1 = load <4 x i16>, ptr %A3046  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)3047  ret <4 x i16> %tmp33048}3049 3050define <2 x i32> @uqshli2s(ptr %A) nounwind {3051; CHECK-SD-LABEL: uqshli2s:3052; CHECK-SD:       // %bb.0:3053; CHECK-SD-NEXT:    ldr d0, [x0]3054; CHECK-SD-NEXT:    uqshl v0.2s, v0.2s, #13055; CHECK-SD-NEXT:    ret3056;3057; CHECK-GI-LABEL: uqshli2s:3058; CHECK-GI:       // %bb.0:3059; CHECK-GI-NEXT:    movi v0.2s, #13060; CHECK-GI-NEXT:    ldr d1, [x0]3061; CHECK-GI-NEXT:    uqshl v0.2s, v1.2s, v0.2s3062; CHECK-GI-NEXT:    ret3063  %tmp1 = load <2 x i32>, ptr %A3064  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)3065  ret <2 x i32> %tmp33066}3067 3068define <16 x i8> @uqshli16b(ptr %A) nounwind {3069; CHECK-SD-LABEL: uqshli16b:3070; CHECK-SD:       // %bb.0:3071; CHECK-SD-NEXT:    ldr q0, [x0]3072; CHECK-SD-NEXT:    uqshl v0.16b, v0.16b, #13073; CHECK-SD-NEXT:    ret3074;3075; CHECK-GI-LABEL: uqshli16b:3076; CHECK-GI:       // %bb.0:3077; CHECK-GI-NEXT:    movi v0.16b, #13078; CHECK-GI-NEXT:    ldr q1, [x0]3079; CHECK-GI-NEXT:    uqshl v0.16b, v1.16b, v0.16b3080; CHECK-GI-NEXT:    ret3081  %tmp1 = load <16 x i8>, ptr %A3082  %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)3083  ret <16 x i8> %tmp33084}3085 3086define <8 x i16> @uqshli8h(ptr %A) nounwind {3087; CHECK-SD-LABEL: uqshli8h:3088; CHECK-SD:       // %bb.0:3089; CHECK-SD-NEXT:    ldr q0, [x0]3090; CHECK-SD-NEXT:    uqshl v0.8h, v0.8h, #13091; CHECK-SD-NEXT:    ret3092;3093; CHECK-GI-LABEL: uqshli8h:3094; CHECK-GI:       // %bb.0:3095; CHECK-GI-NEXT:    movi v0.8h, #13096; CHECK-GI-NEXT:    ldr q1, [x0]3097; CHECK-GI-NEXT:    uqshl v0.8h, v1.8h, v0.8h3098; CHECK-GI-NEXT:    ret3099  %tmp1 = load <8 x i16>, ptr %A3100  %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)3101  ret <8 x i16> %tmp33102}3103 3104define <4 x i32> @uqshli4s(ptr %A) nounwind {3105; CHECK-SD-LABEL: uqshli4s:3106; CHECK-SD:       // %bb.0:3107; CHECK-SD-NEXT:    ldr q0, [x0]3108; CHECK-SD-NEXT:    uqshl v0.4s, v0.4s, #13109; CHECK-SD-NEXT:    ret3110;3111; CHECK-GI-LABEL: uqshli4s:3112; CHECK-GI:       // %bb.0:3113; CHECK-GI-NEXT:    movi v0.4s, #13114; CHECK-GI-NEXT:    ldr q1, [x0]3115; CHECK-GI-NEXT:    uqshl v0.4s, v1.4s, v0.4s3116; CHECK-GI-NEXT:    ret3117  %tmp1 = load <4 x i32>, ptr %A3118  %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)3119  ret <4 x i32> %tmp33120}3121 3122define <2 x i64> @uqshli2d(ptr %A) nounwind {3123; CHECK-SD-LABEL: uqshli2d:3124; CHECK-SD:       // %bb.0:3125; CHECK-SD-NEXT:    ldr q0, [x0]3126; CHECK-SD-NEXT:    uqshl v0.2d, v0.2d, #13127; CHECK-SD-NEXT:    ret3128;3129; CHECK-GI-LABEL: uqshli2d:3130; CHECK-GI:       // %bb.0:3131; CHECK-GI-NEXT:    adrp x8, .LCPI198_03132; CHECK-GI-NEXT:    ldr q1, [x0]3133; CHECK-GI-NEXT:    ldr q0, [x8, :lo12:.LCPI198_0]3134; CHECK-GI-NEXT:    uqshl v0.2d, v1.2d, v0.2d3135; CHECK-GI-NEXT:    ret3136  %tmp1 = load <2 x i64>, ptr %A3137  %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)3138  ret <2 x i64> %tmp33139}3140 3141define <8 x i8> @ursra8b(ptr %A, ptr %B) nounwind {3142; CHECK-SD-LABEL: ursra8b:3143; CHECK-SD:       // %bb.0:3144; CHECK-SD-NEXT:    ldr d1, [x0]3145; CHECK-SD-NEXT:    ldr d0, [x1]3146; CHECK-SD-NEXT:    ursra v0.8b, v1.8b, #13147; CHECK-SD-NEXT:    ret3148;3149; CHECK-GI-LABEL: ursra8b:3150; CHECK-GI:       // %bb.0:3151; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3152; CHECK-GI-NEXT:    ldr d1, [x0]3153; CHECK-GI-NEXT:    urshl v0.8b, v1.8b, v0.8b3154; CHECK-GI-NEXT:    ldr d1, [x1]3155; CHECK-GI-NEXT:    add v0.8b, v0.8b, v1.8b3156; CHECK-GI-NEXT:    ret3157  %tmp1 = load <8 x i8>, ptr %A3158  %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3159  %tmp4 = load <8 x i8>, ptr %B3160  %tmp5 = add <8 x i8> %tmp3, %tmp43161  ret <8 x i8> %tmp53162}3163 3164define <4 x i16> @ursra4h(ptr %A, ptr %B) nounwind {3165; CHECK-SD-LABEL: ursra4h:3166; CHECK-SD:       // %bb.0:3167; CHECK-SD-NEXT:    ldr d1, [x0]3168; CHECK-SD-NEXT:    ldr d0, [x1]3169; CHECK-SD-NEXT:    ursra v0.4h, v1.4h, #13170; CHECK-SD-NEXT:    ret3171;3172; CHECK-GI-LABEL: ursra4h:3173; CHECK-GI:       // %bb.0:3174; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3175; CHECK-GI-NEXT:    ldr d1, [x0]3176; CHECK-GI-NEXT:    urshl v0.4h, v1.4h, v0.4h3177; CHECK-GI-NEXT:    ldr d1, [x1]3178; CHECK-GI-NEXT:    add v0.4h, v0.4h, v1.4h3179; CHECK-GI-NEXT:    ret3180  %tmp1 = load <4 x i16>, ptr %A3181  %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)3182  %tmp4 = load <4 x i16>, ptr %B3183  %tmp5 = add <4 x i16> %tmp3, %tmp43184  ret <4 x i16> %tmp53185}3186 3187define <2 x i32> @ursra2s(ptr %A, ptr %B) nounwind {3188; CHECK-SD-LABEL: ursra2s:3189; CHECK-SD:       // %bb.0:3190; CHECK-SD-NEXT:    ldr d1, [x0]3191; CHECK-SD-NEXT:    ldr d0, [x1]3192; CHECK-SD-NEXT:    ursra v0.2s, v1.2s, #13193; CHECK-SD-NEXT:    ret3194;3195; CHECK-GI-LABEL: ursra2s:3196; CHECK-GI:       // %bb.0:3197; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3198; CHECK-GI-NEXT:    ldr d1, [x0]3199; CHECK-GI-NEXT:    urshl v0.2s, v1.2s, v0.2s3200; CHECK-GI-NEXT:    ldr d1, [x1]3201; CHECK-GI-NEXT:    add v0.2s, v0.2s, v1.2s3202; CHECK-GI-NEXT:    ret3203  %tmp1 = load <2 x i32>, ptr %A3204  %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)3205  %tmp4 = load <2 x i32>, ptr %B3206  %tmp5 = add <2 x i32> %tmp3, %tmp43207  ret <2 x i32> %tmp53208}3209 3210define <16 x i8> @ursra16b(ptr %A, ptr %B) nounwind {3211; CHECK-SD-LABEL: ursra16b:3212; CHECK-SD:       // %bb.0:3213; CHECK-SD-NEXT:    ldr q1, [x0]3214; CHECK-SD-NEXT:    ldr q0, [x1]3215; CHECK-SD-NEXT:    ursra v0.16b, v1.16b, #13216; CHECK-SD-NEXT:    ret3217;3218; CHECK-GI-LABEL: ursra16b:3219; CHECK-GI:       // %bb.0:3220; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3221; CHECK-GI-NEXT:    ldr q1, [x0]3222; CHECK-GI-NEXT:    urshl v0.16b, v1.16b, v0.16b3223; CHECK-GI-NEXT:    ldr q1, [x1]3224; CHECK-GI-NEXT:    add v0.16b, v0.16b, v1.16b3225; CHECK-GI-NEXT:    ret3226  %tmp1 = load <16 x i8>, ptr %A3227  %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3228  %tmp4 = load <16 x i8>, ptr %B3229  %tmp5 = add <16 x i8> %tmp3, %tmp43230   ret <16 x i8> %tmp53231}3232 3233define <8 x i16> @ursra8h(ptr %A, ptr %B) nounwind {3234; CHECK-SD-LABEL: ursra8h:3235; CHECK-SD:       // %bb.0:3236; CHECK-SD-NEXT:    ldr q1, [x0]3237; CHECK-SD-NEXT:    ldr q0, [x1]3238; CHECK-SD-NEXT:    ursra v0.8h, v1.8h, #13239; CHECK-SD-NEXT:    ret3240;3241; CHECK-GI-LABEL: ursra8h:3242; CHECK-GI:       // %bb.0:3243; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3244; CHECK-GI-NEXT:    ldr q1, [x0]3245; CHECK-GI-NEXT:    urshl v0.8h, v1.8h, v0.8h3246; CHECK-GI-NEXT:    ldr q1, [x1]3247; CHECK-GI-NEXT:    add v0.8h, v0.8h, v1.8h3248; CHECK-GI-NEXT:    ret3249  %tmp1 = load <8 x i16>, ptr %A3250  %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)3251  %tmp4 = load <8 x i16>, ptr %B3252  %tmp5 = add <8 x i16> %tmp3, %tmp43253   ret <8 x i16> %tmp53254}3255 3256define <4 x i32> @ursra4s(ptr %A, ptr %B) nounwind {3257; CHECK-SD-LABEL: ursra4s:3258; CHECK-SD:       // %bb.0:3259; CHECK-SD-NEXT:    ldr q1, [x0]3260; CHECK-SD-NEXT:    ldr q0, [x1]3261; CHECK-SD-NEXT:    ursra v0.4s, v1.4s, #13262; CHECK-SD-NEXT:    ret3263;3264; CHECK-GI-LABEL: ursra4s:3265; CHECK-GI:       // %bb.0:3266; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3267; CHECK-GI-NEXT:    ldr q1, [x0]3268; CHECK-GI-NEXT:    urshl v0.4s, v1.4s, v0.4s3269; CHECK-GI-NEXT:    ldr q1, [x1]3270; CHECK-GI-NEXT:    add v0.4s, v0.4s, v1.4s3271; CHECK-GI-NEXT:    ret3272  %tmp1 = load <4 x i32>, ptr %A3273  %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)3274  %tmp4 = load <4 x i32>, ptr %B3275  %tmp5 = add <4 x i32> %tmp3, %tmp43276   ret <4 x i32> %tmp53277}3278 3279define <2 x i64> @ursra2d(ptr %A, ptr %B) nounwind {3280; CHECK-SD-LABEL: ursra2d:3281; CHECK-SD:       // %bb.0:3282; CHECK-SD-NEXT:    ldr q1, [x0]3283; CHECK-SD-NEXT:    ldr q0, [x1]3284; CHECK-SD-NEXT:    ursra v0.2d, v1.2d, #13285; CHECK-SD-NEXT:    ret3286;3287; CHECK-GI-LABEL: ursra2d:3288; CHECK-GI:       // %bb.0:3289; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3290; CHECK-GI-NEXT:    ldr q1, [x0]3291; CHECK-GI-NEXT:    urshl v0.2d, v1.2d, v0.2d3292; CHECK-GI-NEXT:    ldr q1, [x1]3293; CHECK-GI-NEXT:    add v0.2d, v0.2d, v1.2d3294; CHECK-GI-NEXT:    ret3295  %tmp1 = load <2 x i64>, ptr %A3296  %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)3297  %tmp4 = load <2 x i64>, ptr %B3298  %tmp5 = add <2 x i64> %tmp3, %tmp43299   ret <2 x i64> %tmp53300}3301 3302define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {3303; CHECK-LABEL: ursra1d:3304; CHECK:       // %bb.0:3305; CHECK-NEXT:    ldr d1, [x0]3306; CHECK-NEXT:    ldr d0, [x1]3307; CHECK-NEXT:    ursra d0, d1, #13308; CHECK-NEXT:    ret3309  %tmp1 = load <1 x i64>, ptr %A3310  %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)3311  %tmp4 = load <1 x i64>, ptr %B3312  %tmp5 = add <1 x i64> %tmp3, %tmp43313  ret <1 x i64> %tmp53314}3315 3316define i64 @ursra_scalar(ptr %A, ptr %B) nounwind {3317; CHECK-LABEL: ursra_scalar:3318; CHECK:       // %bb.0:3319; CHECK-NEXT:    ldr d0, [x0]3320; CHECK-NEXT:    ldr d1, [x1]3321; CHECK-NEXT:    ursra d1, d0, #13322; CHECK-NEXT:    fmov x0, d13323; CHECK-NEXT:    ret3324  %tmp1 = load i64, ptr %A3325  %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)3326  %tmp4 = load i64, ptr %B3327  %tmp5 = add i64 %tmp3, %tmp43328  ret i64 %tmp53329}3330 3331define <8 x i8> @srsra8b(ptr %A, ptr %B) nounwind {3332; CHECK-SD-LABEL: srsra8b:3333; CHECK-SD:       // %bb.0:3334; CHECK-SD-NEXT:    ldr d1, [x0]3335; CHECK-SD-NEXT:    ldr d0, [x1]3336; CHECK-SD-NEXT:    srsra v0.8b, v1.8b, #13337; CHECK-SD-NEXT:    ret3338;3339; CHECK-GI-LABEL: srsra8b:3340; CHECK-GI:       // %bb.0:3341; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3342; CHECK-GI-NEXT:    ldr d1, [x0]3343; CHECK-GI-NEXT:    srshl v0.8b, v1.8b, v0.8b3344; CHECK-GI-NEXT:    ldr d1, [x1]3345; CHECK-GI-NEXT:    add v0.8b, v0.8b, v1.8b3346; CHECK-GI-NEXT:    ret3347  %tmp1 = load <8 x i8>, ptr %A3348  %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3349  %tmp4 = load <8 x i8>, ptr %B3350  %tmp5 = add <8 x i8> %tmp3, %tmp43351  ret <8 x i8> %tmp53352}3353 3354define <4 x i16> @srsra4h(ptr %A, ptr %B) nounwind {3355; CHECK-SD-LABEL: srsra4h:3356; CHECK-SD:       // %bb.0:3357; CHECK-SD-NEXT:    ldr d1, [x0]3358; CHECK-SD-NEXT:    ldr d0, [x1]3359; CHECK-SD-NEXT:    srsra v0.4h, v1.4h, #13360; CHECK-SD-NEXT:    ret3361;3362; CHECK-GI-LABEL: srsra4h:3363; CHECK-GI:       // %bb.0:3364; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3365; CHECK-GI-NEXT:    ldr d1, [x0]3366; CHECK-GI-NEXT:    srshl v0.4h, v1.4h, v0.4h3367; CHECK-GI-NEXT:    ldr d1, [x1]3368; CHECK-GI-NEXT:    add v0.4h, v0.4h, v1.4h3369; CHECK-GI-NEXT:    ret3370  %tmp1 = load <4 x i16>, ptr %A3371  %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)3372  %tmp4 = load <4 x i16>, ptr %B3373  %tmp5 = add <4 x i16> %tmp3, %tmp43374  ret <4 x i16> %tmp53375}3376 3377define <2 x i32> @srsra2s(ptr %A, ptr %B) nounwind {3378; CHECK-SD-LABEL: srsra2s:3379; CHECK-SD:       // %bb.0:3380; CHECK-SD-NEXT:    ldr d1, [x0]3381; CHECK-SD-NEXT:    ldr d0, [x1]3382; CHECK-SD-NEXT:    srsra v0.2s, v1.2s, #13383; CHECK-SD-NEXT:    ret3384;3385; CHECK-GI-LABEL: srsra2s:3386; CHECK-GI:       // %bb.0:3387; CHECK-GI-NEXT:    movi d0, #0xffffffffffffffff3388; CHECK-GI-NEXT:    ldr d1, [x0]3389; CHECK-GI-NEXT:    srshl v0.2s, v1.2s, v0.2s3390; CHECK-GI-NEXT:    ldr d1, [x1]3391; CHECK-GI-NEXT:    add v0.2s, v0.2s, v1.2s3392; CHECK-GI-NEXT:    ret3393  %tmp1 = load <2 x i32>, ptr %A3394  %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)3395  %tmp4 = load <2 x i32>, ptr %B3396  %tmp5 = add <2 x i32> %tmp3, %tmp43397  ret <2 x i32> %tmp53398}3399 3400define <16 x i8> @srsra16b(ptr %A, ptr %B) nounwind {3401; CHECK-SD-LABEL: srsra16b:3402; CHECK-SD:       // %bb.0:3403; CHECK-SD-NEXT:    ldr q1, [x0]3404; CHECK-SD-NEXT:    ldr q0, [x1]3405; CHECK-SD-NEXT:    srsra v0.16b, v1.16b, #13406; CHECK-SD-NEXT:    ret3407;3408; CHECK-GI-LABEL: srsra16b:3409; CHECK-GI:       // %bb.0:3410; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3411; CHECK-GI-NEXT:    ldr q1, [x0]3412; CHECK-GI-NEXT:    srshl v0.16b, v1.16b, v0.16b3413; CHECK-GI-NEXT:    ldr q1, [x1]3414; CHECK-GI-NEXT:    add v0.16b, v0.16b, v1.16b3415; CHECK-GI-NEXT:    ret3416  %tmp1 = load <16 x i8>, ptr %A3417  %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3418  %tmp4 = load <16 x i8>, ptr %B3419  %tmp5 = add <16 x i8> %tmp3, %tmp43420   ret <16 x i8> %tmp53421}3422 3423define <8 x i16> @srsra8h(ptr %A, ptr %B) nounwind {3424; CHECK-SD-LABEL: srsra8h:3425; CHECK-SD:       // %bb.0:3426; CHECK-SD-NEXT:    ldr q1, [x0]3427; CHECK-SD-NEXT:    ldr q0, [x1]3428; CHECK-SD-NEXT:    srsra v0.8h, v1.8h, #13429; CHECK-SD-NEXT:    ret3430;3431; CHECK-GI-LABEL: srsra8h:3432; CHECK-GI:       // %bb.0:3433; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3434; CHECK-GI-NEXT:    ldr q1, [x0]3435; CHECK-GI-NEXT:    srshl v0.8h, v1.8h, v0.8h3436; CHECK-GI-NEXT:    ldr q1, [x1]3437; CHECK-GI-NEXT:    add v0.8h, v0.8h, v1.8h3438; CHECK-GI-NEXT:    ret3439  %tmp1 = load <8 x i16>, ptr %A3440  %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)3441  %tmp4 = load <8 x i16>, ptr %B3442  %tmp5 = add <8 x i16> %tmp3, %tmp43443   ret <8 x i16> %tmp53444}3445 3446define <4 x i32> @srsra4s(ptr %A, ptr %B) nounwind {3447; CHECK-SD-LABEL: srsra4s:3448; CHECK-SD:       // %bb.0:3449; CHECK-SD-NEXT:    ldr q1, [x0]3450; CHECK-SD-NEXT:    ldr q0, [x1]3451; CHECK-SD-NEXT:    srsra v0.4s, v1.4s, #13452; CHECK-SD-NEXT:    ret3453;3454; CHECK-GI-LABEL: srsra4s:3455; CHECK-GI:       // %bb.0:3456; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3457; CHECK-GI-NEXT:    ldr q1, [x0]3458; CHECK-GI-NEXT:    srshl v0.4s, v1.4s, v0.4s3459; CHECK-GI-NEXT:    ldr q1, [x1]3460; CHECK-GI-NEXT:    add v0.4s, v0.4s, v1.4s3461; CHECK-GI-NEXT:    ret3462  %tmp1 = load <4 x i32>, ptr %A3463  %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)3464  %tmp4 = load <4 x i32>, ptr %B3465  %tmp5 = add <4 x i32> %tmp3, %tmp43466   ret <4 x i32> %tmp53467}3468 3469define <2 x i64> @srsra2d(ptr %A, ptr %B) nounwind {3470; CHECK-SD-LABEL: srsra2d:3471; CHECK-SD:       // %bb.0:3472; CHECK-SD-NEXT:    ldr q1, [x0]3473; CHECK-SD-NEXT:    ldr q0, [x1]3474; CHECK-SD-NEXT:    srsra v0.2d, v1.2d, #13475; CHECK-SD-NEXT:    ret3476;3477; CHECK-GI-LABEL: srsra2d:3478; CHECK-GI:       // %bb.0:3479; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff3480; CHECK-GI-NEXT:    ldr q1, [x0]3481; CHECK-GI-NEXT:    srshl v0.2d, v1.2d, v0.2d3482; CHECK-GI-NEXT:    ldr q1, [x1]3483; CHECK-GI-NEXT:    add v0.2d, v0.2d, v1.2d3484; CHECK-GI-NEXT:    ret3485  %tmp1 = load <2 x i64>, ptr %A3486  %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)3487  %tmp4 = load <2 x i64>, ptr %B3488  %tmp5 = add <2 x i64> %tmp3, %tmp43489   ret <2 x i64> %tmp53490}3491 3492define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {3493; CHECK-LABEL: srsra1d:3494; CHECK:       // %bb.0:3495; CHECK-NEXT:    ldr d1, [x0]3496; CHECK-NEXT:    ldr d0, [x1]3497; CHECK-NEXT:    srsra d0, d1, #13498; CHECK-NEXT:    ret3499  %tmp1 = load <1 x i64>, ptr %A3500  %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)3501  %tmp4 = load <1 x i64>, ptr %B3502  %tmp5 = add <1 x i64> %tmp3, %tmp43503  ret <1 x i64> %tmp53504}3505 3506define i64 @srsra_scalar(ptr %A, ptr %B) nounwind {3507; CHECK-LABEL: srsra_scalar:3508; CHECK:       // %bb.0:3509; CHECK-NEXT:    ldr d0, [x0]3510; CHECK-NEXT:    ldr d1, [x1]3511; CHECK-NEXT:    srsra d1, d0, #13512; CHECK-NEXT:    fmov x0, d13513; CHECK-NEXT:    ret3514  %tmp1 = load i64, ptr %A3515  %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)3516  %tmp4 = load i64, ptr %B3517  %tmp5 = add i64 %tmp3, %tmp43518  ret i64 %tmp53519}3520 3521define <8 x i8> @usra8b(ptr %A, ptr %B) nounwind {3522; CHECK-LABEL: usra8b:3523; CHECK:       // %bb.0:3524; CHECK-NEXT:    ldr d1, [x0]3525; CHECK-NEXT:    ldr d0, [x1]3526; CHECK-NEXT:    usra v0.8b, v1.8b, #13527; CHECK-NEXT:    ret3528  %tmp1 = load <8 x i8>, ptr %A3529  %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3530  %tmp4 = load <8 x i8>, ptr %B3531  %tmp5 = add <8 x i8> %tmp3, %tmp43532  ret <8 x i8> %tmp53533}3534 3535define <4 x i16> @usra4h(ptr %A, ptr %B) nounwind {3536; CHECK-LABEL: usra4h:3537; CHECK:       // %bb.0:3538; CHECK-NEXT:    ldr d1, [x0]3539; CHECK-NEXT:    ldr d0, [x1]3540; CHECK-NEXT:    usra v0.4h, v1.4h, #13541; CHECK-NEXT:    ret3542  %tmp1 = load <4 x i16>, ptr %A3543  %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>3544  %tmp4 = load <4 x i16>, ptr %B3545  %tmp5 = add <4 x i16> %tmp3, %tmp43546  ret <4 x i16> %tmp53547}3548 3549define <2 x i32> @usra2s(ptr %A, ptr %B) nounwind {3550; CHECK-LABEL: usra2s:3551; CHECK:       // %bb.0:3552; CHECK-NEXT:    ldr d1, [x0]3553; CHECK-NEXT:    ldr d0, [x1]3554; CHECK-NEXT:    usra v0.2s, v1.2s, #13555; CHECK-NEXT:    ret3556  %tmp1 = load <2 x i32>, ptr %A3557  %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>3558  %tmp4 = load <2 x i32>, ptr %B3559  %tmp5 = add <2 x i32> %tmp3, %tmp43560  ret <2 x i32> %tmp53561}3562 3563define <16 x i8> @usra16b(ptr %A, ptr %B) nounwind {3564; CHECK-LABEL: usra16b:3565; CHECK:       // %bb.0:3566; CHECK-NEXT:    ldr q1, [x0]3567; CHECK-NEXT:    ldr q0, [x1]3568; CHECK-NEXT:    usra v0.16b, v1.16b, #13569; CHECK-NEXT:    ret3570  %tmp1 = load <16 x i8>, ptr %A3571  %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3572  %tmp4 = load <16 x i8>, ptr %B3573  %tmp5 = add <16 x i8> %tmp3, %tmp43574   ret <16 x i8> %tmp53575}3576 3577define <8 x i16> @usra8h(ptr %A, ptr %B) nounwind {3578; CHECK-LABEL: usra8h:3579; CHECK:       // %bb.0:3580; CHECK-NEXT:    ldr q1, [x0]3581; CHECK-NEXT:    ldr q0, [x1]3582; CHECK-NEXT:    usra v0.8h, v1.8h, #13583; CHECK-NEXT:    ret3584  %tmp1 = load <8 x i16>, ptr %A3585  %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3586  %tmp4 = load <8 x i16>, ptr %B3587  %tmp5 = add <8 x i16> %tmp3, %tmp43588   ret <8 x i16> %tmp53589}3590 3591define <4 x i32> @usra4s(ptr %A, ptr %B) nounwind {3592; CHECK-LABEL: usra4s:3593; CHECK:       // %bb.0:3594; CHECK-NEXT:    ldr q1, [x0]3595; CHECK-NEXT:    ldr q0, [x1]3596; CHECK-NEXT:    usra v0.4s, v1.4s, #13597; CHECK-NEXT:    ret3598  %tmp1 = load <4 x i32>, ptr %A3599  %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3600  %tmp4 = load <4 x i32>, ptr %B3601  %tmp5 = add <4 x i32> %tmp3, %tmp43602   ret <4 x i32> %tmp53603}3604 3605define <2 x i64> @usra2d(ptr %A, ptr %B) nounwind {3606; CHECK-LABEL: usra2d:3607; CHECK:       // %bb.0:3608; CHECK-NEXT:    ldr q1, [x0]3609; CHECK-NEXT:    ldr q0, [x1]3610; CHECK-NEXT:    usra v0.2d, v1.2d, #13611; CHECK-NEXT:    ret3612  %tmp1 = load <2 x i64>, ptr %A3613  %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>3614  %tmp4 = load <2 x i64>, ptr %B3615  %tmp5 = add <2 x i64> %tmp3, %tmp43616   ret <2 x i64> %tmp53617}3618 3619define <1 x i64> @usra1d(ptr %A, ptr %B) nounwind {3620; CHECK-SD-LABEL: usra1d:3621; CHECK-SD:       // %bb.0:3622; CHECK-SD-NEXT:    ldr d1, [x0]3623; CHECK-SD-NEXT:    ldr d0, [x1]3624; CHECK-SD-NEXT:    usra d0, d1, #13625; CHECK-SD-NEXT:    ret3626;3627; CHECK-GI-LABEL: usra1d:3628; CHECK-GI:       // %bb.0:3629; CHECK-GI-NEXT:    ldr x8, [x0]3630; CHECK-GI-NEXT:    ldr x9, [x1]3631; CHECK-GI-NEXT:    add x8, x9, x8, lsr #13632; CHECK-GI-NEXT:    fmov d0, x83633; CHECK-GI-NEXT:    ret3634  %tmp1 = load <1 x i64>, ptr %A3635  %tmp3 = lshr <1 x i64> %tmp1, <i64 1>3636  %tmp4 = load <1 x i64>, ptr %B3637  %tmp5 = add <1 x i64> %tmp3, %tmp43638   ret <1 x i64> %tmp53639}3640 3641define <8 x i8> @ssra8b(ptr %A, ptr %B) nounwind {3642; CHECK-LABEL: ssra8b:3643; CHECK:       // %bb.0:3644; CHECK-NEXT:    ldr d1, [x0]3645; CHECK-NEXT:    ldr d0, [x1]3646; CHECK-NEXT:    ssra v0.8b, v1.8b, #13647; CHECK-NEXT:    ret3648  %tmp1 = load <8 x i8>, ptr %A3649  %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3650  %tmp4 = load <8 x i8>, ptr %B3651  %tmp5 = add <8 x i8> %tmp3, %tmp43652  ret <8 x i8> %tmp53653}3654 3655define <4 x i16> @ssra4h(ptr %A, ptr %B) nounwind {3656; CHECK-LABEL: ssra4h:3657; CHECK:       // %bb.0:3658; CHECK-NEXT:    ldr d1, [x0]3659; CHECK-NEXT:    ldr d0, [x1]3660; CHECK-NEXT:    ssra v0.4h, v1.4h, #13661; CHECK-NEXT:    ret3662  %tmp1 = load <4 x i16>, ptr %A3663  %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>3664  %tmp4 = load <4 x i16>, ptr %B3665  %tmp5 = add <4 x i16> %tmp3, %tmp43666  ret <4 x i16> %tmp53667}3668 3669define <2 x i32> @ssra2s(ptr %A, ptr %B) nounwind {3670; CHECK-LABEL: ssra2s:3671; CHECK:       // %bb.0:3672; CHECK-NEXT:    ldr d1, [x0]3673; CHECK-NEXT:    ldr d0, [x1]3674; CHECK-NEXT:    ssra v0.2s, v1.2s, #13675; CHECK-NEXT:    ret3676  %tmp1 = load <2 x i32>, ptr %A3677  %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>3678  %tmp4 = load <2 x i32>, ptr %B3679  %tmp5 = add <2 x i32> %tmp3, %tmp43680  ret <2 x i32> %tmp53681}3682 3683define <16 x i8> @ssra16b(ptr %A, ptr %B) nounwind {3684; CHECK-LABEL: ssra16b:3685; CHECK:       // %bb.0:3686; CHECK-NEXT:    ldr q1, [x0]3687; CHECK-NEXT:    ldr q0, [x1]3688; CHECK-NEXT:    ssra v0.16b, v1.16b, #13689; CHECK-NEXT:    ret3690  %tmp1 = load <16 x i8>, ptr %A3691  %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3692  %tmp4 = load <16 x i8>, ptr %B3693  %tmp5 = add <16 x i8> %tmp3, %tmp43694   ret <16 x i8> %tmp53695}3696 3697define <8 x i16> @ssra8h(ptr %A, ptr %B) nounwind {3698; CHECK-LABEL: ssra8h:3699; CHECK:       // %bb.0:3700; CHECK-NEXT:    ldr q1, [x0]3701; CHECK-NEXT:    ldr q0, [x1]3702; CHECK-NEXT:    ssra v0.8h, v1.8h, #13703; CHECK-NEXT:    ret3704  %tmp1 = load <8 x i16>, ptr %A3705  %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3706  %tmp4 = load <8 x i16>, ptr %B3707  %tmp5 = add <8 x i16> %tmp3, %tmp43708   ret <8 x i16> %tmp53709}3710 3711define <4 x i32> @ssra4s(ptr %A, ptr %B) nounwind {3712; CHECK-LABEL: ssra4s:3713; CHECK:       // %bb.0:3714; CHECK-NEXT:    ldr q1, [x0]3715; CHECK-NEXT:    ldr q0, [x1]3716; CHECK-NEXT:    ssra v0.4s, v1.4s, #13717; CHECK-NEXT:    ret3718  %tmp1 = load <4 x i32>, ptr %A3719  %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3720  %tmp4 = load <4 x i32>, ptr %B3721  %tmp5 = add <4 x i32> %tmp3, %tmp43722   ret <4 x i32> %tmp53723}3724 3725define <2 x i64> @ssra2d(ptr %A, ptr %B) nounwind {3726; CHECK-LABEL: ssra2d:3727; CHECK:       // %bb.0:3728; CHECK-NEXT:    ldr q1, [x0]3729; CHECK-NEXT:    ldr q0, [x1]3730; CHECK-NEXT:    ssra v0.2d, v1.2d, #13731; CHECK-NEXT:    ret3732  %tmp1 = load <2 x i64>, ptr %A3733  %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>3734  %tmp4 = load <2 x i64>, ptr %B3735  %tmp5 = add <2 x i64> %tmp3, %tmp43736   ret <2 x i64> %tmp53737}3738 3739define <8 x i8> @shr_orr8b(ptr %A, ptr %B) nounwind {3740; CHECK-LABEL: shr_orr8b:3741; CHECK:       // %bb.0:3742; CHECK-NEXT:    ldr d0, [x0]3743; CHECK-NEXT:    ldr d1, [x1]3744; CHECK-NEXT:    ushr v0.8b, v0.8b, #13745; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b3746; CHECK-NEXT:    ret3747  %tmp1 = load <8 x i8>, ptr %A3748  %tmp4 = load <8 x i8>, ptr %B3749  %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3750  %tmp5 = or <8 x i8> %tmp3, %tmp43751  ret <8 x i8> %tmp53752}3753 3754define <4 x i16> @shr_orr4h(ptr %A, ptr %B) nounwind {3755; CHECK-LABEL: shr_orr4h:3756; CHECK:       // %bb.0:3757; CHECK-NEXT:    ldr d0, [x0]3758; CHECK-NEXT:    ldr d1, [x1]3759; CHECK-NEXT:    ushr v0.4h, v0.4h, #13760; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b3761; CHECK-NEXT:    ret3762  %tmp1 = load <4 x i16>, ptr %A3763  %tmp4 = load <4 x i16>, ptr %B3764  %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>3765  %tmp5 = or <4 x i16> %tmp3, %tmp43766  ret <4 x i16> %tmp53767}3768 3769define <2 x i32> @shr_orr2s(ptr %A, ptr %B) nounwind {3770; CHECK-LABEL: shr_orr2s:3771; CHECK:       // %bb.0:3772; CHECK-NEXT:    ldr d0, [x0]3773; CHECK-NEXT:    ldr d1, [x1]3774; CHECK-NEXT:    ushr v0.2s, v0.2s, #13775; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b3776; CHECK-NEXT:    ret3777  %tmp1 = load <2 x i32>, ptr %A3778  %tmp4 = load <2 x i32>, ptr %B3779  %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>3780  %tmp5 = or <2 x i32> %tmp3, %tmp43781  ret <2 x i32> %tmp53782}3783 3784define <16 x i8> @shr_orr16b(ptr %A, ptr %B) nounwind {3785; CHECK-LABEL: shr_orr16b:3786; CHECK:       // %bb.0:3787; CHECK-NEXT:    ldr q0, [x0]3788; CHECK-NEXT:    ldr q1, [x1]3789; CHECK-NEXT:    ushr v0.16b, v0.16b, #13790; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b3791; CHECK-NEXT:    ret3792  %tmp1 = load <16 x i8>, ptr %A3793  %tmp4 = load <16 x i8>, ptr %B3794  %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3795  %tmp5 = or <16 x i8> %tmp3, %tmp43796   ret <16 x i8> %tmp53797}3798 3799define <8 x i16> @shr_orr8h(ptr %A, ptr %B) nounwind {3800; CHECK-LABEL: shr_orr8h:3801; CHECK:       // %bb.0:3802; CHECK-NEXT:    ldr q0, [x0]3803; CHECK-NEXT:    ldr q1, [x1]3804; CHECK-NEXT:    ushr v0.8h, v0.8h, #13805; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b3806; CHECK-NEXT:    ret3807  %tmp1 = load <8 x i16>, ptr %A3808  %tmp4 = load <8 x i16>, ptr %B3809  %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3810  %tmp5 = or <8 x i16> %tmp3, %tmp43811   ret <8 x i16> %tmp53812}3813 3814define <4 x i32> @shr_orr4s(ptr %A, ptr %B) nounwind {3815; CHECK-LABEL: shr_orr4s:3816; CHECK:       // %bb.0:3817; CHECK-NEXT:    ldr q0, [x0]3818; CHECK-NEXT:    ldr q1, [x1]3819; CHECK-NEXT:    ushr v0.4s, v0.4s, #13820; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b3821; CHECK-NEXT:    ret3822  %tmp1 = load <4 x i32>, ptr %A3823  %tmp4 = load <4 x i32>, ptr %B3824  %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3825  %tmp5 = or <4 x i32> %tmp3, %tmp43826   ret <4 x i32> %tmp53827}3828 3829define <2 x i64> @shr_orr2d(ptr %A, ptr %B) nounwind {3830; CHECK-LABEL: shr_orr2d:3831; CHECK:       // %bb.0:3832; CHECK-NEXT:    ldr q0, [x0]3833; CHECK-NEXT:    ldr q1, [x1]3834; CHECK-NEXT:    ushr v0.2d, v0.2d, #13835; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b3836; CHECK-NEXT:    ret3837  %tmp1 = load <2 x i64>, ptr %A3838  %tmp4 = load <2 x i64>, ptr %B3839  %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>3840  %tmp5 = or <2 x i64> %tmp3, %tmp43841   ret <2 x i64> %tmp53842}3843 3844define <8 x i8> @shl_orr8b(ptr %A, ptr %B) nounwind {3845; CHECK-SD-LABEL: shl_orr8b:3846; CHECK-SD:       // %bb.0:3847; CHECK-SD-NEXT:    ldr d0, [x0]3848; CHECK-SD-NEXT:    ldr d1, [x1]3849; CHECK-SD-NEXT:    add v0.8b, v0.8b, v0.8b3850; CHECK-SD-NEXT:    orr v0.8b, v0.8b, v1.8b3851; CHECK-SD-NEXT:    ret3852;3853; CHECK-GI-LABEL: shl_orr8b:3854; CHECK-GI:       // %bb.0:3855; CHECK-GI-NEXT:    ldr d0, [x0]3856; CHECK-GI-NEXT:    ldr d1, [x1]3857; CHECK-GI-NEXT:    shl v0.8b, v0.8b, #13858; CHECK-GI-NEXT:    orr v0.8b, v0.8b, v1.8b3859; CHECK-GI-NEXT:    ret3860  %tmp1 = load <8 x i8>, ptr %A3861  %tmp4 = load <8 x i8>, ptr %B3862  %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3863  %tmp5 = or <8 x i8> %tmp3, %tmp43864  ret <8 x i8> %tmp53865}3866 3867define <4 x i16> @shl_orr4h(ptr %A, ptr %B) nounwind {3868; CHECK-SD-LABEL: shl_orr4h:3869; CHECK-SD:       // %bb.0:3870; CHECK-SD-NEXT:    ldr d0, [x0]3871; CHECK-SD-NEXT:    ldr d1, [x1]3872; CHECK-SD-NEXT:    add v0.4h, v0.4h, v0.4h3873; CHECK-SD-NEXT:    orr v0.8b, v0.8b, v1.8b3874; CHECK-SD-NEXT:    ret3875;3876; CHECK-GI-LABEL: shl_orr4h:3877; CHECK-GI:       // %bb.0:3878; CHECK-GI-NEXT:    ldr d0, [x0]3879; CHECK-GI-NEXT:    ldr d1, [x1]3880; CHECK-GI-NEXT:    shl v0.4h, v0.4h, #13881; CHECK-GI-NEXT:    orr v0.8b, v0.8b, v1.8b3882; CHECK-GI-NEXT:    ret3883  %tmp1 = load <4 x i16>, ptr %A3884  %tmp4 = load <4 x i16>, ptr %B3885  %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>3886  %tmp5 = or <4 x i16> %tmp3, %tmp43887  ret <4 x i16> %tmp53888}3889 3890define <2 x i32> @shl_orr2s(ptr %A, ptr %B) nounwind {3891; CHECK-SD-LABEL: shl_orr2s:3892; CHECK-SD:       // %bb.0:3893; CHECK-SD-NEXT:    ldr d0, [x0]3894; CHECK-SD-NEXT:    ldr d1, [x1]3895; CHECK-SD-NEXT:    add v0.2s, v0.2s, v0.2s3896; CHECK-SD-NEXT:    orr v0.8b, v0.8b, v1.8b3897; CHECK-SD-NEXT:    ret3898;3899; CHECK-GI-LABEL: shl_orr2s:3900; CHECK-GI:       // %bb.0:3901; CHECK-GI-NEXT:    ldr d0, [x0]3902; CHECK-GI-NEXT:    ldr d1, [x1]3903; CHECK-GI-NEXT:    shl v0.2s, v0.2s, #13904; CHECK-GI-NEXT:    orr v0.8b, v0.8b, v1.8b3905; CHECK-GI-NEXT:    ret3906  %tmp1 = load <2 x i32>, ptr %A3907  %tmp4 = load <2 x i32>, ptr %B3908  %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>3909  %tmp5 = or <2 x i32> %tmp3, %tmp43910  ret <2 x i32> %tmp53911}3912 3913define <16 x i8> @shl_orr16b(ptr %A, ptr %B) nounwind {3914; CHECK-SD-LABEL: shl_orr16b:3915; CHECK-SD:       // %bb.0:3916; CHECK-SD-NEXT:    ldr q0, [x0]3917; CHECK-SD-NEXT:    ldr q1, [x1]3918; CHECK-SD-NEXT:    add v0.16b, v0.16b, v0.16b3919; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v1.16b3920; CHECK-SD-NEXT:    ret3921;3922; CHECK-GI-LABEL: shl_orr16b:3923; CHECK-GI:       // %bb.0:3924; CHECK-GI-NEXT:    ldr q0, [x0]3925; CHECK-GI-NEXT:    ldr q1, [x1]3926; CHECK-GI-NEXT:    shl v0.16b, v0.16b, #13927; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b3928; CHECK-GI-NEXT:    ret3929  %tmp1 = load <16 x i8>, ptr %A3930  %tmp4 = load <16 x i8>, ptr %B3931  %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>3932  %tmp5 = or <16 x i8> %tmp3, %tmp43933   ret <16 x i8> %tmp53934}3935 3936define <8 x i16> @shl_orr8h(ptr %A, ptr %B) nounwind {3937; CHECK-SD-LABEL: shl_orr8h:3938; CHECK-SD:       // %bb.0:3939; CHECK-SD-NEXT:    ldr q0, [x0]3940; CHECK-SD-NEXT:    ldr q1, [x1]3941; CHECK-SD-NEXT:    add v0.8h, v0.8h, v0.8h3942; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v1.16b3943; CHECK-SD-NEXT:    ret3944;3945; CHECK-GI-LABEL: shl_orr8h:3946; CHECK-GI:       // %bb.0:3947; CHECK-GI-NEXT:    ldr q0, [x0]3948; CHECK-GI-NEXT:    ldr q1, [x1]3949; CHECK-GI-NEXT:    shl v0.8h, v0.8h, #13950; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b3951; CHECK-GI-NEXT:    ret3952  %tmp1 = load <8 x i16>, ptr %A3953  %tmp4 = load <8 x i16>, ptr %B3954  %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3955  %tmp5 = or <8 x i16> %tmp3, %tmp43956   ret <8 x i16> %tmp53957}3958 3959define <4 x i32> @shl_orr4s(ptr %A, ptr %B) nounwind {3960; CHECK-SD-LABEL: shl_orr4s:3961; CHECK-SD:       // %bb.0:3962; CHECK-SD-NEXT:    ldr q0, [x0]3963; CHECK-SD-NEXT:    ldr q1, [x1]3964; CHECK-SD-NEXT:    add v0.4s, v0.4s, v0.4s3965; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v1.16b3966; CHECK-SD-NEXT:    ret3967;3968; CHECK-GI-LABEL: shl_orr4s:3969; CHECK-GI:       // %bb.0:3970; CHECK-GI-NEXT:    ldr q0, [x0]3971; CHECK-GI-NEXT:    ldr q1, [x1]3972; CHECK-GI-NEXT:    shl v0.4s, v0.4s, #13973; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b3974; CHECK-GI-NEXT:    ret3975  %tmp1 = load <4 x i32>, ptr %A3976  %tmp4 = load <4 x i32>, ptr %B3977  %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3978  %tmp5 = or <4 x i32> %tmp3, %tmp43979   ret <4 x i32> %tmp53980}3981 3982define <2 x i64> @shl_orr2d(ptr %A, ptr %B) nounwind {3983; CHECK-SD-LABEL: shl_orr2d:3984; CHECK-SD:       // %bb.0:3985; CHECK-SD-NEXT:    ldr q0, [x0]3986; CHECK-SD-NEXT:    ldr q1, [x1]3987; CHECK-SD-NEXT:    add v0.2d, v0.2d, v0.2d3988; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v1.16b3989; CHECK-SD-NEXT:    ret3990;3991; CHECK-GI-LABEL: shl_orr2d:3992; CHECK-GI:       // %bb.0:3993; CHECK-GI-NEXT:    ldr q0, [x0]3994; CHECK-GI-NEXT:    ldr q1, [x1]3995; CHECK-GI-NEXT:    shl v0.2d, v0.2d, #13996; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b3997; CHECK-GI-NEXT:    ret3998  %tmp1 = load <2 x i64>, ptr %A3999  %tmp4 = load <2 x i64>, ptr %B4000  %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>4001  %tmp5 = or <2 x i64> %tmp3, %tmp44002   ret <2 x i64> %tmp54003}4004 4005define <8 x i16> @shll(<8 x i8> %in) {4006; CHECK-SD-LABEL: shll:4007; CHECK-SD:       // %bb.0:4008; CHECK-SD-NEXT:    shll v0.8h, v0.8b, #84009; CHECK-SD-NEXT:    ret4010;4011; CHECK-GI-LABEL: shll:4012; CHECK-GI:       // %bb.0:4013; CHECK-GI-NEXT:    ushll v0.8h, v0.8b, #04014; CHECK-GI-NEXT:    shl v0.8h, v0.8h, #84015; CHECK-GI-NEXT:    ret4016  %ext = zext <8 x i8> %in to <8 x i16>4017  %res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>4018  ret <8 x i16> %res4019}4020 4021define <4 x i32> @shll_high(<8 x i16> %in) {4022; CHECK-SD-LABEL: shll_high:4023; CHECK-SD:       // %bb.0:4024; CHECK-SD-NEXT:    shll2 v0.4s, v0.8h, #164025; CHECK-SD-NEXT:    ret4026;4027; CHECK-GI-LABEL: shll_high:4028; CHECK-GI:       // %bb.0:4029; CHECK-GI-NEXT:    ushll2 v0.4s, v0.8h, #04030; CHECK-GI-NEXT:    shl v0.4s, v0.4s, #164031; CHECK-GI-NEXT:    ret4032  %extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>4033  %ext = zext <4 x i16> %extract to <4 x i32>4034  %res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>4035  ret <4 x i32> %res4036}4037 4038define <8 x i8> @sli8b(ptr %A, ptr %B) nounwind {4039; CHECK-LABEL: sli8b:4040; CHECK:       // %bb.0:4041; CHECK-NEXT:    ldr d0, [x0]4042; CHECK-NEXT:    ldr d1, [x1]4043; CHECK-NEXT:    sli v0.8b, v1.8b, #14044; CHECK-NEXT:    ret4045  %tmp1 = load <8 x i8>, ptr %A4046  %tmp2 = load <8 x i8>, ptr %B4047  %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)4048  ret <8 x i8> %tmp34049}4050 4051define <4 x i16> @sli4h(ptr %A, ptr %B) nounwind {4052; CHECK-LABEL: sli4h:4053; CHECK:       // %bb.0:4054; CHECK-NEXT:    ldr d0, [x0]4055; CHECK-NEXT:    ldr d1, [x1]4056; CHECK-NEXT:    sli v0.4h, v1.4h, #14057; CHECK-NEXT:    ret4058  %tmp1 = load <4 x i16>, ptr %A4059  %tmp2 = load <4 x i16>, ptr %B4060  %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)4061  ret <4 x i16> %tmp34062}4063 4064define <2 x i32> @sli2s(ptr %A, ptr %B) nounwind {4065; CHECK-LABEL: sli2s:4066; CHECK:       // %bb.0:4067; CHECK-NEXT:    ldr d0, [x0]4068; CHECK-NEXT:    ldr d1, [x1]4069; CHECK-NEXT:    sli v0.2s, v1.2s, #14070; CHECK-NEXT:    ret4071  %tmp1 = load <2 x i32>, ptr %A4072  %tmp2 = load <2 x i32>, ptr %B4073  %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)4074  ret <2 x i32> %tmp34075}4076 4077define <1 x i64> @sli1d(ptr %A, ptr %B) nounwind {4078; CHECK-LABEL: sli1d:4079; CHECK:       // %bb.0:4080; CHECK-NEXT:    ldr d0, [x0]4081; CHECK-NEXT:    ldr d1, [x1]4082; CHECK-NEXT:    sli d0, d1, #14083; CHECK-NEXT:    ret4084  %tmp1 = load <1 x i64>, ptr %A4085  %tmp2 = load <1 x i64>, ptr %B4086  %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)4087  ret <1 x i64> %tmp34088}4089 4090; Ensure we can select scalar SLI with a zero shift (see issue #139879).4091define <1 x i64> @sli1d_imm0(<1 x i64> %a, <1 x i64> %b) {4092; CHECK-LABEL: sli1d_imm0:4093; CHECK:       // %bb.0:4094; CHECK-NEXT:    sli d0, d1, #04095; CHECK-NEXT:    ret4096  %r = call <1 x i64> @llvm.aarch64.neon.vsli(<1 x i64> %a, <1 x i64> %b, i32 0)4097  ret <1 x i64> %r4098}4099 4100define <16 x i8> @sli16b(ptr %A, ptr %B) nounwind {4101; CHECK-LABEL: sli16b:4102; CHECK:       // %bb.0:4103; CHECK-NEXT:    ldr q0, [x0]4104; CHECK-NEXT:    ldr q1, [x1]4105; CHECK-NEXT:    sli v0.16b, v1.16b, #14106; CHECK-NEXT:    ret4107  %tmp1 = load <16 x i8>, ptr %A4108  %tmp2 = load <16 x i8>, ptr %B4109  %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)4110  ret <16 x i8> %tmp34111}4112 4113define <8 x i16> @sli8h(ptr %A, ptr %B) nounwind {4114; CHECK-LABEL: sli8h:4115; CHECK:       // %bb.0:4116; CHECK-NEXT:    ldr q0, [x0]4117; CHECK-NEXT:    ldr q1, [x1]4118; CHECK-NEXT:    sli v0.8h, v1.8h, #14119; CHECK-NEXT:    ret4120  %tmp1 = load <8 x i16>, ptr %A4121  %tmp2 = load <8 x i16>, ptr %B4122  %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)4123  ret <8 x i16> %tmp34124}4125 4126define <4 x i32> @sli4s(ptr %A, ptr %B) nounwind {4127; CHECK-LABEL: sli4s:4128; CHECK:       // %bb.0:4129; CHECK-NEXT:    ldr q0, [x0]4130; CHECK-NEXT:    ldr q1, [x1]4131; CHECK-NEXT:    sli v0.4s, v1.4s, #14132; CHECK-NEXT:    ret4133  %tmp1 = load <4 x i32>, ptr %A4134  %tmp2 = load <4 x i32>, ptr %B4135  %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)4136  ret <4 x i32> %tmp34137}4138 4139define <2 x i64> @sli2d(ptr %A, ptr %B) nounwind {4140; CHECK-LABEL: sli2d:4141; CHECK:       // %bb.0:4142; CHECK-NEXT:    ldr q0, [x0]4143; CHECK-NEXT:    ldr q1, [x1]4144; CHECK-NEXT:    sli v0.2d, v1.2d, #14145; CHECK-NEXT:    ret4146  %tmp1 = load <2 x i64>, ptr %A4147  %tmp2 = load <2 x i64>, ptr %B4148  %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)4149  ret <2 x i64> %tmp34150}4151 4152declare <8 x i8>  @llvm.aarch64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone4153declare <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone4154declare <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32>, <2 x i32>, i32) nounwind readnone4155declare <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) nounwind readnone4156 4157declare <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwind readnone4158declare <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone4159declare <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone4160declare <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone4161 4162define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) {4163; CHECK-SD-LABEL: ashr_v1i64:4164; CHECK-SD:       // %bb.0:4165; CHECK-SD-NEXT:    neg d1, d14166; CHECK-SD-NEXT:    sshl d0, d0, d14167; CHECK-SD-NEXT:    ret4168;4169; CHECK-GI-LABEL: ashr_v1i64:4170; CHECK-GI:       // %bb.0:4171; CHECK-GI-NEXT:    fmov x8, d04172; CHECK-GI-NEXT:    fmov x9, d14173; CHECK-GI-NEXT:    asr x8, x8, x94174; CHECK-GI-NEXT:    fmov d0, x84175; CHECK-GI-NEXT:    ret4176  %c = ashr <1 x i64> %a, %b4177  ret <1 x i64> %c4178}4179 4180define void @sqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4181; CHECK-SD-LABEL: sqshl_zero_shift_amount:4182; CHECK-SD:       // %bb.0: // %entry4183; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4184; CHECK-SD-NEXT:    str q0, [x0]4185; CHECK-SD-NEXT:    ret4186;4187; CHECK-GI-LABEL: sqshl_zero_shift_amount:4188; CHECK-GI:       // %bb.0: // %entry4189; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004190; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4191; CHECK-GI-NEXT:    sqshl v0.2d, v0.2d, v2.2d4192; CHECK-GI-NEXT:    str q0, [x0]4193; CHECK-GI-NEXT:    ret4194entry:4195  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4196  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4197  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84198  ret void4199}4200 4201define void @uqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4202; CHECK-SD-LABEL: uqshl_zero_shift_amount:4203; CHECK-SD:       // %bb.0: // %entry4204; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4205; CHECK-SD-NEXT:    str q0, [x0]4206; CHECK-SD-NEXT:    ret4207;4208; CHECK-GI-LABEL: uqshl_zero_shift_amount:4209; CHECK-GI:       // %bb.0: // %entry4210; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004211; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4212; CHECK-GI-NEXT:    uqshl v0.2d, v0.2d, v2.2d4213; CHECK-GI-NEXT:    str q0, [x0]4214; CHECK-GI-NEXT:    ret4215entry:4216  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4217  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4218  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84219  ret void4220}4221 4222define void @srshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4223; CHECK-SD-LABEL: srshl_zero_shift_amount:4224; CHECK-SD:       // %bb.0: // %entry4225; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4226; CHECK-SD-NEXT:    str q0, [x0]4227; CHECK-SD-NEXT:    ret4228;4229; CHECK-GI-LABEL: srshl_zero_shift_amount:4230; CHECK-GI:       // %bb.0: // %entry4231; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004232; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4233; CHECK-GI-NEXT:    srshl v0.2d, v0.2d, v2.2d4234; CHECK-GI-NEXT:    str q0, [x0]4235; CHECK-GI-NEXT:    ret4236entry:4237  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4238  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4239  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84240  ret void4241}4242 4243define void @urshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4244; CHECK-SD-LABEL: urshl_zero_shift_amount:4245; CHECK-SD:       // %bb.0: // %entry4246; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4247; CHECK-SD-NEXT:    str q0, [x0]4248; CHECK-SD-NEXT:    ret4249;4250; CHECK-GI-LABEL: urshl_zero_shift_amount:4251; CHECK-GI:       // %bb.0: // %entry4252; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004253; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4254; CHECK-GI-NEXT:    urshl v0.2d, v0.2d, v2.2d4255; CHECK-GI-NEXT:    str q0, [x0]4256; CHECK-GI-NEXT:    ret4257entry:4258  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4259  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4260  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84261  ret void4262}4263 4264define void @sqshlu_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4265; CHECK-LABEL: sqshlu_zero_shift_amount:4266; CHECK:       // %bb.0: // %entry4267; CHECK-NEXT:    addp v0.2d, v0.2d, v1.2d4268; CHECK-NEXT:    sqshlu v0.2d, v0.2d, #04269; CHECK-NEXT:    str q0, [x0]4270; CHECK-NEXT:    ret4271entry:4272  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4273  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4274  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84275  ret void4276}4277 4278define void @sshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4279; CHECK-SD-LABEL: sshl_zero_shift_amount:4280; CHECK-SD:       // %bb.0: // %entry4281; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4282; CHECK-SD-NEXT:    str q0, [x0]4283; CHECK-SD-NEXT:    ret4284;4285; CHECK-GI-LABEL: sshl_zero_shift_amount:4286; CHECK-GI:       // %bb.0: // %entry4287; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004288; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4289; CHECK-GI-NEXT:    sshl v0.2d, v0.2d, v2.2d4290; CHECK-GI-NEXT:    str q0, [x0]4291; CHECK-GI-NEXT:    ret4292entry:4293  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4294  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4295  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84296  ret void4297}4298 4299define void @ushl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {4300; CHECK-SD-LABEL: ushl_zero_shift_amount:4301; CHECK-SD:       // %bb.0: // %entry4302; CHECK-SD-NEXT:    addp v0.2d, v0.2d, v1.2d4303; CHECK-SD-NEXT:    str q0, [x0]4304; CHECK-SD-NEXT:    ret4305;4306; CHECK-GI-LABEL: ushl_zero_shift_amount:4307; CHECK-GI:       // %bb.0: // %entry4308; CHECK-GI-NEXT:    movi v2.2d, #00000000000000004309; CHECK-GI-NEXT:    addp v0.2d, v0.2d, v1.2d4310; CHECK-GI-NEXT:    ushl v0.2d, v0.2d, v2.2d4311; CHECK-GI-NEXT:    str q0, [x0]4312; CHECK-GI-NEXT:    ret4313entry:4314  %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)4315  %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)4316  store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 84317  ret void4318}4319 4320define <4 x i32> @sext_rshrn(<4 x i32> noundef %a) {4321; CHECK-LABEL: sext_rshrn:4322; CHECK:       // %bb.0: // %entry4323; CHECK-NEXT:    rshrn v0.4h, v0.4s, #134324; CHECK-NEXT:    sshll v0.4s, v0.4h, #04325; CHECK-NEXT:    ret4326entry:4327  %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)4328  %vmovl.i = sext <4 x i16> %vrshrn_n1 to <4 x i32>4329  ret <4 x i32> %vmovl.i4330}4331 4332define <4 x i32> @zext_rshrn(<4 x i32> noundef %a) {4333; CHECK-LABEL: zext_rshrn:4334; CHECK:       // %bb.0: // %entry4335; CHECK-NEXT:    rshrn v0.4h, v0.4s, #134336; CHECK-NEXT:    ushll v0.4s, v0.4h, #04337; CHECK-NEXT:    ret4338entry:4339  %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)4340  %vmovl.i = zext <4 x i16> %vrshrn_n1 to <4 x i32>4341  ret <4 x i32> %vmovl.i4342}4343 4344define <4 x i16> @mul_rshrn(<4 x i32> noundef %a) {4345; CHECK-LABEL: mul_rshrn:4346; CHECK:       // %bb.0: // %entry4347; CHECK-NEXT:    movi v1.4s, #34348; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s4349; CHECK-NEXT:    rshrn v0.4h, v0.4s, #134350; CHECK-NEXT:    ret4351entry:4352  %b = add <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>4353  %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %b, i32 13)4354  ret <4 x i16> %vrshrn_n14355}4356 4357define <8 x i16> @signbits_vashr(<8 x i16> %a)  {4358; CHECK-SD-LABEL: signbits_vashr:4359; CHECK-SD:       // %bb.0:4360; CHECK-SD-NEXT:    sshr v0.8h, v0.8h, #84361; CHECK-SD-NEXT:    sshr v0.8h, v0.8h, #94362; CHECK-SD-NEXT:    ret4363;4364; CHECK-GI-LABEL: signbits_vashr:4365; CHECK-GI:       // %bb.0:4366; CHECK-GI-NEXT:    mvni v1.8h, #74367; CHECK-GI-NEXT:    mvni v2.8h, #84368; CHECK-GI-NEXT:    sshl v0.8h, v0.8h, v1.8h4369; CHECK-GI-NEXT:    sshl v0.8h, v0.8h, v2.8h4370; CHECK-GI-NEXT:    sshr v0.8h, v0.8h, #74371; CHECK-GI-NEXT:    ret4372  %b = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %a, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)4373  %c = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %b, <8 x i16> <i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9>)4374  %d = ashr <8 x i16> %c, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>4375  ret <8 x i16> %d4376}4377 4378define <2 x i8> @lshr_trunc_v2i64_v2i8(<2 x i64> %a) {4379; CHECK-SD-LABEL: lshr_trunc_v2i64_v2i8:4380; CHECK-SD:       // %bb.0:4381; CHECK-SD-NEXT:    shrn v0.2s, v0.2d, #164382; CHECK-SD-NEXT:    ret4383;4384; CHECK-GI-LABEL: lshr_trunc_v2i64_v2i8:4385; CHECK-GI:       // %bb.0:4386; CHECK-GI-NEXT:    xtn v0.2s, v0.2d4387; CHECK-GI-NEXT:    ushr v0.2s, v0.2s, #164388; CHECK-GI-NEXT:    ret4389  %b = lshr <2 x i64> %a, <i64 16, i64 16>4390  %c = trunc <2 x i64> %b to <2 x i8>4391  ret <2 x i8> %c4392}4393 4394define <4 x i16> @lshr_trunc_v4i64_v4i16(<4 x i64> %a) {4395; CHECK-SD-LABEL: lshr_trunc_v4i64_v4i16:4396; CHECK-SD:       // %bb.0:4397; CHECK-SD-NEXT:    xtn v1.2s, v1.2d4398; CHECK-SD-NEXT:    xtn v0.2s, v0.2d4399; CHECK-SD-NEXT:    ushr v1.2s, v1.2s, #84400; CHECK-SD-NEXT:    ushr v0.2s, v0.2s, #84401; CHECK-SD-NEXT:    uzp1 v0.4h, v0.4h, v1.4h4402; CHECK-SD-NEXT:    ret4403;4404; CHECK-GI-LABEL: lshr_trunc_v4i64_v4i16:4405; CHECK-GI:       // %bb.0:4406; CHECK-GI-NEXT:    adrp x8, .LCPI270_04407; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s4408; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI270_0]4409; CHECK-GI-NEXT:    uzp1 v2.4s, v2.4s, v2.4s4410; CHECK-GI-NEXT:    neg v1.4s, v2.4s4411; CHECK-GI-NEXT:    ushl v0.4s, v0.4s, v1.4s4412; CHECK-GI-NEXT:    xtn v0.4h, v0.4s4413; CHECK-GI-NEXT:    ret4414  %b = lshr <4 x i64> %a, <i64 8, i64 8, i64 8, i64 8>4415  %c = trunc <4 x i64> %b to <4 x i16>4416  ret <4 x i16> %c4417}4418 4419define <2 x i8> @ashr_trunc_v2i64_v2i8(<2 x i64> %a) {4420; CHECK-SD-LABEL: ashr_trunc_v2i64_v2i8:4421; CHECK-SD:       // %bb.0:4422; CHECK-SD-NEXT:    shrn v0.2s, v0.2d, #164423; CHECK-SD-NEXT:    ret4424;4425; CHECK-GI-LABEL: ashr_trunc_v2i64_v2i8:4426; CHECK-GI:       // %bb.0:4427; CHECK-GI-NEXT:    xtn v0.2s, v0.2d4428; CHECK-GI-NEXT:    sshr v0.2s, v0.2s, #164429; CHECK-GI-NEXT:    ret4430  %b = ashr <2 x i64> %a, <i64 16, i64 16>4431  %c = trunc <2 x i64> %b to <2 x i8>4432  ret <2 x i8> %c4433}4434 4435define <4 x i16> @ashr_trunc_v4i64_v4i16(<4 x i64> %a) {4436; CHECK-SD-LABEL: ashr_trunc_v4i64_v4i16:4437; CHECK-SD:       // %bb.0:4438; CHECK-SD-NEXT:    xtn v1.2s, v1.2d4439; CHECK-SD-NEXT:    xtn v0.2s, v0.2d4440; CHECK-SD-NEXT:    ushr v1.2s, v1.2s, #84441; CHECK-SD-NEXT:    ushr v0.2s, v0.2s, #84442; CHECK-SD-NEXT:    uzp1 v0.4h, v0.4h, v1.4h4443; CHECK-SD-NEXT:    ret4444;4445; CHECK-GI-LABEL: ashr_trunc_v4i64_v4i16:4446; CHECK-GI:       // %bb.0:4447; CHECK-GI-NEXT:    adrp x8, .LCPI272_04448; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s4449; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI272_0]4450; CHECK-GI-NEXT:    uzp1 v2.4s, v2.4s, v2.4s4451; CHECK-GI-NEXT:    neg v1.4s, v2.4s4452; CHECK-GI-NEXT:    sshl v0.4s, v0.4s, v1.4s4453; CHECK-GI-NEXT:    xtn v0.4h, v0.4s4454; CHECK-GI-NEXT:    ret4455  %b = ashr <4 x i64> %a, <i64 8, i64 8, i64 8, i64 8>4456  %c = trunc <4 x i64> %b to <4 x i16>4457  ret <4 x i16> %c4458}4459 4460define <2 x i8> @shl_trunc_v2i64_v2i8(<2 x i64> %a) {4461; CHECK-SD-LABEL: shl_trunc_v2i64_v2i8:4462; CHECK-SD:       // %bb.0:4463; CHECK-SD-NEXT:    xtn v0.2s, v0.2d4464; CHECK-SD-NEXT:    shl v0.2s, v0.2s, #164465; CHECK-SD-NEXT:    ret4466;4467; CHECK-GI-LABEL: shl_trunc_v2i64_v2i8:4468; CHECK-GI:       // %bb.0:4469; CHECK-GI-NEXT:    shl v0.2d, v0.2d, #164470; CHECK-GI-NEXT:    xtn v0.2s, v0.2d4471; CHECK-GI-NEXT:    ret4472  %b = shl <2 x i64> %a, <i64 16, i64 16>4473  %c = trunc <2 x i64> %b to <2 x i8>4474  ret <2 x i8> %c4475}4476 4477define <4 x i16> @shl_trunc_v4i64_v4i16(<4 x i64> %a) {4478; CHECK-SD-LABEL: shl_trunc_v4i64_v4i16:4479; CHECK-SD:       // %bb.0:4480; CHECK-SD-NEXT:    uzp1 v0.4s, v0.4s, v1.4s4481; CHECK-SD-NEXT:    xtn v0.4h, v0.4s4482; CHECK-SD-NEXT:    shl v0.4h, v0.4h, #84483; CHECK-SD-NEXT:    ret4484;4485; CHECK-GI-LABEL: shl_trunc_v4i64_v4i16:4486; CHECK-GI:       // %bb.0:4487; CHECK-GI-NEXT:    adrp x8, .LCPI274_04488; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s4489; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI274_0]4490; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v2.4s4491; CHECK-GI-NEXT:    xtn v0.4h, v0.4s4492; CHECK-GI-NEXT:    xtn v1.4h, v1.4s4493; CHECK-GI-NEXT:    ushl v0.4h, v0.4h, v1.4h4494; CHECK-GI-NEXT:    ret4495  %b = shl <4 x i64> %a, <i64 8, i64 8, i64 8, i64 8>4496  %c = trunc <4 x i64> %b to <4 x i16>4497  ret <4 x i16> %c4498}4499 4500declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>)4501