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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s2 3define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {4; CHECK-LABEL: testShiftRightArith_v8i16:5; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]6; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]7 8entry:9 %a.addr = alloca <8 x i16>, align 1610 %b.addr = alloca <8 x i16>, align 1611 store <8 x i16> %a, ptr %a.addr, align 1612 store <8 x i16> %b, ptr %b.addr, align 1613 %0 = load <8 x i16>, ptr %a.addr, align 1614 %1 = load <8 x i16>, ptr %b.addr, align 1615 %shr = ashr <8 x i16> %0, %116 ret <8 x i16> %shr17}18 19define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {20; CHECK-LABEL: testShiftRightArith_v4i32:21; CHECK: neg.4s [[REG3:v[0-9]+]], [[REG3]]22; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]23entry:24 %a.addr = alloca <4 x i32>, align 3225 %b.addr = alloca <4 x i32>, align 3226 store <4 x i32> %a, ptr %a.addr, align 3227 store <4 x i32> %b, ptr %b.addr, align 3228 %0 = load <4 x i32>, ptr %a.addr, align 3229 %1 = load <4 x i32>, ptr %b.addr, align 3230 %shr = ashr <4 x i32> %0, %131 ret <4 x i32> %shr32}33 34define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {35; CHECK: testShiftRightLogical36; CHECK: neg.8h [[REG5:v[0-9]+]], [[REG5]]37; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]38entry:39 %a.addr = alloca <8 x i16>, align 1640 %b.addr = alloca <8 x i16>, align 1641 store <8 x i16> %a, ptr %a.addr, align 1642 store <8 x i16> %b, ptr %b.addr, align 1643 %0 = load <8 x i16>, ptr %a.addr, align 1644 %1 = load <8 x i16>, ptr %b.addr, align 1645 %shr = lshr <8 x i16> %0, %146 ret <8 x i16> %shr47}48 49define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {50; CHECK-LABEL: sshr_v1i64:51; CHECK: sshr d0, d0, #4252 %tmp3 = ashr <1 x i64> %A, < i64 42 >53 ret <1 x i64> %tmp354}55 56define <1 x i64> @cmlt_v1i64(<1 x i64> %A) nounwind {57; CHECK-LABEL: cmlt_v1i64:58; CHECK: cmlt d0, d0, #059 %tmp3 = ashr <1 x i64> %A, < i64 63 >60 ret <1 x i64> %tmp361}62 63define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {64; CHECK-LABEL: ushr_v1i64:65; CHECK: ushr d0, d0, #6366 %tmp3 = lshr <1 x i64> %A, < i64 63 >67 ret <1 x i64> %tmp368}69 70attributes #0 = { nounwind }71