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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s2 3define <8 x i8> @subhn8b(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: subhn8b:5;CHECK: subhn.8b6 %tmp1 = load <8 x i16>, ptr %A7 %tmp2 = load <8 x i16>, ptr %B8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @subhn4h(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: subhn4h:14;CHECK: subhn.4h15 %tmp1 = load <4 x i32>, ptr %A16 %tmp2 = load <4 x i32>, ptr %B17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @subhn2s(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: subhn2s:23;CHECK: subhn.2s24 %tmp1 = load <2 x i64>, ptr %A25 %tmp2 = load <2 x i64>, ptr %B26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)27 ret <2 x i32> %tmp328}29 30define <16 x i8> @subhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {31;CHECK-LABEL: subhn2_16b:32;CHECK: subhn.8b33;CHECK-NEXT: subhn2.16b34 %vsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind35 %vsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind36 %res = shufflevector <8 x i8> %vsubhn2.i, <8 x i8> %vsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>37 ret <16 x i8> %res38}39 40define <8 x i16> @subhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {41;CHECK-LABEL: subhn2_8h:42;CHECK: subhn.4h43;CHECK-NEXT: subhn2.8h44 %vsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind45 %vsubhn_high3.i = tail call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind46 %res = shufflevector <4 x i16> %vsubhn2.i, <4 x i16> %vsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>47 ret <8 x i16> %res48}49 50define <4 x i32> @subhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {51;CHECK-LABEL: subhn2_4s:52;CHECK: subhn.2s53;CHECK-NEXT: subhn2.4s54 %vsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind55 %vsubhn_high3.i = tail call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind56 %res = shufflevector <2 x i32> %vsubhn2.i, <2 x i32> %vsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>57 ret <4 x i32> %res58}59 60declare <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone61declare <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone62declare <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone63 64define <8 x i8> @rsubhn8b(ptr %A, ptr %B) nounwind {65;CHECK-LABEL: rsubhn8b:66;CHECK: rsubhn.8b67 %tmp1 = load <8 x i16>, ptr %A68 %tmp2 = load <8 x i16>, ptr %B69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)70 ret <8 x i8> %tmp371}72 73define <4 x i16> @rsubhn4h(ptr %A, ptr %B) nounwind {74;CHECK-LABEL: rsubhn4h:75;CHECK: rsubhn.4h76 %tmp1 = load <4 x i32>, ptr %A77 %tmp2 = load <4 x i32>, ptr %B78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)79 ret <4 x i16> %tmp380}81 82define <2 x i32> @rsubhn2s(ptr %A, ptr %B) nounwind {83;CHECK-LABEL: rsubhn2s:84;CHECK: rsubhn.2s85 %tmp1 = load <2 x i64>, ptr %A86 %tmp2 = load <2 x i64>, ptr %B87 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)88 ret <2 x i32> %tmp389}90 91define <16 x i8> @rsubhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {92;CHECK-LABEL: rsubhn2_16b:93;CHECK: rsubhn.8b94;CHECK-NEXT: rsubhn2.16b95 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind96 %vrsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind97 %res = shufflevector <8 x i8> %vrsubhn2.i, <8 x i8> %vrsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>98 ret <16 x i8> %res99}100 101define <8 x i16> @rsubhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {102;CHECK-LABEL: rsubhn2_8h:103;CHECK: rsubhn.4h104;CHECK-NEXT: rsubhn2.8h105 %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind106 %vrsubhn_high3.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind107 %res = shufflevector <4 x i16> %vrsubhn2.i, <4 x i16> %vrsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>108 ret <8 x i16> %res109}110 111define <4 x i32> @rsubhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {112;CHECK-LABEL: rsubhn2_4s:113;CHECK: rsubhn.2s114;CHECK-NEXT: rsubhn2.4s115 %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind116 %vrsubhn_high3.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind117 %res = shufflevector <2 x i32> %vrsubhn2.i, <2 x i32> %vrsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>118 ret <4 x i32> %res119}120 121declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone122declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone123declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone124 125define <8 x i16> @ssubl8h(ptr %A, ptr %B) nounwind {126;CHECK-LABEL: ssubl8h:127;CHECK: ssubl.8h128 %tmp1 = load <8 x i8>, ptr %A129 %tmp2 = load <8 x i8>, ptr %B130 %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>131 %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>132 %tmp5 = sub <8 x i16> %tmp3, %tmp4133 ret <8 x i16> %tmp5134}135 136define <4 x i32> @ssubl4s(ptr %A, ptr %B) nounwind {137;CHECK-LABEL: ssubl4s:138;CHECK: ssubl.4s139 %tmp1 = load <4 x i16>, ptr %A140 %tmp2 = load <4 x i16>, ptr %B141 %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>142 %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>143 %tmp5 = sub <4 x i32> %tmp3, %tmp4144 ret <4 x i32> %tmp5145}146 147define <2 x i64> @ssubl2d(ptr %A, ptr %B) nounwind {148;CHECK-LABEL: ssubl2d:149;CHECK: ssubl.2d150 %tmp1 = load <2 x i32>, ptr %A151 %tmp2 = load <2 x i32>, ptr %B152 %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>153 %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>154 %tmp5 = sub <2 x i64> %tmp3, %tmp4155 ret <2 x i64> %tmp5156}157 158define <8 x i16> @ssubl2_8h(ptr %A, ptr %B) nounwind {159;CHECK-LABEL: ssubl2_8h:160;CHECK: ssubl.8h161 %tmp1 = load <16 x i8>, ptr %A162 %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>163 %ext1 = sext <8 x i8> %high1 to <8 x i16>164 165 %tmp2 = load <16 x i8>, ptr %B166 %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>167 %ext2 = sext <8 x i8> %high2 to <8 x i16>168 169 %res = sub <8 x i16> %ext1, %ext2170 ret <8 x i16> %res171}172 173define <4 x i32> @ssubl2_4s(ptr %A, ptr %B) nounwind {174;CHECK-LABEL: ssubl2_4s:175;CHECK: ssubl.4s176 %tmp1 = load <8 x i16>, ptr %A177 %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>178 %ext1 = sext <4 x i16> %high1 to <4 x i32>179 180 %tmp2 = load <8 x i16>, ptr %B181 %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>182 %ext2 = sext <4 x i16> %high2 to <4 x i32>183 184 %res = sub <4 x i32> %ext1, %ext2185 ret <4 x i32> %res186}187 188define <2 x i64> @ssubl2_2d(ptr %A, ptr %B) nounwind {189;CHECK-LABEL: ssubl2_2d:190;CHECK: ssubl.2d191 %tmp1 = load <4 x i32>, ptr %A192 %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>193 %ext1 = sext <2 x i32> %high1 to <2 x i64>194 195 %tmp2 = load <4 x i32>, ptr %B196 %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>197 %ext2 = sext <2 x i32> %high2 to <2 x i64>198 199 %res = sub <2 x i64> %ext1, %ext2200 ret <2 x i64> %res201}202 203define <8 x i16> @usubl8h(ptr %A, ptr %B) nounwind {204;CHECK-LABEL: usubl8h:205;CHECK: usubl.8h206 %tmp1 = load <8 x i8>, ptr %A207 %tmp2 = load <8 x i8>, ptr %B208 %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>209 %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>210 %tmp5 = sub <8 x i16> %tmp3, %tmp4211 ret <8 x i16> %tmp5212}213 214define <4 x i32> @usubl4s(ptr %A, ptr %B) nounwind {215;CHECK-LABEL: usubl4s:216;CHECK: usubl.4s217 %tmp1 = load <4 x i16>, ptr %A218 %tmp2 = load <4 x i16>, ptr %B219 %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>220 %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>221 %tmp5 = sub <4 x i32> %tmp3, %tmp4222 ret <4 x i32> %tmp5223}224 225define <2 x i64> @usubl2d(ptr %A, ptr %B) nounwind {226;CHECK-LABEL: usubl2d:227;CHECK: usubl.2d228 %tmp1 = load <2 x i32>, ptr %A229 %tmp2 = load <2 x i32>, ptr %B230 %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>231 %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>232 %tmp5 = sub <2 x i64> %tmp3, %tmp4233 ret <2 x i64> %tmp5234}235 236define <8 x i16> @usubl2_8h(ptr %A, ptr %B) nounwind {237;CHECK-LABEL: usubl2_8h:238;CHECK: usubl.8h239 %tmp1 = load <16 x i8>, ptr %A240 %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>241 %ext1 = zext <8 x i8> %high1 to <8 x i16>242 243 %tmp2 = load <16 x i8>, ptr %B244 %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>245 %ext2 = zext <8 x i8> %high2 to <8 x i16>246 247 %res = sub <8 x i16> %ext1, %ext2248 ret <8 x i16> %res249}250 251define <4 x i32> @usubl2_4s(ptr %A, ptr %B) nounwind {252;CHECK-LABEL: usubl2_4s:253;CHECK: usubl.4s254 %tmp1 = load <8 x i16>, ptr %A255 %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>256 %ext1 = zext <4 x i16> %high1 to <4 x i32>257 258 %tmp2 = load <8 x i16>, ptr %B259 %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>260 %ext2 = zext <4 x i16> %high2 to <4 x i32>261 262 %res = sub <4 x i32> %ext1, %ext2263 ret <4 x i32> %res264}265 266define <2 x i64> @usubl2_2d(ptr %A, ptr %B) nounwind {267;CHECK-LABEL: usubl2_2d:268;CHECK: usubl.2d269 %tmp1 = load <4 x i32>, ptr %A270 %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>271 %ext1 = zext <2 x i32> %high1 to <2 x i64>272 273 %tmp2 = load <4 x i32>, ptr %B274 %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>275 %ext2 = zext <2 x i32> %high2 to <2 x i64>276 277 %res = sub <2 x i64> %ext1, %ext2278 ret <2 x i64> %res279}280 281define <8 x i16> @ssubw8h(ptr %A, ptr %B) nounwind {282;CHECK-LABEL: ssubw8h:283;CHECK: ssubw.8h284 %tmp1 = load <8 x i16>, ptr %A285 %tmp2 = load <8 x i8>, ptr %B286 %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>287 %tmp4 = sub <8 x i16> %tmp1, %tmp3288 ret <8 x i16> %tmp4289}290 291define <4 x i32> @ssubw4s(ptr %A, ptr %B) nounwind {292;CHECK-LABEL: ssubw4s:293;CHECK: ssubw.4s294 %tmp1 = load <4 x i32>, ptr %A295 %tmp2 = load <4 x i16>, ptr %B296 %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>297 %tmp4 = sub <4 x i32> %tmp1, %tmp3298 ret <4 x i32> %tmp4299}300 301define <2 x i64> @ssubw2d(ptr %A, ptr %B) nounwind {302;CHECK-LABEL: ssubw2d:303;CHECK: ssubw.2d304 %tmp1 = load <2 x i64>, ptr %A305 %tmp2 = load <2 x i32>, ptr %B306 %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>307 %tmp4 = sub <2 x i64> %tmp1, %tmp3308 ret <2 x i64> %tmp4309}310 311define <8 x i16> @ssubw2_8h(ptr %A, ptr %B) nounwind {312;CHECK-LABEL: ssubw2_8h:313;CHECK: ssubw.8h314 %tmp1 = load <8 x i16>, ptr %A315 316 %tmp2 = load <16 x i8>, ptr %B317 %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>318 %ext2 = sext <8 x i8> %high2 to <8 x i16>319 320 %res = sub <8 x i16> %tmp1, %ext2321 ret <8 x i16> %res322}323 324define <4 x i32> @ssubw2_4s(ptr %A, ptr %B) nounwind {325;CHECK-LABEL: ssubw2_4s:326;CHECK: ssubw.4s327 %tmp1 = load <4 x i32>, ptr %A328 329 %tmp2 = load <8 x i16>, ptr %B330 %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>331 %ext2 = sext <4 x i16> %high2 to <4 x i32>332 333 %res = sub <4 x i32> %tmp1, %ext2334 ret <4 x i32> %res335}336 337define <2 x i64> @ssubw2_2d(ptr %A, ptr %B) nounwind {338;CHECK-LABEL: ssubw2_2d:339;CHECK: ssubw.2d340 %tmp1 = load <2 x i64>, ptr %A341 342 %tmp2 = load <4 x i32>, ptr %B343 %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>344 %ext2 = sext <2 x i32> %high2 to <2 x i64>345 346 %res = sub <2 x i64> %tmp1, %ext2347 ret <2 x i64> %res348}349 350define <8 x i16> @usubw8h(ptr %A, ptr %B) nounwind {351;CHECK-LABEL: usubw8h:352;CHECK: usubw.8h353 %tmp1 = load <8 x i16>, ptr %A354 %tmp2 = load <8 x i8>, ptr %B355 %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>356 %tmp4 = sub <8 x i16> %tmp1, %tmp3357 ret <8 x i16> %tmp4358}359 360define <4 x i32> @usubw4s(ptr %A, ptr %B) nounwind {361;CHECK-LABEL: usubw4s:362;CHECK: usubw.4s363 %tmp1 = load <4 x i32>, ptr %A364 %tmp2 = load <4 x i16>, ptr %B365 %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>366 %tmp4 = sub <4 x i32> %tmp1, %tmp3367 ret <4 x i32> %tmp4368}369 370define <2 x i64> @usubw2d(ptr %A, ptr %B) nounwind {371;CHECK-LABEL: usubw2d:372;CHECK: usubw.2d373 %tmp1 = load <2 x i64>, ptr %A374 %tmp2 = load <2 x i32>, ptr %B375 %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>376 %tmp4 = sub <2 x i64> %tmp1, %tmp3377 ret <2 x i64> %tmp4378}379 380define <8 x i16> @usubw2_8h(ptr %A, ptr %B) nounwind {381;CHECK-LABEL: usubw2_8h:382;CHECK: usubw.8h383 %tmp1 = load <8 x i16>, ptr %A384 385 %tmp2 = load <16 x i8>, ptr %B386 %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>387 %ext2 = zext <8 x i8> %high2 to <8 x i16>388 389 %res = sub <8 x i16> %tmp1, %ext2390 ret <8 x i16> %res391}392 393define <4 x i32> @usubw2_4s(ptr %A, ptr %B) nounwind {394;CHECK-LABEL: usubw2_4s:395;CHECK: usubw.4s396 %tmp1 = load <4 x i32>, ptr %A397 398 %tmp2 = load <8 x i16>, ptr %B399 %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>400 %ext2 = zext <4 x i16> %high2 to <4 x i32>401 402 %res = sub <4 x i32> %tmp1, %ext2403 ret <4 x i32> %res404}405 406define <2 x i64> @usubw2_2d(ptr %A, ptr %B) nounwind {407;CHECK-LABEL: usubw2_2d:408;CHECK: usubw.2d409 %tmp1 = load <2 x i64>, ptr %A410 411 %tmp2 = load <4 x i32>, ptr %B412 %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>413 %ext2 = zext <2 x i32> %high2 to <2 x i64>414 415 %res = sub <2 x i64> %tmp1, %ext2416 ret <2 x i64> %res417}418