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1; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR1282; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+fullfp16 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128-FULLFP163; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,ZCZ-FPR644; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR645; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+zcz-fpr128 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR1286; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,FP-WORKAROUND7; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR1288; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR649; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-FPR6410; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-FPR6411 12define half @tf16() {13entry:14; ALL-LABEL: tf16:15; FP-WORKAROUND: mov s0, wzr16; NOZCZ-FPR64-NOZCZ-FPR128: mov s0, wzr17; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: mov h0, wzr18; ZCZ-FPR64: movi d0, #019; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #020 ret half 0.021}22 23define float @tf32() {24entry:25; ALL-LABEL: tf32:26; FP-WORKAROUND: mov s0, wzr27; NOZCZ-FPR64-NOZCZ-FPR128: mov s0, wzr28; ZCZ-FPR64: movi d0, #029; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #030 ret float 0.031}32 33define double @td64() {34entry:35; ALL-LABEL: td64:36; FP-WORKAROUND: mov d0, xzr37; NOZCZ-FPR64-NOZCZ-FPR128: mov d0, xzr38; ZCZ-FPR64: movi d0, #039; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #040 ret double 0.041}42 43define <8 x i8> @tv8i8() {44entry:45; ALL-LABEL: tv8i8:46; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #047; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #048; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #049; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #050 ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>51}52 53define <4 x i16> @tv4i16() {54entry:55; ALL-LABEL: tv4i16:56; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #057; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #058; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #059; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #060 ret <4 x i16> <i16 0, i16 0, i16 0, i16 0>61}62 63define <2 x i32> @tv2i32() {64entry:65; ALL-LABEL: tv2i32:66; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #067; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #068; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #069; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #070 ret <2 x i32> <i32 0, i32 0>71}72 73define <2 x float> @tv2f32() {74entry:75; ALL-LABEL: tv2f32:76; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #077; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #078; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #079; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #080 ret <2 x float> <float 0.0, float 0.0>81}82 83define <16 x i8> @tv16i8() {84entry:85; ALL-LABEL: tv16i8:86; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #087; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #088; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #089; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #090 ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>91}92 93define <8 x i16> @tv8i16() {94entry:95; ALL-LABEL: tv8i16:96; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #097; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #098; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #099; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0100 ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>101}102 103define <4 x i32> @tv4i32() {104entry:105; ALL-LABEL: tv4i32:106; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0107; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0108; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0109; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0110 ret <4 x i32> <i32 0, i32 0, i32 0, i32 0>111}112 113define <2 x i64> @tv2i64() {114entry:115; ALL-LABEL: tv2i64:116; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0117; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0118; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0119; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0120 ret <2 x i64> <i64 0, i64 0>121}122 123define <4 x float> @tv4f32() {124entry:125; ALL-LABEL: tv4f32:126; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0127; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0128; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0129; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0130 ret <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>131}132 133define <2 x double> @tv2d64() {134entry:135; ALL-LABEL: tv2d64:136; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0137; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0138; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0139; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0140 ret <2 x double> <double 0.0, double 0.0>141}142 143; We used to produce spills+reloads for a Q register with zero cycle zeroing144; enabled.145; ALL-LABEL: foo:146; ALL-NOT: str q{{[0-9]+}}147; ALL-NOT: ldr q{{[0-9]+}}148define double @foo(i32 %n) {149entry:150 br label %for.body151 152for.body:153 %phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ]154 %i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ]155 %conv21 = sitofp i32 %i.076 to double156 %call = tail call fast double @sin(double %conv21)157 %cmp.i = fcmp fast olt double %phi0, %call158 %v0 = select i1 %cmp.i, double %call, double %phi0159 %inc = add nuw nsw i32 %i.076, 1160 %cmp = icmp slt i32 %inc, %n161 br i1 %cmp, label %for.body, label %for.end162 163for.end:164 ret double %v0165}166 167declare double @sin(double)168