443 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for shuffle_zip16; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shuffle_zip27; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shuffle_zip38 9define <8 x i8> @vzipi8(ptr %A, ptr %B) nounwind {10; CHECK-LABEL: vzipi8:11; CHECK: // %bb.0:12; CHECK-NEXT: ldr d0, [x0]13; CHECK-NEXT: ldr d1, [x1]14; CHECK-NEXT: zip1.8b v2, v0, v115; CHECK-NEXT: zip2.8b v0, v0, v116; CHECK-NEXT: add.8b v0, v2, v017; CHECK-NEXT: ret18 %tmp1 = load <8 x i8>, ptr %A19 %tmp2 = load <8 x i8>, ptr %B20 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>21 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>22 %tmp5 = add <8 x i8> %tmp3, %tmp423 ret <8 x i8> %tmp524}25 26define <4 x i16> @vzipi16(ptr %A, ptr %B) nounwind {27; CHECK-LABEL: vzipi16:28; CHECK: // %bb.0:29; CHECK-NEXT: ldr d0, [x0]30; CHECK-NEXT: ldr d1, [x1]31; CHECK-NEXT: zip1.4h v2, v0, v132; CHECK-NEXT: zip2.4h v0, v0, v133; CHECK-NEXT: add.4h v0, v2, v034; CHECK-NEXT: ret35 %tmp1 = load <4 x i16>, ptr %A36 %tmp2 = load <4 x i16>, ptr %B37 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>38 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>39 %tmp5 = add <4 x i16> %tmp3, %tmp440 ret <4 x i16> %tmp541}42 43define <16 x i8> @vzipQi8(ptr %A, ptr %B) nounwind {44; CHECK-LABEL: vzipQi8:45; CHECK: // %bb.0:46; CHECK-NEXT: ldr q0, [x0]47; CHECK-NEXT: ldr q1, [x1]48; CHECK-NEXT: zip1.16b v2, v0, v149; CHECK-NEXT: zip2.16b v0, v0, v150; CHECK-NEXT: add.16b v0, v2, v051; CHECK-NEXT: ret52 %tmp1 = load <16 x i8>, ptr %A53 %tmp2 = load <16 x i8>, ptr %B54 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>55 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>56 %tmp5 = add <16 x i8> %tmp3, %tmp457 ret <16 x i8> %tmp558}59 60define <8 x i16> @vzipQi16(ptr %A, ptr %B) nounwind {61; CHECK-LABEL: vzipQi16:62; CHECK: // %bb.0:63; CHECK-NEXT: ldr q0, [x0]64; CHECK-NEXT: ldr q1, [x1]65; CHECK-NEXT: zip1.8h v2, v0, v166; CHECK-NEXT: zip2.8h v0, v0, v167; CHECK-NEXT: add.8h v0, v2, v068; CHECK-NEXT: ret69 %tmp1 = load <8 x i16>, ptr %A70 %tmp2 = load <8 x i16>, ptr %B71 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>72 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>73 %tmp5 = add <8 x i16> %tmp3, %tmp474 ret <8 x i16> %tmp575}76 77define <4 x i32> @vzipQi32(ptr %A, ptr %B) nounwind {78; CHECK-LABEL: vzipQi32:79; CHECK: // %bb.0:80; CHECK-NEXT: ldr q0, [x0]81; CHECK-NEXT: ldr q1, [x1]82; CHECK-NEXT: zip1.4s v2, v0, v183; CHECK-NEXT: zip2.4s v0, v0, v184; CHECK-NEXT: add.4s v0, v2, v085; CHECK-NEXT: ret86 %tmp1 = load <4 x i32>, ptr %A87 %tmp2 = load <4 x i32>, ptr %B88 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>89 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>90 %tmp5 = add <4 x i32> %tmp3, %tmp491 ret <4 x i32> %tmp592}93 94define <4 x float> @vzipQf(ptr %A, ptr %B) nounwind {95; CHECK-LABEL: vzipQf:96; CHECK: // %bb.0:97; CHECK-NEXT: ldr q0, [x0]98; CHECK-NEXT: ldr q1, [x1]99; CHECK-NEXT: zip1.4s v2, v0, v1100; CHECK-NEXT: zip2.4s v0, v0, v1101; CHECK-NEXT: fadd.4s v0, v2, v0102; CHECK-NEXT: ret103 %tmp1 = load <4 x float>, ptr %A104 %tmp2 = load <4 x float>, ptr %B105 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>106 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>107 %tmp5 = fadd <4 x float> %tmp3, %tmp4108 ret <4 x float> %tmp5109}110 111; Undef shuffle indices should not prevent matching to VZIP:112 113define <8 x i8> @vzipi8_undef(ptr %A, ptr %B) nounwind {114; CHECK-LABEL: vzipi8_undef:115; CHECK: // %bb.0:116; CHECK-NEXT: ldr d0, [x0]117; CHECK-NEXT: ldr d1, [x1]118; CHECK-NEXT: zip1.8b v2, v0, v1119; CHECK-NEXT: zip2.8b v0, v0, v1120; CHECK-NEXT: add.8b v0, v2, v0121; CHECK-NEXT: ret122 %tmp1 = load <8 x i8>, ptr %A123 %tmp2 = load <8 x i8>, ptr %B124 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>125 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>126 %tmp5 = add <8 x i8> %tmp3, %tmp4127 ret <8 x i8> %tmp5128}129 130define <16 x i8> @vzipQi8_undef(ptr %A, ptr %B) nounwind {131; CHECK-LABEL: vzipQi8_undef:132; CHECK: // %bb.0:133; CHECK-NEXT: ldr q0, [x0]134; CHECK-NEXT: ldr q1, [x1]135; CHECK-NEXT: zip1.16b v2, v0, v1136; CHECK-NEXT: zip2.16b v0, v0, v1137; CHECK-NEXT: add.16b v0, v2, v0138; CHECK-NEXT: ret139 %tmp1 = load <16 x i8>, ptr %A140 %tmp2 = load <16 x i8>, ptr %B141 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>142 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>143 %tmp5 = add <16 x i8> %tmp3, %tmp4144 ret <16 x i8> %tmp5145}146 147define <8 x i16> @vzip1_undef_01(<8 x i16> %A, <8 x i16> %B) nounwind {148; CHECK-LABEL: vzip1_undef_01:149; CHECK: // %bb.0:150; CHECK-NEXT: zip1.8h v0, v0, v1151; CHECK-NEXT: ret152 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>153 ret <8 x i16> %s154}155 156define <8 x i16> @vzip1_undef_0(<8 x i16> %A, <8 x i16> %B) nounwind {157; CHECK-LABEL: vzip1_undef_0:158; CHECK: // %bb.0:159; CHECK-NEXT: zip1.8h v0, v0, v1160; CHECK-NEXT: ret161 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>162 ret <8 x i16> %s163}164 165define <8 x i16> @vzip1_undef_1(<8 x i16> %A, <8 x i16> %B) nounwind {166; CHECK-LABEL: vzip1_undef_1:167; CHECK: // %bb.0:168; CHECK-NEXT: zip1.8h v0, v0, v1169; CHECK-NEXT: ret170 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>171 ret <8 x i16> %s172}173 174define <8 x i16> @vzip1_undef_012(<8 x i16> %A, <8 x i16> %B) nounwind {175; CHECK-LABEL: vzip1_undef_012:176; CHECK: // %bb.0:177; CHECK-NEXT: zip1.8h v0, v0, v1178; CHECK-NEXT: ret179 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 9, i32 2, i32 10, i32 3, i32 11>180 ret <8 x i16> %s181}182 183define <8 x i16> @vzip2_undef_01(<8 x i16> %A, <8 x i16> %B) nounwind {184; CHECK-LABEL: vzip2_undef_01:185; CHECK: // %bb.0:186; CHECK-NEXT: zip2.8h v0, v0, v1187; CHECK-NEXT: ret188 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>189 ret <8 x i16> %s190}191 192define <8 x i16> @vzip2_undef_0(<8 x i16> %A, <8 x i16> %B) nounwind {193; CHECK-LABEL: vzip2_undef_0:194; CHECK: // %bb.0:195; CHECK-NEXT: zip2.8h v0, v0, v1196; CHECK-NEXT: ret197 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>198 ret <8 x i16> %s199}200 201define <8 x i16> @vzip2_undef_1(<8 x i16> %A, <8 x i16> %B) nounwind {202; CHECK-LABEL: vzip2_undef_1:203; CHECK: // %bb.0:204; CHECK-NEXT: zip2.8h v0, v0, v1205; CHECK-NEXT: ret206 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 4, i32 undef, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>207 ret <8 x i16> %s208}209 210define <8 x i16> @vzip2_undef_012(<8 x i16> %A, <8 x i16> %B) nounwind {211; CHECK-LABEL: vzip2_undef_012:212; CHECK: // %bb.0:213; CHECK-NEXT: zip2.8h v0, v0, v1214; CHECK-NEXT: ret215 %s = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 13, i32 6, i32 14, i32 7, i32 15>216 ret <8 x i16> %s217}218 219define <16 x i8> @combine_v16i8(<8 x i8> %0, <8 x i8> %1) {220; CHECK-LABEL: combine_v16i8:221; CHECK: // %bb.0:222; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0223; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1224; CHECK-NEXT: zip1.16b v0, v0, v1225; CHECK-NEXT: ret226 %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>227 ret <16 x i8> %3228}229 230define <16 x i8> @combine2_v16i8(<8 x i8> %0, <8 x i8> %1) {231; CHECK-SD-LABEL: combine2_v16i8:232; CHECK-SD: // %bb.0:233; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0234; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1235; CHECK-SD-NEXT: zip1.16b v0, v0, v1236; CHECK-SD-NEXT: ret237;238; CHECK-GI-LABEL: combine2_v16i8:239; CHECK-GI: // %bb.0:240; CHECK-GI-NEXT: zip1.8b v2, v0, v1241; CHECK-GI-NEXT: zip2.8b v0, v0, v1242; CHECK-GI-NEXT: mov.d v2[1], v0[0]243; CHECK-GI-NEXT: mov.16b v0, v2244; CHECK-GI-NEXT: ret245 %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>246 %4 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>247 %5 = shufflevector <8 x i8> %3, <8 x i8> %4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>248 ret <16 x i8> %5249}250 251define <8 x i16> @combine_v8i16(<4 x i16> %0, <4 x i16> %1) {252; CHECK-LABEL: combine_v8i16:253; CHECK: // %bb.0:254; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0255; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1256; CHECK-NEXT: zip1.8h v0, v0, v1257; CHECK-NEXT: ret258 %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>259 ret <8 x i16> %3260}261 262define <8 x i16> @combine2_v8i16(<4 x i16> %0, <4 x i16> %1) {263; CHECK-SD-LABEL: combine2_v8i16:264; CHECK-SD: // %bb.0:265; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0266; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1267; CHECK-SD-NEXT: zip1.8h v0, v0, v1268; CHECK-SD-NEXT: ret269;270; CHECK-GI-LABEL: combine2_v8i16:271; CHECK-GI: // %bb.0:272; CHECK-GI-NEXT: zip1.4h v2, v0, v1273; CHECK-GI-NEXT: zip2.4h v0, v0, v1274; CHECK-GI-NEXT: mov.d v2[1], v0[0]275; CHECK-GI-NEXT: mov.16b v0, v2276; CHECK-GI-NEXT: ret277 %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>278 %4 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>279 %5 = shufflevector <4 x i16> %3, <4 x i16> %4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>280 ret <8 x i16> %5281}282 283define <4 x i32> @combine_v4i32(<2 x i32> %0, <2 x i32> %1) {284; CHECK-LABEL: combine_v4i32:285; CHECK: // %bb.0:286; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0287; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1288; CHECK-NEXT: zip1.4s v0, v0, v1289; CHECK-NEXT: ret290 %3 = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>291 ret <4 x i32> %3292}293 294define <4 x i32> @combine2_v4i32(<2 x i32> %0, <2 x i32> %1) {295; CHECK-SD-LABEL: combine2_v4i32:296; CHECK-SD: // %bb.0:297; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0298; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1299; CHECK-SD-NEXT: zip1.4s v0, v0, v1300; CHECK-SD-NEXT: ret301;302; CHECK-GI-LABEL: combine2_v4i32:303; CHECK-GI: // %bb.0:304; CHECK-GI-NEXT: zip1.2s v2, v0, v1305; CHECK-GI-NEXT: zip2.2s v0, v0, v1306; CHECK-GI-NEXT: mov.d v2[1], v0[0]307; CHECK-GI-NEXT: mov.16b v0, v2308; CHECK-GI-NEXT: ret309 %3 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 0, i32 2>310 %4 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 1, i32 3>311 %5 = shufflevector <2 x i32> %3, <2 x i32> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>312 ret <4 x i32> %5313}314 315define <16 x i8> @combine_v16i8_undef(<8 x i8> %0, <8 x i8> %1) {316; CHECK-LABEL: combine_v16i8_undef:317; CHECK: // %bb.0:318; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0319; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1320; CHECK-NEXT: zip1.16b v0, v0, v1321; CHECK-NEXT: ret322 %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>323 ret <16 x i8> %3324}325 326define <16 x i8> @combine2_v16i8_undef(<8 x i8> %0, <8 x i8> %1) {327; CHECK-SD-LABEL: combine2_v16i8_undef:328; CHECK-SD: // %bb.0:329; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0330; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1331; CHECK-SD-NEXT: zip1.16b v0, v0, v1332; CHECK-SD-NEXT: ret333;334; CHECK-GI-LABEL: combine2_v16i8_undef:335; CHECK-GI: // %bb.0:336; CHECK-GI-NEXT: zip1.8b v2, v0, v1337; CHECK-GI-NEXT: zip2.8b v0, v0, v1338; CHECK-GI-NEXT: mov.d v2[1], v0[0]339; CHECK-GI-NEXT: mov.16b v0, v2340; CHECK-GI-NEXT: ret341 %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>342 %4 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>343 %5 = shufflevector <8 x i8> %3, <8 x i8> %4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>344 ret <16 x i8> %5345}346 347define <8 x i16> @combine_v8i16_undef(<4 x i16> %0, <4 x i16> %1) {348; CHECK-LABEL: combine_v8i16_undef:349; CHECK: // %bb.0:350; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0351; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1352; CHECK-NEXT: zip1.8h v0, v0, v1353; CHECK-NEXT: ret354 %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 undef, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>355 ret <8 x i16> %3356}357 358define <16 x i8> @combine_v8i16_8first(<8 x i8> %0, <8 x i8> %1) {359; CHECK-LABEL: combine_v8i16_8first:360; CHECK: // %bb.0:361; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0362; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1363; CHECK-NEXT: zip1.16b v0, v0, v1364; CHECK-NEXT: ret365 %3 = shufflevector <8 x i8> %1, <8 x i8> %0, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>366 ret <16 x i8> %3367}368 369 370define <16 x i8> @combine_v8i16_8firstundef(<8 x i8> %0, <8 x i8> %1) {371; CHECK-LABEL: combine_v8i16_8firstundef:372; CHECK: // %bb.0:373; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0374; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1375; CHECK-NEXT: zip1.16b v0, v0, v1376; CHECK-NEXT: ret377 %3 = shufflevector <8 x i8> %1, <8 x i8> %0, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 undef>378 ret <16 x i8> %3379}380 381define <4 x float> @shuffle_zip1(<4 x float> %arg) {382; CHECK-LABEL: shuffle_zip1:383; CHECK: // %bb.0: // %bb384; CHECK-NEXT: fcmgt.4s v0, v0, #0.0385; CHECK-NEXT: uzp1.8h v1, v0, v0386; CHECK-NEXT: xtn.4h v0, v0387; CHECK-NEXT: xtn.4h v1, v1388; CHECK-NEXT: zip2.4h v0, v0, v1389; CHECK-NEXT: fmov.4s v1, #1.00000000390; CHECK-NEXT: zip1.4h v0, v0, v0391; CHECK-NEXT: sshll.4s v0, v0, #0392; CHECK-NEXT: and.16b v0, v0, v1393; CHECK-NEXT: ret394bb:395 %inst = fcmp olt <4 x float> zeroinitializer, %arg396 %inst1 = shufflevector <4 x i1> %inst, <4 x i1> zeroinitializer, <2 x i32> <i32 2, i32 0>397 %inst2 = shufflevector <2 x i1> %inst1, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1>398 %inst3 = select <4 x i1> %inst2, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> zeroinitializer399 ret <4 x float> %inst3400}401 402define <4 x i32> @shuffle_zip2(<4 x i32> %arg) {403; CHECK-LABEL: shuffle_zip2:404; CHECK: // %bb.0: // %bb405; CHECK-NEXT: cmtst.4s v0, v0, v0406; CHECK-NEXT: uzp1.8h v1, v0, v0407; CHECK-NEXT: xtn.4h v0, v0408; CHECK-NEXT: xtn.4h v1, v1409; CHECK-NEXT: zip2.4h v0, v0, v1410; CHECK-NEXT: movi.4s v1, #1411; CHECK-NEXT: zip1.4h v0, v0, v0412; CHECK-NEXT: ushll.4s v0, v0, #0413; CHECK-NEXT: and.16b v0, v0, v1414; CHECK-NEXT: ret415bb:416 %inst = icmp ult <4 x i32> zeroinitializer, %arg417 %inst1 = shufflevector <4 x i1> %inst, <4 x i1> zeroinitializer, <2 x i32> <i32 2, i32 0>418 %inst2 = shufflevector <2 x i1> %inst1, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1>419 %inst3 = select <4 x i1> %inst2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> zeroinitializer420 ret <4 x i32> %inst3421}422 423define <4 x i32> @shuffle_zip3(<4 x i32> %arg) {424; CHECK-LABEL: shuffle_zip3:425; CHECK: // %bb.0: // %bb426; CHECK-NEXT: cmgt.4s v0, v0, #0427; CHECK-NEXT: uzp1.8h v1, v0, v0428; CHECK-NEXT: xtn.4h v0, v0429; CHECK-NEXT: xtn.4h v1, v1430; CHECK-NEXT: zip2.4h v0, v0, v1431; CHECK-NEXT: movi.4s v1, #1432; CHECK-NEXT: zip1.4h v0, v0, v0433; CHECK-NEXT: ushll.4s v0, v0, #0434; CHECK-NEXT: and.16b v0, v0, v1435; CHECK-NEXT: ret436bb:437 %inst = icmp slt <4 x i32> zeroinitializer, %arg438 %inst1 = shufflevector <4 x i1> %inst, <4 x i1> zeroinitializer, <2 x i32> <i32 2, i32 0>439 %inst2 = shufflevector <2 x i1> %inst1, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1>440 %inst3 = select <4 x i1> %inst2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> zeroinitializer441 ret <4 x i32> %inst3442}443