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1; RUN: llc -mtriple=arm64_32-apple-ios7.0 -o - %s | FileCheck %s2; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS3 4define i8 @test_load_8(ptr %addr) {5; CHECK-LABAL: test_load_8:6; CHECK: ldarb w0, [x0]7 %val = load atomic i8, ptr %addr seq_cst, align 18 ret i8 %val9}10 11define i16 @test_load_16(ptr %addr) {12; CHECK-LABAL: test_load_16:13; CHECK: ldarh w0, [x0]14 %val = load atomic i16, ptr %addr acquire, align 215 ret i16 %val16}17 18define i32 @test_load_32(ptr %addr) {19; CHECK-LABAL: test_load_32:20; CHECK: ldar w0, [x0]21 %val = load atomic i32, ptr %addr seq_cst, align 422 ret i32 %val23}24 25define i64 @test_load_64(ptr %addr) {26; CHECK-LABAL: test_load_64:27; CHECK: ldar x0, [x0]28 %val = load atomic i64, ptr %addr seq_cst, align 829 ret i64 %val30}31 32define ptr @test_load_ptr(ptr %addr) {33; CHECK-LABAL: test_load_ptr:34; CHECK: ldar w0, [x0]35 %val = load atomic ptr, ptr %addr seq_cst, align 836 ret ptr %val37}38 39define void @test_store_8(ptr %addr) {40; CHECK-LABAL: test_store_8:41; CHECK: stlrb wzr, [x0]42 store atomic i8 0, ptr %addr seq_cst, align 143 ret void44}45 46define void @test_store_16(ptr %addr) {47; CHECK-LABAL: test_store_16:48; CHECK: stlrh wzr, [x0]49 store atomic i16 0, ptr %addr seq_cst, align 250 ret void51}52 53define void @test_store_32(ptr %addr) {54; CHECK-LABAL: test_store_32:55; CHECK: stlr wzr, [x0]56 store atomic i32 0, ptr %addr seq_cst, align 457 ret void58}59 60define void @test_store_64(ptr %addr) {61; CHECK-LABAL: test_store_64:62; CHECK: stlr xzr, [x0]63 store atomic i64 0, ptr %addr seq_cst, align 864 ret void65}66 67define void @test_store_ptr(ptr %addr) {68; CHECK-LABAL: test_store_ptr:69; CHECK: stlr wzr, [x0]70 store atomic ptr null, ptr %addr seq_cst, align 871 ret void72}73 74declare i64 @llvm.aarch64.ldxr.p0(ptr %addr)75 76define i8 @test_ldxr_8(ptr %addr) {77; CHECK-LABEL: test_ldxr_8:78; CHECK: ldxrb w0, [x0]79 80 %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i8) %addr)81 %val8 = trunc i64 %val to i882 ret i8 %val883}84 85define i16 @test_ldxr_16(ptr %addr) {86; CHECK-LABEL: test_ldxr_16:87; CHECK: ldxrh w0, [x0]88 89 %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i16) %addr)90 %val16 = trunc i64 %val to i1691 ret i16 %val1692}93 94define i32 @test_ldxr_32(ptr %addr) {95; CHECK-LABEL: test_ldxr_32:96; CHECK: ldxr w0, [x0]97 98 %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)99 %val32 = trunc i64 %val to i32100 ret i32 %val32101}102 103define i64 @test_ldxr_64(ptr %addr) {104; CHECK-LABEL: test_ldxr_64:105; CHECK: ldxr x0, [x0]106 107 %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i64) %addr)108 ret i64 %val109}110 111declare i64 @llvm.aarch64.ldaxr.p0(ptr %addr)112 113define i8 @test_ldaxr_8(ptr %addr) {114; CHECK-LABEL: test_ldaxr_8:115; CHECK: ldaxrb w0, [x0]116 117 %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i8) %addr)118 %val8 = trunc i64 %val to i8119 ret i8 %val8120}121 122define i16 @test_ldaxr_16(ptr %addr) {123; CHECK-LABEL: test_ldaxr_16:124; CHECK: ldaxrh w0, [x0]125 126 %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) %addr)127 %val16 = trunc i64 %val to i16128 ret i16 %val16129}130 131define i32 @test_ldaxr_32(ptr %addr) {132; CHECK-LABEL: test_ldaxr_32:133; CHECK: ldaxr w0, [x0]134 135 %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) %addr)136 %val32 = trunc i64 %val to i32137 ret i32 %val32138}139 140define i64 @test_ldaxr_64(ptr %addr) {141; CHECK-LABEL: test_ldaxr_64:142; CHECK: ldaxr x0, [x0]143 144 %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i64) %addr)145 ret i64 %val146}147 148declare i32 @llvm.aarch64.stxr.p0(i64, ptr)149 150define i32 @test_stxr_8(ptr %addr, i8 %val) {151; CHECK-LABEL: test_stxr_8:152; CHECK: stxrb [[TMP:w[0-9]+]], w1, [x0]153; CHECK: mov w0, [[TMP]]154 155 %extval = zext i8 %val to i64156 %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i8) %addr)157 ret i32 %success158}159 160define i32 @test_stxr_16(ptr %addr, i16 %val) {161; CHECK-LABEL: test_stxr_16:162; CHECK: stxrh [[TMP:w[0-9]+]], w1, [x0]163; CHECK: mov w0, [[TMP]]164 165 %extval = zext i16 %val to i64166 %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i16) %addr)167 ret i32 %success168}169 170define i32 @test_stxr_32(ptr %addr, i32 %val) {171; CHECK-LABEL: test_stxr_32:172; CHECK: stxr [[TMP:w[0-9]+]], w1, [x0]173; CHECK: mov w0, [[TMP]]174 175 %extval = zext i32 %val to i64176 %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i32) %addr)177 ret i32 %success178}179 180define i32 @test_stxr_64(ptr %addr, i64 %val) {181; CHECK-LABEL: test_stxr_64:182; CHECK: stxr [[TMP:w[0-9]+]], x1, [x0]183; CHECK: mov w0, [[TMP]]184 185 %success = call i32 @llvm.aarch64.stxr.p0(i64 %val, ptr elementtype(i64) %addr)186 ret i32 %success187}188 189declare i32 @llvm.aarch64.stlxr.p0(i64, ptr)190 191define i32 @test_stlxr_8(ptr %addr, i8 %val) {192; CHECK-LABEL: test_stlxr_8:193; CHECK: stlxrb [[TMP:w[0-9]+]], w1, [x0]194; CHECK: mov w0, [[TMP]]195 196 %extval = zext i8 %val to i64197 %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i8) %addr)198 ret i32 %success199}200 201define i32 @test_stlxr_16(ptr %addr, i16 %val) {202; CHECK-LABEL: test_stlxr_16:203; CHECK: stlxrh [[TMP:w[0-9]+]], w1, [x0]204; CHECK: mov w0, [[TMP]]205 206 %extval = zext i16 %val to i64207 %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i16) %addr)208 ret i32 %success209}210 211define i32 @test_stlxr_32(ptr %addr, i32 %val) {212; CHECK-LABEL: test_stlxr_32:213; CHECK: stlxr [[TMP:w[0-9]+]], w1, [x0]214; CHECK: mov w0, [[TMP]]215 216 %extval = zext i32 %val to i64217 %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i32) %addr)218 ret i32 %success219}220 221define i32 @test_stlxr_64(ptr %addr, i64 %val) {222; CHECK-LABEL: test_stlxr_64:223; CHECK: stlxr [[TMP:w[0-9]+]], x1, [x0]224; CHECK: mov w0, [[TMP]]225 226 %success = call i32 @llvm.aarch64.stlxr.p0(i64 %val, ptr elementtype(i64) %addr)227 ret i32 %success228}229 230define {ptr, i1} @test_cmpxchg_ptr(ptr %addr, ptr %cmp, ptr %new) {231; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel232; CHECK-LABEL: test_cmpxchg_ptr:233; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:234; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]235; CHECK: cmp [[OLD]], w1236; CHECK: b.ne [[DONE:LBB[0-9]+_[0-9]+]]237; CHECK: stlxr [[SUCCESS:w[0-9]+]], w2, [x0]238; CHECK: cbnz [[SUCCESS]], [[LOOP]]239 240; CHECK: mov w1, #1241; CHECK: mov w0, [[OLD]]242; CHECK: ret243 244; CHECK: [[DONE]]:245; CHECK: mov w1, wzr246; CHECK: mov w0, [[OLD]]247; CHECK: clrex248; CHECK: ret249 %res = cmpxchg ptr %addr, ptr %cmp, ptr %new acq_rel acquire250 ret {ptr, i1} %res251}252