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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mcpu=cyclone %s -o - | FileCheck %s3 4define <2 x double> @test_insert_elt(<2 x double> %vec, double %val) {5; CHECK-LABEL: test_insert_elt:6; CHECK: ; %bb.0:7; CHECK-NEXT: ; kill: def $d1 killed $d1 def $q18; CHECK-NEXT: mov.d v0[0], v1[0]9; CHECK-NEXT: ret10 %res = insertelement <2 x double> %vec, double %val, i32 011 ret <2 x double> %res12}13 14define void @test_split_16B(<4 x float> %val, ptr %addr) {15; CHECK-LABEL: test_split_16B:16; CHECK: ; %bb.0:17; CHECK-NEXT: str q0, [x0]18; CHECK-NEXT: ret19 store <4 x float> %val, ptr %addr, align 820 ret void21}22 23define void @test_split_16B_splat(<4 x i32>, ptr %addr) {24; CHECK-LABEL: test_split_16B_splat:25; CHECK: ; %bb.0:26; CHECK-NEXT: movi.4s v0, #4227; CHECK-NEXT: str q0, [x0]28; CHECK-NEXT: ret29 %vec.tmp0 = insertelement <4 x i32> undef, i32 42, i32 030 %vec.tmp1 = insertelement <4 x i32> %vec.tmp0, i32 42, i32 131 %vec.tmp2 = insertelement <4 x i32> %vec.tmp1, i32 42, i32 232 %vec = insertelement <4 x i32> %vec.tmp2, i32 42, i32 333 store <4 x i32> %vec, ptr %addr, align 834 ret void35}36 37 38%vec = type <2 x double>39 40declare {%vec, %vec} @llvm.aarch64.neon.ld2r.v2f64.p0(ptr)41define {%vec, %vec} @test_neon_load(ptr %addr) {42; CHECK-LABEL: test_neon_load:43; CHECK: ; %bb.0:44; CHECK-NEXT: ld2r.2d { v0, v1 }, [x0]45; CHECK-NEXT: ret46 %res = call {%vec, %vec} @llvm.aarch64.neon.ld2r.v2f64.p0(ptr %addr)47 ret {%vec, %vec} %res48}49 50declare {%vec, %vec} @llvm.aarch64.neon.ld2lane.v2f64.p0(%vec, %vec, i64, ptr)51define {%vec, %vec} @test_neon_load_lane(ptr %addr, %vec %in1, %vec %in2) {52; CHECK-LABEL: test_neon_load_lane:53; CHECK: ; %bb.0:54; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q155; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q156; CHECK-NEXT: ld2.d { v0, v1 }[0], [x0]57; CHECK-NEXT: ret58 %res = call {%vec, %vec} @llvm.aarch64.neon.ld2lane.v2f64.p0(%vec %in1, %vec %in2, i64 0, ptr %addr)59 ret {%vec, %vec} %res60}61 62declare void @llvm.aarch64.neon.st2.v2f64.p0(%vec, %vec, ptr)63define void @test_neon_store(ptr %addr, %vec %in1, %vec %in2) {64; CHECK-LABEL: test_neon_store:65; CHECK: ; %bb.0:66; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q167; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q168; CHECK-NEXT: st2.2d { v0, v1 }, [x0]69; CHECK-NEXT: ret70 call void @llvm.aarch64.neon.st2.v2f64.p0(%vec %in1, %vec %in2, ptr %addr)71 ret void72}73 74declare void @llvm.aarch64.neon.st2lane.v2f64.p0(%vec, %vec, i64, ptr)75define void @test_neon_store_lane(ptr %addr, %vec %in1, %vec %in2) {76; CHECK-LABEL: test_neon_store_lane:77; CHECK: ; %bb.0:78; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q179; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q180; CHECK-NEXT: st2.d { v0, v1 }[1], [x0]81; CHECK-NEXT: ret82 call void @llvm.aarch64.neon.st2lane.v2f64.p0(%vec %in1, %vec %in2, i64 1, ptr %addr)83 ret void84}85 86declare {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0(ptr)87define {{%vec, %vec}, ptr} @test_neon_load_post(ptr %addr, i32 %offset) {88; CHECK-LABEL: test_neon_load_post:89; CHECK: ; %bb.0:90; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x191; CHECK-NEXT: sxtw x8, w192; CHECK-NEXT: ld2.2d { v0, v1 }, [x0], x893; CHECK-NEXT: ret94 %vecs = call {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0(ptr %addr)95 %addr.new = getelementptr inbounds i8, ptr %addr, i32 %offset96 %res.tmp = insertvalue {{%vec, %vec}, ptr} undef, {%vec, %vec} %vecs, 097 %res = insertvalue {{%vec, %vec}, ptr} %res.tmp, ptr %addr.new, 198 ret {{%vec, %vec}, ptr} %res99}100 101define {{%vec, %vec}, ptr} @test_neon_load_post_lane(ptr %addr, i32 %offset, %vec %in1, %vec %in2) {102; CHECK-LABEL: test_neon_load_post_lane:103; CHECK: ; %bb.0:104; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1105; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1106; CHECK-NEXT: sxtw x8, w1107; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1108; CHECK-NEXT: ld2.d { v0, v1 }[1], [x0], x8109; CHECK-NEXT: ret110 %vecs = call {%vec, %vec} @llvm.aarch64.neon.ld2lane.v2f64.p0(%vec %in1, %vec %in2, i64 1, ptr %addr)111 %addr.new = getelementptr inbounds i8, ptr %addr, i32 %offset112 %res.tmp = insertvalue {{%vec, %vec}, ptr} undef, {%vec, %vec} %vecs, 0113 %res = insertvalue {{%vec, %vec}, ptr} %res.tmp, ptr %addr.new, 1114 ret {{%vec, %vec}, ptr} %res115}116 117define ptr @test_neon_store_post(ptr %addr, i32 %offset, %vec %in1, %vec %in2) {118; CHECK-LABEL: test_neon_store_post:119; CHECK: ; %bb.0:120; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1121; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1122; CHECK-NEXT: sxtw x8, w1123; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1124; CHECK-NEXT: st2.2d { v0, v1 }, [x0], x8125; CHECK-NEXT: ret126 call void @llvm.aarch64.neon.st2.v2f64.p0(%vec %in1, %vec %in2, ptr %addr)127 %addr.new = getelementptr inbounds i8, ptr %addr, i32 %offset128 ret ptr %addr.new129}130 131define ptr @test_neon_store_post_lane(ptr %addr, i32 %offset, %vec %in1, %vec %in2) {132; CHECK-LABEL: test_neon_store_post_lane:133; CHECK: ; %bb.0:134; CHECK-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1135; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1136; CHECK-NEXT: sxtw x8, w1137; CHECK-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1138; CHECK-NEXT: st2.d { v0, v1 }[0], [x0], x8139; CHECK-NEXT: ret140 call void @llvm.aarch64.neon.st2lane.v2f64.p0(%vec %in1, %vec %in2, i64 0, ptr %addr)141 %addr.new = getelementptr inbounds i8, ptr %addr, i32 %offset142 ret ptr %addr.new143}144 145; ld1 is slightly different because it goes via ISelLowering of normal IR ops146; rather than an intrinsic.147define {%vec, ptr} @test_neon_ld1_post_lane(ptr %addr, i32 %offset, %vec %in) {148; CHECK-LABEL: test_neon_ld1_post_lane:149; CHECK: ; %bb.0:150; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1151; CHECK-NEXT: sbfiz x8, x1, #3, #32152; CHECK-NEXT: ld1.d { v0 }[0], [x0], x8153; CHECK-NEXT: ret154 %loaded = load double, ptr %addr, align 8155 %newvec = insertelement %vec %in, double %loaded, i32 0156 %addr.new = getelementptr inbounds double, ptr %addr, i32 %offset157 %res.tmp = insertvalue {%vec, ptr} undef, %vec %newvec, 0158 %res = insertvalue {%vec, ptr} %res.tmp, ptr %addr.new, 1159 ret {%vec, ptr} %res160}161 162define {{%vec, %vec}, ptr} @test_neon_load_post_exact(ptr %addr) {163; CHECK-LABEL: test_neon_load_post_exact:164; CHECK: ; %bb.0:165; CHECK-NEXT: ld2.2d { v0, v1 }, [x0], #32166; CHECK-NEXT: ret167 %vecs = call {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0(ptr %addr)168 %addr.new = getelementptr inbounds i8, ptr %addr, i32 32169 %res.tmp = insertvalue {{%vec, %vec}, ptr} undef, {%vec, %vec} %vecs, 0170 %res = insertvalue {{%vec, %vec}, ptr} %res.tmp, ptr %addr.new, 1171 ret {{%vec, %vec}, ptr} %res172}173 174define {%vec, ptr} @test_neon_ld1_post_lane_exact(ptr %addr, %vec %in) {175; CHECK-LABEL: test_neon_ld1_post_lane_exact:176; CHECK: ; %bb.0:177; CHECK-NEXT: ld1.d { v0 }[0], [x0], #8178; CHECK-NEXT: ret179 %loaded = load double, ptr %addr, align 8180 %newvec = insertelement %vec %in, double %loaded, i32 0181 %addr.new = getelementptr inbounds double, ptr %addr, i32 1182 %res.tmp = insertvalue {%vec, ptr} undef, %vec %newvec, 0183 %res = insertvalue {%vec, ptr} %res.tmp, ptr %addr.new, 1184 ret {%vec, ptr} %res185}186 187; As in the general load/store case, this GEP has defined semantics when the188; address wraps. We cannot use post-indexed addressing.189define {%vec, ptr} @test_neon_ld1_notpost_lane_exact(ptr %addr, %vec %in) {190; CHECK-LABEL: test_neon_ld1_notpost_lane_exact:191; CHECK: ; %bb.0:192; CHECK-NEXT: ld1.d { v0 }[0], [x0]193; CHECK-NEXT: add w0, w0, #8194; CHECK-NEXT: ret195 %loaded = load double, ptr %addr, align 8196 %newvec = insertelement %vec %in, double %loaded, i32 0197 %addr.new = getelementptr double, ptr %addr, i32 1198 %res.tmp = insertvalue {%vec, ptr} undef, %vec %newvec, 0199 %res = insertvalue {%vec, ptr} %res.tmp, ptr %addr.new, 1200 ret {%vec, ptr} %res201}202 203define {%vec, ptr} @test_neon_ld1_notpost_lane(ptr %addr, i32 %offset, %vec %in) {204; CHECK-LABEL: test_neon_ld1_notpost_lane:205; CHECK: ; %bb.0:206; CHECK-NEXT: ld1.d { v0 }[0], [x0]207; CHECK-NEXT: add w0, w0, w1, lsl #3208; CHECK-NEXT: ret209 %loaded = load double, ptr %addr, align 8210 %newvec = insertelement %vec %in, double %loaded, i32 0211 %addr.new = getelementptr double, ptr %addr, i32 %offset212 %res.tmp = insertvalue {%vec, ptr} undef, %vec %newvec, 0213 %res = insertvalue {%vec, ptr} %res.tmp, ptr %addr.new, 1214 ret {%vec, ptr} %res215}216