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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 < %s | FileCheck %s3 4define <16 x i16> @zext_avgflooru(<16 x i8> %a0, <16 x i8> %a1) {5; CHECK-LABEL: zext_avgflooru:6; CHECK: // %bb.0:7; CHECK-NEXT: uhadd v0.16b, v0.16b, v1.16b8; CHECK-NEXT: ushll2 v1.8h, v0.16b, #09; CHECK-NEXT: ushll v0.8h, v0.8b, #010; CHECK-NEXT: ret11 %x0 = zext <16 x i8> %a0 to <16 x i16>12 %x1 = zext <16 x i8> %a1 to <16 x i16>13 %and = and <16 x i16> %x0, %x114 %xor = xor <16 x i16> %x0, %x115 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>16 %avg = add <16 x i16> %and, %shift17 ret <16 x i16> %avg18}19 20define <16 x i16> @zext_avgflooru_mismatch(<16 x i8> %a0, <16 x i4> %a1) {21; CHECK-LABEL: zext_avgflooru_mismatch:22; CHECK: // %bb.0:23; CHECK-NEXT: movi v2.16b, #1524; CHECK-NEXT: and v1.16b, v1.16b, v2.16b25; CHECK-NEXT: uhadd v0.16b, v0.16b, v1.16b26; CHECK-NEXT: ushll2 v1.8h, v0.16b, #027; CHECK-NEXT: ushll v0.8h, v0.8b, #028; CHECK-NEXT: ret29 %x0 = zext <16 x i8> %a0 to <16 x i16>30 %x1 = zext <16 x i4> %a1 to <16 x i16>31 %and = and <16 x i16> %x0, %x132 %xor = xor <16 x i16> %x0, %x133 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>34 %avg = add <16 x i16> %and, %shift35 ret <16 x i16> %avg36}37 38define <16 x i16> @zext_avgceilu(<16 x i8> %a0, <16 x i8> %a1) {39; CHECK-LABEL: zext_avgceilu:40; CHECK: // %bb.0:41; CHECK-NEXT: urhadd v0.16b, v0.16b, v1.16b42; CHECK-NEXT: ushll2 v1.8h, v0.16b, #043; CHECK-NEXT: ushll v0.8h, v0.8b, #044; CHECK-NEXT: ret45 %x0 = zext <16 x i8> %a0 to <16 x i16>46 %x1 = zext <16 x i8> %a1 to <16 x i16>47 %or = or <16 x i16> %x0, %x148 %xor = xor <16 x i16> %x0, %x149 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>50 %avg = sub <16 x i16> %or, %shift51 ret <16 x i16> %avg52}53 54define <16 x i16> @zext_avgceilu_mismatch(<16 x i4> %a0, <16 x i8> %a1) {55; CHECK-LABEL: zext_avgceilu_mismatch:56; CHECK: // %bb.0:57; CHECK-NEXT: movi v2.16b, #1558; CHECK-NEXT: and v0.16b, v0.16b, v2.16b59; CHECK-NEXT: urhadd v0.16b, v0.16b, v1.16b60; CHECK-NEXT: ushll2 v1.8h, v0.16b, #061; CHECK-NEXT: ushll v0.8h, v0.8b, #062; CHECK-NEXT: ret63 %x0 = zext <16 x i4> %a0 to <16 x i16>64 %x1 = zext <16 x i8> %a1 to <16 x i16>65 %or = or <16 x i16> %x0, %x166 %xor = xor <16 x i16> %x0, %x167 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>68 %avg = sub <16 x i16> %or, %shift69 ret <16 x i16> %avg70}71 72define <16 x i16> @sext_avgfloors(<16 x i8> %a0, <16 x i8> %a1) {73; CHECK-LABEL: sext_avgfloors:74; CHECK: // %bb.0:75; CHECK-NEXT: shadd v0.16b, v0.16b, v1.16b76; CHECK-NEXT: sshll2 v1.8h, v0.16b, #077; CHECK-NEXT: sshll v0.8h, v0.8b, #078; CHECK-NEXT: ret79 %x0 = sext <16 x i8> %a0 to <16 x i16>80 %x1 = sext <16 x i8> %a1 to <16 x i16>81 %and = and <16 x i16> %x0, %x182 %xor = xor <16 x i16> %x0, %x183 %shift = ashr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>84 %avg = add <16 x i16> %and, %shift85 ret <16 x i16> %avg86}87 88define <16 x i16> @sext_avgfloors_mismatch(<16 x i8> %a0, <16 x i4> %a1) {89; CHECK-LABEL: sext_avgfloors_mismatch:90; CHECK: // %bb.0:91; CHECK-NEXT: ushll2 v2.8h, v1.16b, #092; CHECK-NEXT: ushll v1.8h, v1.8b, #093; CHECK-NEXT: sshll v3.8h, v0.8b, #094; CHECK-NEXT: sshll2 v0.8h, v0.16b, #095; CHECK-NEXT: shl v1.8h, v1.8h, #1296; CHECK-NEXT: shl v2.8h, v2.8h, #1297; CHECK-NEXT: sshr v4.8h, v1.8h, #1298; CHECK-NEXT: sshr v1.8h, v2.8h, #1299; CHECK-NEXT: shadd v1.8h, v0.8h, v1.8h100; CHECK-NEXT: shadd v0.8h, v3.8h, v4.8h101; CHECK-NEXT: ret102 %x0 = sext <16 x i8> %a0 to <16 x i16>103 %x1 = sext <16 x i4> %a1 to <16 x i16>104 %and = and <16 x i16> %x0, %x1105 %xor = xor <16 x i16> %x0, %x1106 %shift = ashr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>107 %avg = add <16 x i16> %and, %shift108 ret <16 x i16> %avg109}110 111define <16 x i16> @sext_avgceils(<16 x i8> %a0, <16 x i8> %a1) {112; CHECK-LABEL: sext_avgceils:113; CHECK: // %bb.0:114; CHECK-NEXT: srhadd v0.16b, v0.16b, v1.16b115; CHECK-NEXT: sshll2 v1.8h, v0.16b, #0116; CHECK-NEXT: sshll v0.8h, v0.8b, #0117; CHECK-NEXT: ret118 %x0 = sext <16 x i8> %a0 to <16 x i16>119 %x1 = sext <16 x i8> %a1 to <16 x i16>120 %or = or <16 x i16> %x0, %x1121 %xor = xor <16 x i16> %x0, %x1122 %shift = ashr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>123 %avg = sub <16 x i16> %or, %shift124 ret <16 x i16> %avg125}126 127define <16 x i16> @sext_avgceils_mismatch(<16 x i4> %a0, <16 x i8> %a1) {128; CHECK-LABEL: sext_avgceils_mismatch:129; CHECK: // %bb.0:130; CHECK-NEXT: ushll v2.8h, v0.8b, #0131; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0132; CHECK-NEXT: sshll v3.8h, v1.8b, #0133; CHECK-NEXT: sshll2 v1.8h, v1.16b, #0134; CHECK-NEXT: shl v2.8h, v2.8h, #12135; CHECK-NEXT: shl v0.8h, v0.8h, #12136; CHECK-NEXT: sshr v2.8h, v2.8h, #12137; CHECK-NEXT: sshr v0.8h, v0.8h, #12138; CHECK-NEXT: srhadd v1.8h, v0.8h, v1.8h139; CHECK-NEXT: srhadd v0.8h, v2.8h, v3.8h140; CHECK-NEXT: ret141 %x0 = sext <16 x i4> %a0 to <16 x i16>142 %x1 = sext <16 x i8> %a1 to <16 x i16>143 %or = or <16 x i16> %x0, %x1144 %xor = xor <16 x i16> %x0, %x1145 %shift = ashr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>146 %avg = sub <16 x i16> %or, %shift147 ret <16 x i16> %avg148}149 150define <8 x i16> @add_avgflooru(<8 x i16> %a0, <8 x i16> %a1) {151; CHECK-LABEL: add_avgflooru:152; CHECK: // %bb.0:153; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h154; CHECK-NEXT: ret155 %add = add nuw <8 x i16> %a0, %a1156 %avg = lshr <8 x i16> %add, splat(i16 1)157 ret <8 x i16> %avg158}159 160define <8 x i16> @add_avgflooru_mismatch(<8 x i16> %a0, <8 x i16> %a1) {161; CHECK-LABEL: add_avgflooru_mismatch:162; CHECK: // %bb.0:163; CHECK-NEXT: add v0.8h, v0.8h, v1.8h164; CHECK-NEXT: ushr v0.8h, v0.8h, #1165; CHECK-NEXT: ret166 %add = add <8 x i16> %a0, %a1167 %avg = lshr <8 x i16> %add, splat(i16 1)168 ret <8 x i16> %avg169}170 171define <8 x i16> @add_avgceilu(<8 x i16> %a0, <8 x i16> %a1) {172; CHECK-LABEL: add_avgceilu:173; CHECK: // %bb.0:174; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h175; CHECK-NEXT: ret176 %add0 = add nuw <8 x i16> %a0, splat(i16 1)177 %add = add nuw <8 x i16> %a1, %add0178 %avg = lshr <8 x i16> %add, splat(i16 1)179 ret <8 x i16> %avg180}181 182define <8 x i16> @add_avgceilu2(<8 x i16> %a0, <8 x i16> %a1) {183; CHECK-LABEL: add_avgceilu2:184; CHECK: // %bb.0:185; CHECK-NEXT: urhadd v0.8h, v1.8h, v0.8h186; CHECK-NEXT: ret187 %add0 = add nuw <8 x i16> %a1, %a0188 %add = add nuw <8 x i16> %add0, splat(i16 1)189 %avg = lshr <8 x i16> %add, splat(i16 1)190 ret <8 x i16> %avg191}192 193define <8 x i16> @add_avgceilu_mismatch1(<8 x i16> %a0, <8 x i16> %a1) {194; CHECK-LABEL: add_avgceilu_mismatch1:195; CHECK: // %bb.0:196; CHECK-NEXT: movi v2.8h, #1197; CHECK-NEXT: add v0.8h, v1.8h, v0.8h198; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h199; CHECK-NEXT: ret200 %add0 = add <8 x i16> %a1, %a0201 %add = add nuw <8 x i16> %add0, splat(i16 1)202 %avg = lshr <8 x i16> %add, splat(i16 1)203 ret <8 x i16> %avg204}205 206define <8 x i16> @add_avgceilu_mismatch2(<8 x i16> %a0, <8 x i16> %a1) {207; CHECK-LABEL: add_avgceilu_mismatch2:208; CHECK: // %bb.0:209; CHECK-NEXT: mvn v1.16b, v1.16b210; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h211; CHECK-NEXT: ushr v0.8h, v0.8h, #1212; CHECK-NEXT: ret213 %add0 = add nuw <8 x i16> %a1, %a0214 %add = add <8 x i16> %add0, splat(i16 1)215 %avg = lshr <8 x i16> %add, splat(i16 1)216 ret <8 x i16> %avg217}218 219define <8 x i16> @add_avgceilu_mismatch3(<8 x i16> %a0, <8 x i16> %a1) {220; CHECK-LABEL: add_avgceilu_mismatch3:221; CHECK: // %bb.0:222; CHECK-NEXT: mvn v1.16b, v1.16b223; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h224; CHECK-NEXT: ushr v0.8h, v0.8h, #1225; CHECK-NEXT: ret226 %add0 = add nuw <8 x i16> %a1, %a0227 %add = add <8 x i16> %add0, splat(i16 1)228 %avg = lshr <8 x i16> %add, splat(i16 1)229 ret <8 x i16> %avg230}231 232define <8 x i16> @add_avgfloors(<8 x i16> %a0, <8 x i16> %a1) {233; CHECK-LABEL: add_avgfloors:234; CHECK: // %bb.0:235; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h236; CHECK-NEXT: ret237 %add = add nsw <8 x i16> %a0, %a1238 %avg = ashr <8 x i16> %add, splat(i16 1)239 ret <8 x i16> %avg240}241 242define <8 x i16> @add_avgfloors_mismatch(<8 x i16> %a0, <8 x i16> %a1) {243; CHECK-LABEL: add_avgfloors_mismatch:244; CHECK: // %bb.0:245; CHECK-NEXT: add v0.8h, v0.8h, v1.8h246; CHECK-NEXT: sshr v0.8h, v0.8h, #1247; CHECK-NEXT: ret248 %add = add <8 x i16> %a0, %a1249 %avg = ashr <8 x i16> %add, splat(i16 1)250 ret <8 x i16> %avg251}252 253define <8 x i16> @add_avgfoor_mismatch2(<8 x i16> %a0, <8 x i16> %a1) {254; CHECK-LABEL: add_avgfoor_mismatch2:255; CHECK: // %bb.0:256; CHECK-NEXT: add v0.8h, v0.8h, v1.8h257; CHECK-NEXT: sshr v0.8h, v0.8h, #2258; CHECK-NEXT: ret259 %add = add nsw <8 x i16> %a0, %a1260 %avg = ashr <8 x i16> %add, splat(i16 2)261 ret <8 x i16> %avg262}263 264define <8 x i16> @add_avgceils(<8 x i16> %a0, <8 x i16> %a1) {265; CHECK-LABEL: add_avgceils:266; CHECK: // %bb.0:267; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h268; CHECK-NEXT: ret269 %add0 = add nsw <8 x i16> %a0, splat(i16 1)270 %add = add nsw <8 x i16> %a1, %add0271 %avg = ashr <8 x i16> %add, splat(i16 1)272 ret <8 x i16> %avg273}274 275define <8 x i16> @add_avgceils2(<8 x i16> %a0, <8 x i16> %a1) {276; CHECK-LABEL: add_avgceils2:277; CHECK: // %bb.0:278; CHECK-NEXT: srhadd v0.8h, v1.8h, v0.8h279; CHECK-NEXT: ret280 %add0 = add nsw <8 x i16> %a1, %a0281 %add = add nsw <8 x i16> %add0, splat(i16 1)282 %avg = ashr <8 x i16> %add, splat(i16 1)283 ret <8 x i16> %avg284}285 286define <8 x i16> @add_avgceils_mismatch1(<8 x i16> %a0, <8 x i16> %a1) {287; CHECK-LABEL: add_avgceils_mismatch1:288; CHECK: // %bb.0:289; CHECK-NEXT: movi v2.8h, #1290; CHECK-NEXT: add v0.8h, v1.8h, v0.8h291; CHECK-NEXT: shadd v0.8h, v0.8h, v2.8h292; CHECK-NEXT: ret293 %add0 = add <8 x i16> %a1, %a0294 %add = add nsw <8 x i16> %add0, splat(i16 1)295 %avg = ashr <8 x i16> %add, splat(i16 1)296 ret <8 x i16> %avg297}298 299define <8 x i16> @add_avgceils_mismatch2(<8 x i16> %a0, <8 x i16> %a1) {300; CHECK-LABEL: add_avgceils_mismatch2:301; CHECK: // %bb.0:302; CHECK-NEXT: mvn v1.16b, v1.16b303; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h304; CHECK-NEXT: sshr v0.8h, v0.8h, #1305; CHECK-NEXT: ret306 %add0 = add nsw <8 x i16> %a1, %a0307 %add = add <8 x i16> %add0, splat(i16 1)308 %avg = ashr <8 x i16> %add, splat(i16 1)309 ret <8 x i16> %avg310}311 312define <8 x i16> @add_avgceils_mismatch3(<8 x i16> %a0, <8 x i16> %a1) {313; CHECK-LABEL: add_avgceils_mismatch3:314; CHECK: // %bb.0:315; CHECK-NEXT: mvn v1.16b, v1.16b316; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h317; CHECK-NEXT: sshr v0.8h, v0.8h, #1318; CHECK-NEXT: ret319 %add0 = add nsw <8 x i16> %a1, %a0320 %add = add <8 x i16> %add0, splat(i16 1)321 %avg = ashr <8 x i16> %add, splat(i16 1)322 ret <8 x i16> %avg323}324 325define <8 x i16> @add_avgceils_mismatch4(<8 x i16> %a0, <8 x i16> %a1) {326; CHECK-LABEL: add_avgceils_mismatch4:327; CHECK: // %bb.0:328; CHECK-NEXT: mvn v0.16b, v0.16b329; CHECK-NEXT: sub v0.8h, v1.8h, v0.8h330; CHECK-NEXT: sshr v0.8h, v0.8h, #2331; CHECK-NEXT: ret332 %add0 = add nsw <8 x i16> %a0, splat(i16 1)333 %add = add nsw <8 x i16> %a1, %add0334 %avg = ashr <8 x i16> %add, splat(i16 2)335 ret <8 x i16> %avg336}337 338define <8 x i16> @add_avgceilu_mismatch(<8 x i16> %a0, <8 x i16> %a1) {339; CHECK-LABEL: add_avgceilu_mismatch:340; CHECK: // %bb.0:341; CHECK-NEXT: movi v2.8h, #1342; CHECK-NEXT: add v0.8h, v1.8h, v0.8h343; CHECK-NEXT: add v0.8h, v0.8h, v2.8h344; CHECK-NEXT: ushr v0.8h, v0.8h, #2345; CHECK-NEXT: ret346 %add0 = add nuw <8 x i16> %a1, %a0347 %add = add nuw <8 x i16> %add0, splat(i16 1)348 %avg = lshr <8 x i16> %add, splat(i16 2)349 ret <8 x i16> %avg350}351