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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=-bf16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT3; RUN: llc < %s -mtriple=aarch64 -mattr=+bf16 | FileCheck %s --check-prefixes=CHECK,CHECK-BF164 5define <4 x bfloat> @add_h(<4 x bfloat> %a, <4 x bfloat> %b) {6; CHECK-CVT-LABEL: add_h:7; CHECK-CVT: // %bb.0: // %entry8; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #169; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #1610; CHECK-CVT-NEXT: fadd v0.4s, v0.4s, v1.4s11; CHECK-CVT-NEXT: movi v1.4s, #112; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #1613; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b14; CHECK-CVT-NEXT: movi v2.4s, #127, msl #815; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s16; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s17; CHECK-CVT-NEXT: ret18;19; CHECK-BF16-LABEL: add_h:20; CHECK-BF16: // %bb.0: // %entry21; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #1622; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #1623; CHECK-BF16-NEXT: fadd v0.4s, v0.4s, v1.4s24; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s25; CHECK-BF16-NEXT: ret26entry:27 28 %0 = fadd <4 x bfloat> %a, %b29 ret <4 x bfloat> %030}31 32 33define <4 x bfloat> @build_h4(<4 x bfloat> %a) {34; CHECK-LABEL: build_h4:35; CHECK: // %bb.0: // %entry36; CHECK-NEXT: mov w8, #15565 // =0x3ccd37; CHECK-NEXT: dup v0.4h, w838; CHECK-NEXT: ret39entry:40 ret <4 x bfloat> <bfloat 0xR3CCD, bfloat 0xR3CCD, bfloat 0xR3CCD, bfloat 0xR3CCD>41}42 43 44define <4 x bfloat> @sub_h(<4 x bfloat> %a, <4 x bfloat> %b) {45; CHECK-CVT-LABEL: sub_h:46; CHECK-CVT: // %bb.0: // %entry47; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #1648; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #1649; CHECK-CVT-NEXT: fsub v0.4s, v0.4s, v1.4s50; CHECK-CVT-NEXT: movi v1.4s, #151; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #1652; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b53; CHECK-CVT-NEXT: movi v2.4s, #127, msl #854; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s55; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s56; CHECK-CVT-NEXT: ret57;58; CHECK-BF16-LABEL: sub_h:59; CHECK-BF16: // %bb.0: // %entry60; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #1661; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #1662; CHECK-BF16-NEXT: fsub v0.4s, v0.4s, v1.4s63; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s64; CHECK-BF16-NEXT: ret65entry:66 67 %0 = fsub <4 x bfloat> %a, %b68 ret <4 x bfloat> %069}70 71 72define <4 x bfloat> @mul_h(<4 x bfloat> %a, <4 x bfloat> %b) {73; CHECK-CVT-LABEL: mul_h:74; CHECK-CVT: // %bb.0: // %entry75; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #1676; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #1677; CHECK-CVT-NEXT: fmul v0.4s, v0.4s, v1.4s78; CHECK-CVT-NEXT: movi v1.4s, #179; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #1680; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b81; CHECK-CVT-NEXT: movi v2.4s, #127, msl #882; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s83; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s84; CHECK-CVT-NEXT: ret85;86; CHECK-BF16-LABEL: mul_h:87; CHECK-BF16: // %bb.0: // %entry88; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #1689; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #1690; CHECK-BF16-NEXT: fmul v0.4s, v0.4s, v1.4s91; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s92; CHECK-BF16-NEXT: ret93entry:94 95 %0 = fmul <4 x bfloat> %a, %b96 ret <4 x bfloat> %097}98 99 100define <4 x bfloat> @div_h(<4 x bfloat> %a, <4 x bfloat> %b) {101; CHECK-CVT-LABEL: div_h:102; CHECK-CVT: // %bb.0: // %entry103; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16104; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16105; CHECK-CVT-NEXT: fdiv v0.4s, v0.4s, v1.4s106; CHECK-CVT-NEXT: movi v1.4s, #1107; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16108; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b109; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8110; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s111; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s112; CHECK-CVT-NEXT: ret113;114; CHECK-BF16-LABEL: div_h:115; CHECK-BF16: // %bb.0: // %entry116; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16117; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16118; CHECK-BF16-NEXT: fdiv v0.4s, v0.4s, v1.4s119; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s120; CHECK-BF16-NEXT: ret121entry:122 123 %0 = fdiv <4 x bfloat> %a, %b124 ret <4 x bfloat> %0125}126 127 128define <4 x bfloat> @load_h(ptr %a) {129; CHECK-LABEL: load_h:130; CHECK: // %bb.0: // %entry131; CHECK-NEXT: ldr d0, [x0]132; CHECK-NEXT: ret133entry:134 %0 = load <4 x bfloat>, ptr %a, align 4135 ret <4 x bfloat> %0136}137 138 139define void @store_h(ptr %a, <4 x bfloat> %b) {140; CHECK-LABEL: store_h:141; CHECK: // %bb.0: // %entry142; CHECK-NEXT: str d0, [x0]143; CHECK-NEXT: ret144entry:145 store <4 x bfloat> %b, ptr %a, align 4146 ret void147}148 149define <4 x bfloat> @s_to_h(<4 x float> %a) {150; CHECK-CVT-LABEL: s_to_h:151; CHECK-CVT: // %bb.0:152; CHECK-CVT-NEXT: movi v1.4s, #1153; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8154; CHECK-CVT-NEXT: ushr v3.4s, v0.4s, #16155; CHECK-CVT-NEXT: and v1.16b, v3.16b, v1.16b156; CHECK-CVT-NEXT: add v2.4s, v0.4s, v2.4s157; CHECK-CVT-NEXT: fcmeq v3.4s, v0.4s, v0.4s158; CHECK-CVT-NEXT: orr v0.4s, #64, lsl #16159; CHECK-CVT-NEXT: add v1.4s, v1.4s, v2.4s160; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v3.16b161; CHECK-CVT-NEXT: shrn v0.4h, v0.4s, #16162; CHECK-CVT-NEXT: ret163;164; CHECK-BF16-LABEL: s_to_h:165; CHECK-BF16: // %bb.0:166; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s167; CHECK-BF16-NEXT: ret168 %1 = fptrunc <4 x float> %a to <4 x bfloat>169 ret <4 x bfloat> %1170}171 172define <4 x bfloat> @d_to_h(<4 x double> %a) {173; CHECK-CVT-LABEL: d_to_h:174; CHECK-CVT: // %bb.0:175; CHECK-CVT-NEXT: fcvtxn v0.2s, v0.2d176; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8177; CHECK-CVT-NEXT: fcvtxn2 v0.4s, v1.2d178; CHECK-CVT-NEXT: movi v1.4s, #1179; CHECK-CVT-NEXT: ushr v3.4s, v0.4s, #16180; CHECK-CVT-NEXT: add v2.4s, v0.4s, v2.4s181; CHECK-CVT-NEXT: and v1.16b, v3.16b, v1.16b182; CHECK-CVT-NEXT: fcmeq v3.4s, v0.4s, v0.4s183; CHECK-CVT-NEXT: orr v0.4s, #64, lsl #16184; CHECK-CVT-NEXT: add v1.4s, v1.4s, v2.4s185; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v3.16b186; CHECK-CVT-NEXT: shrn v0.4h, v0.4s, #16187; CHECK-CVT-NEXT: ret188;189; CHECK-BF16-LABEL: d_to_h:190; CHECK-BF16: // %bb.0:191; CHECK-BF16-NEXT: fcvtxn v0.2s, v0.2d192; CHECK-BF16-NEXT: fcvtxn2 v0.4s, v1.2d193; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s194; CHECK-BF16-NEXT: ret195 %1 = fptrunc <4 x double> %a to <4 x bfloat>196 ret <4 x bfloat> %1197}198 199define <4 x float> @h_to_s(<4 x bfloat> %a) {200; CHECK-LABEL: h_to_s:201; CHECK: // %bb.0:202; CHECK-NEXT: shll v0.4s, v0.4h, #16203; CHECK-NEXT: ret204 %1 = fpext <4 x bfloat> %a to <4 x float>205 ret <4 x float> %1206}207 208define <4 x double> @h_to_d(<4 x bfloat> %a) {209; CHECK-LABEL: h_to_d:210; CHECK: // %bb.0:211; CHECK-NEXT: shll v0.4s, v0.4h, #16212; CHECK-NEXT: fcvtl2 v1.2d, v0.4s213; CHECK-NEXT: fcvtl v0.2d, v0.2s214; CHECK-NEXT: ret215 %1 = fpext <4 x bfloat> %a to <4 x double>216 ret <4 x double> %1217}218 219define <4 x bfloat> @bitcast_i_to_h(float, <4 x i16> %a) {220; CHECK-LABEL: bitcast_i_to_h:221; CHECK: // %bb.0:222; CHECK-NEXT: fmov d0, d1223; CHECK-NEXT: ret224 %2 = bitcast <4 x i16> %a to <4 x bfloat>225 ret <4 x bfloat> %2226}227 228define <4 x i16> @bitcast_h_to_i(float, <4 x bfloat> %a) {229; CHECK-LABEL: bitcast_h_to_i:230; CHECK: // %bb.0:231; CHECK-NEXT: fmov d0, d1232; CHECK-NEXT: ret233 %2 = bitcast <4 x bfloat> %a to <4 x i16>234 ret <4 x i16> %2235}236 237define <4 x bfloat> @sitofp_i8(<4 x i8> %a) #0 {238; CHECK-CVT-LABEL: sitofp_i8:239; CHECK-CVT: // %bb.0:240; CHECK-CVT-NEXT: shl v0.4h, v0.4h, #8241; CHECK-CVT-NEXT: movi v1.4s, #1242; CHECK-CVT-NEXT: sshr v0.4h, v0.4h, #8243; CHECK-CVT-NEXT: sshll v0.4s, v0.4h, #0244; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s245; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16246; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b247; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8248; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s249; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s250; CHECK-CVT-NEXT: ret251;252; CHECK-BF16-LABEL: sitofp_i8:253; CHECK-BF16: // %bb.0:254; CHECK-BF16-NEXT: shl v0.4h, v0.4h, #8255; CHECK-BF16-NEXT: sshr v0.4h, v0.4h, #8256; CHECK-BF16-NEXT: sshll v0.4s, v0.4h, #0257; CHECK-BF16-NEXT: scvtf v0.4s, v0.4s258; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s259; CHECK-BF16-NEXT: ret260 %1 = sitofp <4 x i8> %a to <4 x bfloat>261 ret <4 x bfloat> %1262}263 264define <4 x bfloat> @sitofp_i16(<4 x i16> %a) #0 {265; CHECK-CVT-LABEL: sitofp_i16:266; CHECK-CVT: // %bb.0:267; CHECK-CVT-NEXT: sshll v0.4s, v0.4h, #0268; CHECK-CVT-NEXT: movi v1.4s, #1269; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s270; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16271; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b272; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8273; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s274; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s275; CHECK-CVT-NEXT: ret276;277; CHECK-BF16-LABEL: sitofp_i16:278; CHECK-BF16: // %bb.0:279; CHECK-BF16-NEXT: sshll v0.4s, v0.4h, #0280; CHECK-BF16-NEXT: scvtf v0.4s, v0.4s281; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s282; CHECK-BF16-NEXT: ret283 %1 = sitofp <4 x i16> %a to <4 x bfloat>284 ret <4 x bfloat> %1285}286 287 288define <4 x bfloat> @sitofp_i32(<4 x i32> %a) #0 {289; CHECK-CVT-LABEL: sitofp_i32:290; CHECK-CVT: // %bb.0:291; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s292; CHECK-CVT-NEXT: movi v1.4s, #1293; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16294; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b295; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8296; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s297; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s298; CHECK-CVT-NEXT: ret299;300; CHECK-BF16-LABEL: sitofp_i32:301; CHECK-BF16: // %bb.0:302; CHECK-BF16-NEXT: scvtf v0.4s, v0.4s303; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s304; CHECK-BF16-NEXT: ret305 %1 = sitofp <4 x i32> %a to <4 x bfloat>306 ret <4 x bfloat> %1307}308 309 310define <4 x bfloat> @sitofp_i64(<4 x i64> %a) #0 {311; CHECK-CVT-LABEL: sitofp_i64:312; CHECK-CVT: // %bb.0:313; CHECK-CVT-NEXT: mov x8, v0.d[1]314; CHECK-CVT-NEXT: fmov x9, d0315; CHECK-CVT-NEXT: scvtf s2, x9316; CHECK-CVT-NEXT: mov x9, v1.d[1]317; CHECK-CVT-NEXT: scvtf s0, x8318; CHECK-CVT-NEXT: fmov x8, d1319; CHECK-CVT-NEXT: scvtf s1, x8320; CHECK-CVT-NEXT: mov v2.s[1], v0.s[0]321; CHECK-CVT-NEXT: scvtf s0, x9322; CHECK-CVT-NEXT: mov v2.s[2], v1.s[0]323; CHECK-CVT-NEXT: movi v1.4s, #127, msl #8324; CHECK-CVT-NEXT: mov v2.s[3], v0.s[0]325; CHECK-CVT-NEXT: movi v0.4s, #1326; CHECK-CVT-NEXT: ushr v3.4s, v2.4s, #16327; CHECK-CVT-NEXT: add v1.4s, v2.4s, v1.4s328; CHECK-CVT-NEXT: and v0.16b, v3.16b, v0.16b329; CHECK-CVT-NEXT: fcmeq v3.4s, v2.4s, v2.4s330; CHECK-CVT-NEXT: orr v2.4s, #64, lsl #16331; CHECK-CVT-NEXT: add v0.4s, v0.4s, v1.4s332; CHECK-CVT-NEXT: bif v0.16b, v2.16b, v3.16b333; CHECK-CVT-NEXT: shrn v0.4h, v0.4s, #16334; CHECK-CVT-NEXT: ret335;336; CHECK-BF16-LABEL: sitofp_i64:337; CHECK-BF16: // %bb.0:338; CHECK-BF16-NEXT: mov x8, v0.d[1]339; CHECK-BF16-NEXT: fmov x9, d0340; CHECK-BF16-NEXT: scvtf s2, x9341; CHECK-BF16-NEXT: mov x9, v1.d[1]342; CHECK-BF16-NEXT: scvtf s0, x8343; CHECK-BF16-NEXT: fmov x8, d1344; CHECK-BF16-NEXT: mov v2.s[1], v0.s[0]345; CHECK-BF16-NEXT: scvtf s0, x8346; CHECK-BF16-NEXT: mov v2.s[2], v0.s[0]347; CHECK-BF16-NEXT: scvtf s0, x9348; CHECK-BF16-NEXT: mov v2.s[3], v0.s[0]349; CHECK-BF16-NEXT: bfcvtn v0.4h, v2.4s350; CHECK-BF16-NEXT: ret351 %1 = sitofp <4 x i64> %a to <4 x bfloat>352 ret <4 x bfloat> %1353}354 355define <4 x bfloat> @uitofp_i8(<4 x i8> %a) #0 {356; CHECK-CVT-LABEL: uitofp_i8:357; CHECK-CVT: // %bb.0:358; CHECK-CVT-NEXT: bic v0.4h, #255, lsl #8359; CHECK-CVT-NEXT: movi v1.4s, #1360; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0361; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s362; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16363; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b364; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8365; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s366; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s367; CHECK-CVT-NEXT: ret368;369; CHECK-BF16-LABEL: uitofp_i8:370; CHECK-BF16: // %bb.0:371; CHECK-BF16-NEXT: bic v0.4h, #255, lsl #8372; CHECK-BF16-NEXT: ushll v0.4s, v0.4h, #0373; CHECK-BF16-NEXT: ucvtf v0.4s, v0.4s374; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s375; CHECK-BF16-NEXT: ret376 %1 = uitofp <4 x i8> %a to <4 x bfloat>377 ret <4 x bfloat> %1378}379 380 381define <4 x bfloat> @uitofp_i16(<4 x i16> %a) #0 {382; CHECK-CVT-LABEL: uitofp_i16:383; CHECK-CVT: // %bb.0:384; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0385; CHECK-CVT-NEXT: movi v1.4s, #1386; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s387; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16388; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b389; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8390; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s391; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s392; CHECK-CVT-NEXT: ret393;394; CHECK-BF16-LABEL: uitofp_i16:395; CHECK-BF16: // %bb.0:396; CHECK-BF16-NEXT: ushll v0.4s, v0.4h, #0397; CHECK-BF16-NEXT: ucvtf v0.4s, v0.4s398; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s399; CHECK-BF16-NEXT: ret400 %1 = uitofp <4 x i16> %a to <4 x bfloat>401 ret <4 x bfloat> %1402}403 404 405define <4 x bfloat> @uitofp_i32(<4 x i32> %a) #0 {406; CHECK-CVT-LABEL: uitofp_i32:407; CHECK-CVT: // %bb.0:408; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s409; CHECK-CVT-NEXT: movi v1.4s, #1410; CHECK-CVT-NEXT: ushr v2.4s, v0.4s, #16411; CHECK-CVT-NEXT: and v1.16b, v2.16b, v1.16b412; CHECK-CVT-NEXT: movi v2.4s, #127, msl #8413; CHECK-CVT-NEXT: add v0.4s, v1.4s, v0.4s414; CHECK-CVT-NEXT: addhn v0.4h, v0.4s, v2.4s415; CHECK-CVT-NEXT: ret416;417; CHECK-BF16-LABEL: uitofp_i32:418; CHECK-BF16: // %bb.0:419; CHECK-BF16-NEXT: ucvtf v0.4s, v0.4s420; CHECK-BF16-NEXT: bfcvtn v0.4h, v0.4s421; CHECK-BF16-NEXT: ret422 %1 = uitofp <4 x i32> %a to <4 x bfloat>423 ret <4 x bfloat> %1424}425 426 427define <4 x bfloat> @uitofp_i64(<4 x i64> %a) #0 {428; CHECK-CVT-LABEL: uitofp_i64:429; CHECK-CVT: // %bb.0:430; CHECK-CVT-NEXT: mov x8, v0.d[1]431; CHECK-CVT-NEXT: fmov x9, d0432; CHECK-CVT-NEXT: ucvtf s2, x9433; CHECK-CVT-NEXT: mov x9, v1.d[1]434; CHECK-CVT-NEXT: ucvtf s0, x8435; CHECK-CVT-NEXT: fmov x8, d1436; CHECK-CVT-NEXT: ucvtf s1, x8437; CHECK-CVT-NEXT: mov v2.s[1], v0.s[0]438; CHECK-CVT-NEXT: ucvtf s0, x9439; CHECK-CVT-NEXT: mov v2.s[2], v1.s[0]440; CHECK-CVT-NEXT: movi v1.4s, #127, msl #8441; CHECK-CVT-NEXT: mov v2.s[3], v0.s[0]442; CHECK-CVT-NEXT: movi v0.4s, #1443; CHECK-CVT-NEXT: ushr v3.4s, v2.4s, #16444; CHECK-CVT-NEXT: add v1.4s, v2.4s, v1.4s445; CHECK-CVT-NEXT: and v0.16b, v3.16b, v0.16b446; CHECK-CVT-NEXT: fcmeq v3.4s, v2.4s, v2.4s447; CHECK-CVT-NEXT: orr v2.4s, #64, lsl #16448; CHECK-CVT-NEXT: add v0.4s, v0.4s, v1.4s449; CHECK-CVT-NEXT: bif v0.16b, v2.16b, v3.16b450; CHECK-CVT-NEXT: shrn v0.4h, v0.4s, #16451; CHECK-CVT-NEXT: ret452;453; CHECK-BF16-LABEL: uitofp_i64:454; CHECK-BF16: // %bb.0:455; CHECK-BF16-NEXT: mov x8, v0.d[1]456; CHECK-BF16-NEXT: fmov x9, d0457; CHECK-BF16-NEXT: ucvtf s2, x9458; CHECK-BF16-NEXT: mov x9, v1.d[1]459; CHECK-BF16-NEXT: ucvtf s0, x8460; CHECK-BF16-NEXT: fmov x8, d1461; CHECK-BF16-NEXT: mov v2.s[1], v0.s[0]462; CHECK-BF16-NEXT: ucvtf s0, x8463; CHECK-BF16-NEXT: mov v2.s[2], v0.s[0]464; CHECK-BF16-NEXT: ucvtf s0, x9465; CHECK-BF16-NEXT: mov v2.s[3], v0.s[0]466; CHECK-BF16-NEXT: bfcvtn v0.4h, v2.4s467; CHECK-BF16-NEXT: ret468 %1 = uitofp <4 x i64> %a to <4 x bfloat>469 ret <4 x bfloat> %1470}471 472define void @test_insert_at_zero(bfloat %a, ptr %b) #0 {473; CHECK-LABEL: test_insert_at_zero:474; CHECK: // %bb.0:475; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0476; CHECK-NEXT: str d0, [x0]477; CHECK-NEXT: ret478 %1 = insertelement <4 x bfloat> undef, bfloat %a, i64 0479 store <4 x bfloat> %1, ptr %b, align 4480 ret void481}482 483define <4 x i8> @fptosi_i8(<4 x bfloat> %a) #0 {484; CHECK-LABEL: fptosi_i8:485; CHECK: // %bb.0:486; CHECK-NEXT: shll v0.4s, v0.4h, #16487; CHECK-NEXT: fcvtzs v0.4s, v0.4s488; CHECK-NEXT: xtn v0.4h, v0.4s489; CHECK-NEXT: ret490 %1 = fptosi<4 x bfloat> %a to <4 x i8>491 ret <4 x i8> %1492}493 494define <4 x i16> @fptosi_i16(<4 x bfloat> %a) #0 {495; CHECK-LABEL: fptosi_i16:496; CHECK: // %bb.0:497; CHECK-NEXT: shll v0.4s, v0.4h, #16498; CHECK-NEXT: fcvtzs v0.4s, v0.4s499; CHECK-NEXT: xtn v0.4h, v0.4s500; CHECK-NEXT: ret501 %1 = fptosi<4 x bfloat> %a to <4 x i16>502 ret <4 x i16> %1503}504 505define <4 x i8> @fptoui_i8(<4 x bfloat> %a) #0 {506; CHECK-LABEL: fptoui_i8:507; CHECK: // %bb.0:508; CHECK-NEXT: shll v0.4s, v0.4h, #16509; CHECK-NEXT: fcvtzs v0.4s, v0.4s510; CHECK-NEXT: xtn v0.4h, v0.4s511; CHECK-NEXT: ret512; NOTE: fcvtzs selected here because the xtn shaves the sign bit513 %1 = fptoui<4 x bfloat> %a to <4 x i8>514 ret <4 x i8> %1515}516 517define <4 x i16> @fptoui_i16(<4 x bfloat> %a) #0 {518; CHECK-LABEL: fptoui_i16:519; CHECK: // %bb.0:520; CHECK-NEXT: shll v0.4s, v0.4h, #16521; CHECK-NEXT: fcvtzu v0.4s, v0.4s522; CHECK-NEXT: xtn v0.4h, v0.4s523; CHECK-NEXT: ret524 %1 = fptoui<4 x bfloat> %a to <4 x i16>525 ret <4 x i16> %1526}527 528define <4 x i1> @test_fcmp_une(<4 x bfloat> %a, <4 x bfloat> %b) #0 {529; CHECK-LABEL: test_fcmp_une:530; CHECK: // %bb.0:531; CHECK-NEXT: shll v1.4s, v1.4h, #16532; CHECK-NEXT: shll v0.4s, v0.4h, #16533; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s534; CHECK-NEXT: mvn v0.16b, v0.16b535; CHECK-NEXT: xtn v0.4h, v0.4s536; CHECK-NEXT: ret537 538 %1 = fcmp une <4 x bfloat> %a, %b539 ret <4 x i1> %1540}541 542define <4 x i1> @test_fcmp_ueq(<4 x bfloat> %a, <4 x bfloat> %b) #0 {543; CHECK-LABEL: test_fcmp_ueq:544; CHECK: // %bb.0:545; CHECK-NEXT: shll v1.4s, v1.4h, #16546; CHECK-NEXT: shll v0.4s, v0.4h, #16547; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s548; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s549; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b550; CHECK-NEXT: xtn v0.4h, v0.4s551; CHECK-NEXT: mvn v0.8b, v0.8b552; CHECK-NEXT: ret553 554 %1 = fcmp ueq <4 x bfloat> %a, %b555 ret <4 x i1> %1556}557 558define <4 x i1> @test_fcmp_ugt(<4 x bfloat> %a, <4 x bfloat> %b) #0 {559; CHECK-LABEL: test_fcmp_ugt:560; CHECK: // %bb.0:561; CHECK-NEXT: shll v0.4s, v0.4h, #16562; CHECK-NEXT: shll v1.4s, v1.4h, #16563; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s564; CHECK-NEXT: xtn v0.4h, v0.4s565; CHECK-NEXT: mvn v0.8b, v0.8b566; CHECK-NEXT: ret567 568 %1 = fcmp ugt <4 x bfloat> %a, %b569 ret <4 x i1> %1570}571 572define <4 x i1> @test_fcmp_uge(<4 x bfloat> %a, <4 x bfloat> %b) #0 {573; CHECK-LABEL: test_fcmp_uge:574; CHECK: // %bb.0:575; CHECK-NEXT: shll v0.4s, v0.4h, #16576; CHECK-NEXT: shll v1.4s, v1.4h, #16577; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s578; CHECK-NEXT: xtn v0.4h, v0.4s579; CHECK-NEXT: mvn v0.8b, v0.8b580; CHECK-NEXT: ret581 582 %1 = fcmp uge <4 x bfloat> %a, %b583 ret <4 x i1> %1584}585 586define <4 x i1> @test_fcmp_ult(<4 x bfloat> %a, <4 x bfloat> %b) #0 {587; CHECK-LABEL: test_fcmp_ult:588; CHECK: // %bb.0:589; CHECK-NEXT: shll v1.4s, v1.4h, #16590; CHECK-NEXT: shll v0.4s, v0.4h, #16591; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s592; CHECK-NEXT: xtn v0.4h, v0.4s593; CHECK-NEXT: mvn v0.8b, v0.8b594; CHECK-NEXT: ret595 596 %1 = fcmp ult <4 x bfloat> %a, %b597 ret <4 x i1> %1598}599 600define <4 x i1> @test_fcmp_ule(<4 x bfloat> %a, <4 x bfloat> %b) #0 {601; CHECK-LABEL: test_fcmp_ule:602; CHECK: // %bb.0:603; CHECK-NEXT: shll v1.4s, v1.4h, #16604; CHECK-NEXT: shll v0.4s, v0.4h, #16605; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s606; CHECK-NEXT: xtn v0.4h, v0.4s607; CHECK-NEXT: mvn v0.8b, v0.8b608; CHECK-NEXT: ret609 610 %1 = fcmp ule <4 x bfloat> %a, %b611 ret <4 x i1> %1612}613 614define <4 x i1> @test_fcmp_uno(<4 x bfloat> %a, <4 x bfloat> %b) #0 {615; CHECK-LABEL: test_fcmp_uno:616; CHECK: // %bb.0:617; CHECK-NEXT: shll v1.4s, v1.4h, #16618; CHECK-NEXT: shll v0.4s, v0.4h, #16619; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s620; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s621; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b622; CHECK-NEXT: xtn v0.4h, v0.4s623; CHECK-NEXT: mvn v0.8b, v0.8b624; CHECK-NEXT: ret625 626 %1 = fcmp uno <4 x bfloat> %a, %b627 ret <4 x i1> %1628}629 630define <4 x i1> @test_fcmp_one(<4 x bfloat> %a, <4 x bfloat> %b) #0 {631; CHECK-LABEL: test_fcmp_one:632; CHECK: // %bb.0:633; CHECK-NEXT: shll v1.4s, v1.4h, #16634; CHECK-NEXT: shll v0.4s, v0.4h, #16635; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s636; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s637; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b638; CHECK-NEXT: xtn v0.4h, v0.4s639; CHECK-NEXT: ret640 641 %1 = fcmp one <4 x bfloat> %a, %b642 ret <4 x i1> %1643}644 645define <4 x i1> @test_fcmp_oeq(<4 x bfloat> %a, <4 x bfloat> %b) #0 {646; CHECK-LABEL: test_fcmp_oeq:647; CHECK: // %bb.0:648; CHECK-NEXT: shll v1.4s, v1.4h, #16649; CHECK-NEXT: shll v0.4s, v0.4h, #16650; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s651; CHECK-NEXT: xtn v0.4h, v0.4s652; CHECK-NEXT: ret653 654 %1 = fcmp oeq <4 x bfloat> %a, %b655 ret <4 x i1> %1656}657 658define <4 x i1> @test_fcmp_ogt(<4 x bfloat> %a, <4 x bfloat> %b) #0 {659; CHECK-LABEL: test_fcmp_ogt:660; CHECK: // %bb.0:661; CHECK-NEXT: shll v1.4s, v1.4h, #16662; CHECK-NEXT: shll v0.4s, v0.4h, #16663; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s664; CHECK-NEXT: xtn v0.4h, v0.4s665; CHECK-NEXT: ret666 667 %1 = fcmp ogt <4 x bfloat> %a, %b668 ret <4 x i1> %1669}670 671define <4 x i1> @test_fcmp_oge(<4 x bfloat> %a, <4 x bfloat> %b) #0 {672; CHECK-LABEL: test_fcmp_oge:673; CHECK: // %bb.0:674; CHECK-NEXT: shll v1.4s, v1.4h, #16675; CHECK-NEXT: shll v0.4s, v0.4h, #16676; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s677; CHECK-NEXT: xtn v0.4h, v0.4s678; CHECK-NEXT: ret679 680 %1 = fcmp oge <4 x bfloat> %a, %b681 ret <4 x i1> %1682}683 684define <4 x i1> @test_fcmp_olt(<4 x bfloat> %a, <4 x bfloat> %b) #0 {685; CHECK-LABEL: test_fcmp_olt:686; CHECK: // %bb.0:687; CHECK-NEXT: shll v0.4s, v0.4h, #16688; CHECK-NEXT: shll v1.4s, v1.4h, #16689; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s690; CHECK-NEXT: xtn v0.4h, v0.4s691; CHECK-NEXT: ret692 693 %1 = fcmp olt <4 x bfloat> %a, %b694 ret <4 x i1> %1695}696 697define <4 x i1> @test_fcmp_ole(<4 x bfloat> %a, <4 x bfloat> %b) #0 {698; CHECK-LABEL: test_fcmp_ole:699; CHECK: // %bb.0:700; CHECK-NEXT: shll v0.4s, v0.4h, #16701; CHECK-NEXT: shll v1.4s, v1.4h, #16702; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s703; CHECK-NEXT: xtn v0.4h, v0.4s704; CHECK-NEXT: ret705 706 %1 = fcmp ole <4 x bfloat> %a, %b707 ret <4 x i1> %1708}709 710define <4 x i1> @test_fcmp_ord(<4 x bfloat> %a, <4 x bfloat> %b) #0 {711; CHECK-LABEL: test_fcmp_ord:712; CHECK: // %bb.0:713; CHECK-NEXT: shll v1.4s, v1.4h, #16714; CHECK-NEXT: shll v0.4s, v0.4h, #16715; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s716; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s717; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b718; CHECK-NEXT: xtn v0.4h, v0.4s719; CHECK-NEXT: ret720 721 %1 = fcmp ord <4 x bfloat> %a, %b722 ret <4 x i1> %1723}724 725attributes #0 = { nounwind }726