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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+bf16 | FileCheck %s3 4define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {5; CHECK-LABEL: v4bf16_to_v4i16:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: fmov d0, d18; CHECK-NEXT: ret9entry:10 %1 = bitcast <4 x bfloat> %a to <4 x i16>11 ret <4 x i16> %112}13 14define <4 x half> @v4bf16_to_v4f16(float, <4 x bfloat> %a) nounwind {15; CHECK-LABEL: v4bf16_to_v4f16:16; CHECK: // %bb.0: // %entry17; CHECK-NEXT: fmov d0, d118; CHECK-NEXT: ret19entry:20 %1 = bitcast <4 x bfloat> %a to <4 x half>21 ret <4 x half> %122}23 24define <2 x i32> @v4bf16_to_v2i32(float, <4 x bfloat> %a) nounwind {25; CHECK-LABEL: v4bf16_to_v2i32:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: fmov d0, d128; CHECK-NEXT: ret29entry:30 %1 = bitcast <4 x bfloat> %a to <2 x i32>31 ret <2 x i32> %132}33 34define <1 x i64> @v4bf16_to_v1i64(float, <4 x bfloat> %a) nounwind {35; CHECK-LABEL: v4bf16_to_v1i64:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: fmov d0, d138; CHECK-NEXT: ret39entry:40 %1 = bitcast <4 x bfloat> %a to <1 x i64>41 ret <1 x i64> %142}43 44define i64 @v4bf16_to_i64(float, <4 x bfloat> %a) nounwind {45; CHECK-LABEL: v4bf16_to_i64:46; CHECK: // %bb.0: // %entry47; CHECK-NEXT: fmov x0, d148; CHECK-NEXT: ret49entry:50 %1 = bitcast <4 x bfloat> %a to i6451 ret i64 %152}53 54define <2 x float> @v4bf16_to_v2float(float, <4 x bfloat> %a) nounwind {55; CHECK-LABEL: v4bf16_to_v2float:56; CHECK: // %bb.0: // %entry57; CHECK-NEXT: fmov d0, d158; CHECK-NEXT: ret59entry:60 %1 = bitcast <4 x bfloat> %a to <2 x float>61 ret <2 x float> %162}63 64define <1 x double> @v4bf16_to_v1double(float, <4 x bfloat> %a) nounwind {65; CHECK-LABEL: v4bf16_to_v1double:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: fmov d0, d168; CHECK-NEXT: ret69entry:70 %1 = bitcast <4 x bfloat> %a to <1 x double>71 ret <1 x double> %172}73 74define double @v4bf16_to_double(float, <4 x bfloat> %a) nounwind {75; CHECK-LABEL: v4bf16_to_double:76; CHECK: // %bb.0: // %entry77; CHECK-NEXT: fmov d0, d178; CHECK-NEXT: ret79entry:80 %1 = bitcast <4 x bfloat> %a to double81 ret double %182}83 84 85define <4 x bfloat> @v4i16_to_v4bf16(float, <4 x i16> %a) nounwind {86; CHECK-LABEL: v4i16_to_v4bf16:87; CHECK: // %bb.0: // %entry88; CHECK-NEXT: fmov d0, d189; CHECK-NEXT: ret90entry:91 %1 = bitcast <4 x i16> %a to <4 x bfloat>92 ret <4 x bfloat> %193}94 95define <4 x bfloat> @v4f16_to_v4bf16(float, <4 x half> %a) nounwind {96; CHECK-LABEL: v4f16_to_v4bf16:97; CHECK: // %bb.0: // %entry98; CHECK-NEXT: fmov d0, d199; CHECK-NEXT: ret100entry:101 %1 = bitcast <4 x half> %a to <4 x bfloat>102 ret <4 x bfloat> %1103}104 105define <4 x bfloat> @v2i32_to_v4bf16(float, <2 x i32> %a) nounwind {106; CHECK-LABEL: v2i32_to_v4bf16:107; CHECK: // %bb.0: // %entry108; CHECK-NEXT: fmov d0, d1109; CHECK-NEXT: ret110entry:111 %1 = bitcast <2 x i32> %a to <4 x bfloat>112 ret <4 x bfloat> %1113}114 115define <4 x bfloat> @v1i64_to_v4bf16(float, <1 x i64> %a) nounwind {116; CHECK-LABEL: v1i64_to_v4bf16:117; CHECK: // %bb.0: // %entry118; CHECK-NEXT: fmov d0, d1119; CHECK-NEXT: ret120entry:121 %1 = bitcast <1 x i64> %a to <4 x bfloat>122 ret <4 x bfloat> %1123}124 125define <4 x bfloat> @i64_to_v4bf16(float, i64 %a) nounwind {126; CHECK-LABEL: i64_to_v4bf16:127; CHECK: // %bb.0: // %entry128; CHECK-NEXT: fmov d0, x0129; CHECK-NEXT: ret130entry:131 %1 = bitcast i64 %a to <4 x bfloat>132 ret <4 x bfloat> %1133}134 135define <4 x bfloat> @v2float_to_v4bf16(float, <2 x float> %a) nounwind {136; CHECK-LABEL: v2float_to_v4bf16:137; CHECK: // %bb.0: // %entry138; CHECK-NEXT: fmov d0, d1139; CHECK-NEXT: ret140entry:141 %1 = bitcast <2 x float> %a to <4 x bfloat>142 ret <4 x bfloat> %1143}144 145define <4 x bfloat> @v1double_to_v4bf16(float, <1 x double> %a) nounwind {146; CHECK-LABEL: v1double_to_v4bf16:147; CHECK: // %bb.0: // %entry148; CHECK-NEXT: fmov d0, d1149; CHECK-NEXT: ret150entry:151 %1 = bitcast <1 x double> %a to <4 x bfloat>152 ret <4 x bfloat> %1153}154 155define <4 x bfloat> @double_to_v4bf16(float, double %a) nounwind {156; CHECK-LABEL: double_to_v4bf16:157; CHECK: // %bb.0: // %entry158; CHECK-NEXT: fmov d0, d1159; CHECK-NEXT: ret160entry:161 %1 = bitcast double %a to <4 x bfloat>162 ret <4 x bfloat> %1163}164 165define <8 x i16> @v8bf16_to_v8i16(float, <8 x bfloat> %a) nounwind {166; CHECK-LABEL: v8bf16_to_v8i16:167; CHECK: // %bb.0: // %entry168; CHECK-NEXT: mov v0.16b, v1.16b169; CHECK-NEXT: ret170entry:171 %1 = bitcast <8 x bfloat> %a to <8 x i16>172 ret <8 x i16> %1173}174 175define <8 x half> @v8bf16_to_v8f16(float, <8 x bfloat> %a) nounwind {176; CHECK-LABEL: v8bf16_to_v8f16:177; CHECK: // %bb.0: // %entry178; CHECK-NEXT: mov v0.16b, v1.16b179; CHECK-NEXT: ret180entry:181 %1 = bitcast <8 x bfloat> %a to <8 x half>182 ret <8 x half> %1183}184 185define <4 x i32> @v8bf16_to_v4i32(float, <8 x bfloat> %a) nounwind {186; CHECK-LABEL: v8bf16_to_v4i32:187; CHECK: // %bb.0: // %entry188; CHECK-NEXT: mov v0.16b, v1.16b189; CHECK-NEXT: ret190entry:191 %1 = bitcast <8 x bfloat> %a to <4 x i32>192 ret <4 x i32> %1193}194 195define <2 x i64> @v8bf16_to_v2i64(float, <8 x bfloat> %a) nounwind {196; CHECK-LABEL: v8bf16_to_v2i64:197; CHECK: // %bb.0: // %entry198; CHECK-NEXT: mov v0.16b, v1.16b199; CHECK-NEXT: ret200entry:201 %1 = bitcast <8 x bfloat> %a to <2 x i64>202 ret <2 x i64> %1203}204 205define <4 x float> @v8bf16_to_v4float(float, <8 x bfloat> %a) nounwind {206; CHECK-LABEL: v8bf16_to_v4float:207; CHECK: // %bb.0: // %entry208; CHECK-NEXT: mov v0.16b, v1.16b209; CHECK-NEXT: ret210entry:211 %1 = bitcast <8 x bfloat> %a to <4 x float>212 ret <4 x float> %1213}214 215define <2 x double> @v8bf16_to_v2double(float, <8 x bfloat> %a) nounwind {216; CHECK-LABEL: v8bf16_to_v2double:217; CHECK: // %bb.0: // %entry218; CHECK-NEXT: mov v0.16b, v1.16b219; CHECK-NEXT: ret220entry:221 %1 = bitcast <8 x bfloat> %a to <2 x double>222 ret <2 x double> %1223}224 225define <8 x bfloat> @v8i16_to_v8bf16(float, <8 x i16> %a) nounwind {226; CHECK-LABEL: v8i16_to_v8bf16:227; CHECK: // %bb.0: // %entry228; CHECK-NEXT: mov v0.16b, v1.16b229; CHECK-NEXT: ret230entry:231 %1 = bitcast <8 x i16> %a to <8 x bfloat>232 ret <8 x bfloat> %1233}234 235define <8 x bfloat> @v8f16_to_v8bf16(float, <8 x half> %a) nounwind {236; CHECK-LABEL: v8f16_to_v8bf16:237; CHECK: // %bb.0: // %entry238; CHECK-NEXT: mov v0.16b, v1.16b239; CHECK-NEXT: ret240entry:241 %1 = bitcast <8 x half> %a to <8 x bfloat>242 ret <8 x bfloat> %1243}244 245define <8 x bfloat> @v4i32_to_v8bf16(float, <4 x i32> %a) nounwind {246; CHECK-LABEL: v4i32_to_v8bf16:247; CHECK: // %bb.0: // %entry248; CHECK-NEXT: mov v0.16b, v1.16b249; CHECK-NEXT: ret250entry:251 %1 = bitcast <4 x i32> %a to <8 x bfloat>252 ret <8 x bfloat> %1253}254 255define <8 x bfloat> @v2i64_to_v8bf16(float, <2 x i64> %a) nounwind {256; CHECK-LABEL: v2i64_to_v8bf16:257; CHECK: // %bb.0: // %entry258; CHECK-NEXT: mov v0.16b, v1.16b259; CHECK-NEXT: ret260entry:261 %1 = bitcast <2 x i64> %a to <8 x bfloat>262 ret <8 x bfloat> %1263}264 265define <8 x bfloat> @v4float_to_v8bf16(float, <4 x float> %a) nounwind {266; CHECK-LABEL: v4float_to_v8bf16:267; CHECK: // %bb.0: // %entry268; CHECK-NEXT: mov v0.16b, v1.16b269; CHECK-NEXT: ret270entry:271 %1 = bitcast <4 x float> %a to <8 x bfloat>272 ret <8 x bfloat> %1273}274 275define <8 x bfloat> @v2double_to_v8bf16(float, <2 x double> %a) nounwind {276; CHECK-LABEL: v2double_to_v8bf16:277; CHECK: // %bb.0: // %entry278; CHECK-NEXT: mov v0.16b, v1.16b279; CHECK-NEXT: ret280entry:281 %1 = bitcast <2 x double> %a to <8 x bfloat>282 ret <8 x bfloat> %1283}284