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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined.6 7define <4 x i16> @foo1(<2 x i32> %a) {8; CHECK-SD-LABEL: foo1:9; CHECK-SD: // %bb.0:10; CHECK-SD-NEXT: movi v0.2d, #000000000000000011; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: foo1:14; CHECK-GI: // %bb.0:15; CHECK-GI-NEXT: mov w8, #58712 // =0xe55816; CHECK-GI-NEXT: fmov s1, w817; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s18; CHECK-GI-NEXT: dup v0.4h, v0.h[1]19; CHECK-GI-NEXT: ret20 %1 = shufflevector <2 x i32> <i32 58712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>21; Can't optimize the following bitcast to scalar_to_vector.22 %2 = bitcast <2 x i32> %1 to <4 x i16>23 %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>24 ret <4 x i16> %325}26 27define <4 x i16> @foo2(<2 x i32> %a) {28; CHECK-SD-LABEL: foo2:29; CHECK-SD: // %bb.0:30; CHECK-SD-NEXT: movi v0.2d, #000000000000000031; CHECK-SD-NEXT: ret32;33; CHECK-GI-LABEL: foo2:34; CHECK-GI: // %bb.0:35; CHECK-GI-NEXT: mov w8, #712 // =0x2c836; CHECK-GI-NEXT: fmov s1, w837; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s38; CHECK-GI-NEXT: dup v0.4h, v0.h[1]39; CHECK-GI-NEXT: ret40 %1 = shufflevector <2 x i32> <i32 712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>41; Can't optimize the following bitcast to scalar_to_vector.42 %2 = bitcast <2 x i32> %1 to <4 x i16>43 %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>44 ret <4 x i16> %345}46 47; ===== To and From Scalar Types =====48 49define i32 @bitcast_v4i8_i32(<4 x i8> %a, <4 x i8> %b){50; CHECK-SD-LABEL: bitcast_v4i8_i32:51; CHECK-SD: // %bb.0:52; CHECK-SD-NEXT: sub sp, sp, #1653; CHECK-SD-NEXT: .cfi_def_cfa_offset 1654; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h55; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b56; CHECK-SD-NEXT: fmov w0, s057; CHECK-SD-NEXT: add sp, sp, #1658; CHECK-SD-NEXT: ret59;60; CHECK-GI-LABEL: bitcast_v4i8_i32:61; CHECK-GI: // %bb.0:62; CHECK-GI-NEXT: add v0.4h, v0.4h, v1.4h63; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b64; CHECK-GI-NEXT: fmov w0, s065; CHECK-GI-NEXT: ret66 %c = add <4 x i8> %a, %b67 %d = bitcast <4 x i8> %c to i3268 ret i32 %d69}70 71define <4 x i8> @bitcast_i32_v4i8(i32 %a, i32 %b){72; CHECK-SD-LABEL: bitcast_i32_v4i8:73; CHECK-SD: // %bb.0:74; CHECK-SD-NEXT: add w8, w0, w175; CHECK-SD-NEXT: fmov s0, w876; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b77; CHECK-SD-NEXT: ret78;79; CHECK-GI-LABEL: bitcast_i32_v4i8:80; CHECK-GI: // %bb.0:81; CHECK-GI-NEXT: add w8, w0, w182; CHECK-GI-NEXT: fmov s0, w883; CHECK-GI-NEXT: mov b1, v0.b[1]84; CHECK-GI-NEXT: mov b2, v0.b[2]85; CHECK-GI-NEXT: fmov w8, s186; CHECK-GI-NEXT: mov b1, v0.b[3]87; CHECK-GI-NEXT: mov v0.h[1], w888; CHECK-GI-NEXT: fmov w8, s289; CHECK-GI-NEXT: mov v0.h[2], w890; CHECK-GI-NEXT: fmov w8, s191; CHECK-GI-NEXT: mov v0.h[3], w892; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q093; CHECK-GI-NEXT: ret94 %c = add i32 %a, %b95 %d = bitcast i32 %c to <4 x i8>96 ret <4 x i8> %d97}98 99define i32 @bitcast_v2i16_i32(<2 x i16> %a, <2 x i16> %b){100; CHECK-SD-LABEL: bitcast_v2i16_i32:101; CHECK-SD: // %bb.0:102; CHECK-SD-NEXT: sub sp, sp, #16103; CHECK-SD-NEXT: .cfi_def_cfa_offset 16104; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s105; CHECK-SD-NEXT: mov s1, v0.s[1]106; CHECK-SD-NEXT: str h0, [sp, #12]107; CHECK-SD-NEXT: str h1, [sp, #14]108; CHECK-SD-NEXT: ldr w0, [sp, #12]109; CHECK-SD-NEXT: add sp, sp, #16110; CHECK-SD-NEXT: ret111;112; CHECK-GI-LABEL: bitcast_v2i16_i32:113; CHECK-GI: // %bb.0:114; CHECK-GI-NEXT: add v0.2s, v0.2s, v1.2s115; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h116; CHECK-GI-NEXT: fmov w0, s0117; CHECK-GI-NEXT: ret118 %c = add <2 x i16> %a, %b119 %d = bitcast <2 x i16> %c to i32120 ret i32 %d121}122 123define <2 x i16> @bitcast_i32_v2i16(i32 %a, i32 %b){124; CHECK-SD-LABEL: bitcast_i32_v2i16:125; CHECK-SD: // %bb.0:126; CHECK-SD-NEXT: add w8, w0, w1127; CHECK-SD-NEXT: fmov s0, w8128; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h129; CHECK-SD-NEXT: ret130;131; CHECK-GI-LABEL: bitcast_i32_v2i16:132; CHECK-GI: // %bb.0:133; CHECK-GI-NEXT: add w8, w0, w1134; CHECK-GI-NEXT: fmov s0, w8135; CHECK-GI-NEXT: mov h1, v0.h[1]136; CHECK-GI-NEXT: fmov w8, s1137; CHECK-GI-NEXT: mov v0.s[1], w8138; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0139; CHECK-GI-NEXT: ret140 %c = add i32 %a, %b141 %d = bitcast i32 %c to <2 x i16>142 ret <2 x i16> %d143}144 145define i64 @bitcast_v8i8_i64(<8 x i8> %a, <8 x i8> %b){146; CHECK-LABEL: bitcast_v8i8_i64:147; CHECK: // %bb.0:148; CHECK-NEXT: add v0.8b, v0.8b, v1.8b149; CHECK-NEXT: fmov x0, d0150; CHECK-NEXT: ret151 %c = add <8 x i8> %a, %b152 %d = bitcast <8 x i8> %c to i64153 ret i64 %d154}155 156define <8 x i8> @bitcast_i64_v8i8(i64 %a, i64 %b){157; CHECK-LABEL: bitcast_i64_v8i8:158; CHECK: // %bb.0:159; CHECK-NEXT: add x8, x0, x1160; CHECK-NEXT: fmov d0, x8161; CHECK-NEXT: ret162 %c = add i64 %a, %b163 %d = bitcast i64 %c to <8 x i8>164 ret <8 x i8> %d165}166 167define i64 @bitcast_v4i16_i64(<4 x i16> %a, <4 x i16> %b){168; CHECK-LABEL: bitcast_v4i16_i64:169; CHECK: // %bb.0:170; CHECK-NEXT: add v0.4h, v0.4h, v1.4h171; CHECK-NEXT: fmov x0, d0172; CHECK-NEXT: ret173 %c = add <4 x i16> %a, %b174 %d = bitcast <4 x i16> %c to i64175 ret i64 %d176}177 178define <4 x i16> @bitcast_i64_v4i16(i64 %a, i64 %b){179; CHECK-LABEL: bitcast_i64_v4i16:180; CHECK: // %bb.0:181; CHECK-NEXT: add x8, x0, x1182; CHECK-NEXT: fmov d0, x8183; CHECK-NEXT: ret184 %c = add i64 %a, %b185 %d = bitcast i64 %c to <4 x i16>186 ret <4 x i16> %d187}188 189define i64 @bitcast_v2i32_i64(<2 x i32> %a, <2 x i32> %b){190; CHECK-LABEL: bitcast_v2i32_i64:191; CHECK: // %bb.0:192; CHECK-NEXT: add v0.2s, v0.2s, v1.2s193; CHECK-NEXT: fmov x0, d0194; CHECK-NEXT: ret195 %c = add <2 x i32> %a, %b196 %d = bitcast <2 x i32> %c to i64197 ret i64 %d198}199 200define <2 x i32> @bitcast_i64_v2i32(i64 %a, i64 %b){201; CHECK-LABEL: bitcast_i64_v2i32:202; CHECK: // %bb.0:203; CHECK-NEXT: add x8, x0, x1204; CHECK-NEXT: fmov d0, x8205; CHECK-NEXT: ret206 %c = add i64 %a, %b207 %d = bitcast i64 %c to <2 x i32>208 ret <2 x i32> %d209}210 211; ===== Legal Vector Types =====212 213define <4 x i16> @bitcast_v2i32_v4i16(<2 x i32> %a, <2 x i32> %b){214; CHECK-LABEL: bitcast_v2i32_v4i16:215; CHECK: // %bb.0:216; CHECK-NEXT: add v0.2s, v0.2s, v1.2s217; CHECK-NEXT: ret218 %c = add <2 x i32> %a, %b219 %d = bitcast <2 x i32> %c to <4 x i16>220 ret <4 x i16> %d221}222 223define <4 x i32> @bitcast_v2i64_v4i32(<2 x i64> %a, <2 x i64> %b){224; CHECK-LABEL: bitcast_v2i64_v4i32:225; CHECK: // %bb.0:226; CHECK-NEXT: add v0.2d, v0.2d, v1.2d227; CHECK-NEXT: ret228 %c = add <2 x i64> %a, %b229 %d = bitcast <2 x i64> %c to <4 x i32>230 ret <4 x i32> %d231}232 233define <8 x i8> @bitcast_v2i32_v8i8(<2 x i32> %a, <2 x i32> %b){234; CHECK-LABEL: bitcast_v2i32_v8i8:235; CHECK: // %bb.0:236; CHECK-NEXT: add v0.2s, v0.2s, v1.2s237; CHECK-NEXT: ret238 %c = add <2 x i32> %a, %b239 %d = bitcast <2 x i32> %c to <8 x i8>240 ret <8 x i8> %d241}242 243define <8 x i16> @bitcast_v2i64_v8i16(<2 x i64> %a, <2 x i64> %b){244; CHECK-LABEL: bitcast_v2i64_v8i16:245; CHECK: // %bb.0:246; CHECK-NEXT: add v0.2d, v0.2d, v1.2d247; CHECK-NEXT: ret248 %c = add <2 x i64> %a, %b249 %d = bitcast <2 x i64> %c to <8 x i16>250 ret <8 x i16> %d251}252 253define <16 x i8> @bitcast_v2i64_v16i8(<2 x i64> %a, <2 x i64> %b){254; CHECK-LABEL: bitcast_v2i64_v16i8:255; CHECK: // %bb.0:256; CHECK-NEXT: add v0.2d, v0.2d, v1.2d257; CHECK-NEXT: ret258 %c = add <2 x i64> %a, %b259 %d = bitcast <2 x i64> %c to <16 x i8>260 ret <16 x i8> %d261}262 263define <2 x i32> @bitcast_v4i16_v2i32(<4 x i16> %a, <4 x i16> %b){264; CHECK-LABEL: bitcast_v4i16_v2i32:265; CHECK: // %bb.0:266; CHECK-NEXT: add v0.4h, v0.4h, v1.4h267; CHECK-NEXT: ret268 %c = add <4 x i16> %a, %b269 %d = bitcast <4 x i16> %c to <2 x i32>270 ret <2 x i32> %d271}272 273define <2 x i64> @bitcast_v4i32_v2i64(<4 x i32> %a, <4 x i32> %b){274; CHECK-LABEL: bitcast_v4i32_v2i64:275; CHECK: // %bb.0:276; CHECK-NEXT: add v0.4s, v0.4s, v1.4s277; CHECK-NEXT: ret278 %c = add <4 x i32> %a, %b279 %d = bitcast <4 x i32> %c to <2 x i64>280 ret <2 x i64> %d281}282 283define <8 x i8> @bitcast_v4i16_v8i8(<4 x i16> %a, <4 x i16> %b){284; CHECK-LABEL: bitcast_v4i16_v8i8:285; CHECK: // %bb.0:286; CHECK-NEXT: add v0.4h, v0.4h, v1.4h287; CHECK-NEXT: ret288 %c = add <4 x i16> %a, %b289 %d = bitcast <4 x i16> %c to <8 x i8>290 ret <8 x i8> %d291}292 293define <8 x i16> @bitcast_v4i32_v8i16(<4 x i32> %a, <4 x i32> %b){294; CHECK-LABEL: bitcast_v4i32_v8i16:295; CHECK: // %bb.0:296; CHECK-NEXT: add v0.4s, v0.4s, v1.4s297; CHECK-NEXT: ret298 %c = add <4 x i32> %a, %b299 %d = bitcast <4 x i32> %c to <8 x i16>300 ret <8 x i16> %d301}302 303define <16 x i8> @bitcast_v4i32_v16i8(<4 x i32> %a, <4 x i32> %b){304; CHECK-LABEL: bitcast_v4i32_v16i8:305; CHECK: // %bb.0:306; CHECK-NEXT: add v0.4s, v0.4s, v1.4s307; CHECK-NEXT: ret308 %c = add <4 x i32> %a, %b309 %d = bitcast <4 x i32> %c to <16 x i8>310 ret <16 x i8> %d311}312 313define <2 x i32> @bitcast_v8i8_v2i32(<8 x i8> %a, <8 x i8> %b){314; CHECK-LABEL: bitcast_v8i8_v2i32:315; CHECK: // %bb.0:316; CHECK-NEXT: add v0.8b, v0.8b, v1.8b317; CHECK-NEXT: ret318 %c = add <8 x i8> %a, %b319 %d = bitcast <8 x i8> %c to <2 x i32>320 ret <2 x i32> %d321}322 323define <2 x i64> @bitcast_v8i16_v2i64(<8 x i16> %a, <8 x i16> %b){324; CHECK-LABEL: bitcast_v8i16_v2i64:325; CHECK: // %bb.0:326; CHECK-NEXT: add v0.8h, v0.8h, v1.8h327; CHECK-NEXT: ret328 %c = add <8 x i16> %a, %b329 %d = bitcast <8 x i16> %c to <2 x i64>330 ret <2 x i64> %d331}332 333define <4 x i16> @bitcast_v8i8_v4i16(<8 x i8> %a, <8 x i8> %b){334; CHECK-LABEL: bitcast_v8i8_v4i16:335; CHECK: // %bb.0:336; CHECK-NEXT: add v0.8b, v0.8b, v1.8b337; CHECK-NEXT: ret338 %c = add <8 x i8> %a, %b339 %d = bitcast <8 x i8> %c to <4 x i16>340 ret <4 x i16> %d341}342 343define <4 x i32> @bitcast_v8i16_v4i32(<8 x i16> %a, <8 x i16> %b){344; CHECK-LABEL: bitcast_v8i16_v4i32:345; CHECK: // %bb.0:346; CHECK-NEXT: add v0.8h, v0.8h, v1.8h347; CHECK-NEXT: ret348 %c = add <8 x i16> %a, %b349 %d = bitcast <8 x i16> %c to <4 x i32>350 ret <4 x i32> %d351}352 353define <16 x i8> @bitcast_v8i16_v16i8(<8 x i16> %a, <8 x i16> %b){354; CHECK-LABEL: bitcast_v8i16_v16i8:355; CHECK: // %bb.0:356; CHECK-NEXT: add v0.8h, v0.8h, v1.8h357; CHECK-NEXT: ret358 %c = add <8 x i16> %a, %b359 %d = bitcast <8 x i16> %c to <16 x i8>360 ret <16 x i8> %d361}362 363define <2 x i64> @bitcast_v16i8_v2i64(<16 x i8> %a, <16 x i8> %b){364; CHECK-LABEL: bitcast_v16i8_v2i64:365; CHECK: // %bb.0:366; CHECK-NEXT: add v0.16b, v0.16b, v1.16b367; CHECK-NEXT: ret368 %c = add <16 x i8> %a, %b369 %d = bitcast <16 x i8> %c to <2 x i64>370 ret <2 x i64> %d371}372 373define <4 x i32> @bitcast_v16i8_v4i32(<16 x i8> %a, <16 x i8> %b){374; CHECK-LABEL: bitcast_v16i8_v4i32:375; CHECK: // %bb.0:376; CHECK-NEXT: add v0.16b, v0.16b, v1.16b377; CHECK-NEXT: ret378 %c = add <16 x i8> %a, %b379 %d = bitcast <16 x i8> %c to <4 x i32>380 ret <4 x i32> %d381}382 383define <8 x i16> @bitcast_v16i8_v8i16(<16 x i8> %a, <16 x i8> %b){384; CHECK-LABEL: bitcast_v16i8_v8i16:385; CHECK: // %bb.0:386; CHECK-NEXT: add v0.16b, v0.16b, v1.16b387; CHECK-NEXT: ret388 %c = add <16 x i8> %a, %b389 %d = bitcast <16 x i8> %c to <8 x i16>390 ret <8 x i16> %d391}392 393; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====394 395define <4 x i8> @bitcast_v2i16_v4i8(<2 x i16> %a, <2 x i16> %b){396; CHECK-SD-LABEL: bitcast_v2i16_v4i8:397; CHECK-SD: // %bb.0:398; CHECK-SD-NEXT: sub sp, sp, #16399; CHECK-SD-NEXT: .cfi_def_cfa_offset 16400; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s401; CHECK-SD-NEXT: mov s1, v0.s[1]402; CHECK-SD-NEXT: str h0, [sp, #12]403; CHECK-SD-NEXT: str h1, [sp, #14]404; CHECK-SD-NEXT: ldr s0, [sp, #12]405; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0406; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0407; CHECK-SD-NEXT: add sp, sp, #16408; CHECK-SD-NEXT: ret409;410; CHECK-GI-LABEL: bitcast_v2i16_v4i8:411; CHECK-GI: // %bb.0:412; CHECK-GI-NEXT: add v0.2s, v0.2s, v1.2s413; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h414; CHECK-GI-NEXT: mov b1, v0.b[1]415; CHECK-GI-NEXT: mov b2, v0.b[2]416; CHECK-GI-NEXT: fmov w8, s1417; CHECK-GI-NEXT: mov b1, v0.b[3]418; CHECK-GI-NEXT: mov v0.h[1], w8419; CHECK-GI-NEXT: fmov w8, s2420; CHECK-GI-NEXT: mov v0.h[2], w8421; CHECK-GI-NEXT: fmov w8, s1422; CHECK-GI-NEXT: mov v0.h[3], w8423; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0424; CHECK-GI-NEXT: ret425 %c = add <2 x i16> %a, %b426 %d = bitcast <2 x i16> %c to <4 x i8>427 ret <4 x i8> %d428}429 430define <2 x i16> @bitcast_v4i8_v2i16(<4 x i8> %a, <4 x i8> %b){431; CHECK-SD-LABEL: bitcast_v4i8_v2i16:432; CHECK-SD: // %bb.0:433; CHECK-SD-NEXT: sub sp, sp, #16434; CHECK-SD-NEXT: .cfi_def_cfa_offset 16435; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h436; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b437; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0438; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0439; CHECK-SD-NEXT: add sp, sp, #16440; CHECK-SD-NEXT: ret441;442; CHECK-GI-LABEL: bitcast_v4i8_v2i16:443; CHECK-GI: // %bb.0:444; CHECK-GI-NEXT: add v0.4h, v0.4h, v1.4h445; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b446; CHECK-GI-NEXT: mov h1, v0.h[1]447; CHECK-GI-NEXT: fmov w8, s1448; CHECK-GI-NEXT: mov v0.s[1], w8449; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0450; CHECK-GI-NEXT: ret451 %c = add <4 x i8> %a, %b452 %d = bitcast <4 x i8> %c to <2 x i16>453 ret <2 x i16> %d454}455 456define <8 x i32> @bitcast_v4i64_v8i32(<4 x i64> %a, <4 x i64> %b){457; CHECK-SD-LABEL: bitcast_v4i64_v8i32:458; CHECK-SD: // %bb.0:459; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d460; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d461; CHECK-SD-NEXT: ret462;463; CHECK-GI-LABEL: bitcast_v4i64_v8i32:464; CHECK-GI: // %bb.0:465; CHECK-GI-NEXT: add v0.2d, v0.2d, v2.2d466; CHECK-GI-NEXT: add v1.2d, v1.2d, v3.2d467; CHECK-GI-NEXT: ret468 %c = add <4 x i64> %a, %b469 %d = bitcast <4 x i64> %c to <8 x i32>470 ret <8 x i32> %d471}472 473define <16 x i16> @bitcast_v4i64_v16i16(<4 x i64> %a, <4 x i64> %b){474; CHECK-SD-LABEL: bitcast_v4i64_v16i16:475; CHECK-SD: // %bb.0:476; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d477; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d478; CHECK-SD-NEXT: ret479;480; CHECK-GI-LABEL: bitcast_v4i64_v16i16:481; CHECK-GI: // %bb.0:482; CHECK-GI-NEXT: add v0.2d, v0.2d, v2.2d483; CHECK-GI-NEXT: add v1.2d, v1.2d, v3.2d484; CHECK-GI-NEXT: ret485 %c = add <4 x i64> %a, %b486 %d = bitcast <4 x i64> %c to <16 x i16>487 ret <16 x i16> %d488}489 490define <4 x i64> @bitcast_v8i32_v4i64(<8 x i32> %a, <8 x i32> %b){491; CHECK-SD-LABEL: bitcast_v8i32_v4i64:492; CHECK-SD: // %bb.0:493; CHECK-SD-NEXT: add v1.4s, v1.4s, v3.4s494; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s495; CHECK-SD-NEXT: ret496;497; CHECK-GI-LABEL: bitcast_v8i32_v4i64:498; CHECK-GI: // %bb.0:499; CHECK-GI-NEXT: add v0.4s, v0.4s, v2.4s500; CHECK-GI-NEXT: add v1.4s, v1.4s, v3.4s501; CHECK-GI-NEXT: mov x8, v0.d[1]502; CHECK-GI-NEXT: mov x9, v1.d[1]503; CHECK-GI-NEXT: mov v0.d[1], x8504; CHECK-GI-NEXT: mov v1.d[1], x9505; CHECK-GI-NEXT: ret506 %c = add <8 x i32> %a, %b507 %d = bitcast <8 x i32> %c to <4 x i64>508 ret <4 x i64> %d509}510 511define <16 x i16> @bitcast_v8i32_v16i16(<8 x i32> %a, <8 x i32> %b){512; CHECK-SD-LABEL: bitcast_v8i32_v16i16:513; CHECK-SD: // %bb.0:514; CHECK-SD-NEXT: add v1.4s, v1.4s, v3.4s515; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s516; CHECK-SD-NEXT: ret517;518; CHECK-GI-LABEL: bitcast_v8i32_v16i16:519; CHECK-GI: // %bb.0:520; CHECK-GI-NEXT: add v0.4s, v0.4s, v2.4s521; CHECK-GI-NEXT: add v1.4s, v1.4s, v3.4s522; CHECK-GI-NEXT: ret523 %c = add <8 x i32> %a, %b524 %d = bitcast <8 x i32> %c to <16 x i16>525 ret <16 x i16> %d526}527 528define <16 x i32> @bitcast_v8i64_v16i32(<8 x i64> %a, <8 x i64> %b){529; CHECK-SD-LABEL: bitcast_v8i64_v16i32:530; CHECK-SD: // %bb.0:531; CHECK-SD-NEXT: add v2.2d, v2.2d, v6.2d532; CHECK-SD-NEXT: add v0.2d, v0.2d, v4.2d533; CHECK-SD-NEXT: add v1.2d, v1.2d, v5.2d534; CHECK-SD-NEXT: add v3.2d, v3.2d, v7.2d535; CHECK-SD-NEXT: ret536;537; CHECK-GI-LABEL: bitcast_v8i64_v16i32:538; CHECK-GI: // %bb.0:539; CHECK-GI-NEXT: add v0.2d, v0.2d, v4.2d540; CHECK-GI-NEXT: add v1.2d, v1.2d, v5.2d541; CHECK-GI-NEXT: add v2.2d, v2.2d, v6.2d542; CHECK-GI-NEXT: add v3.2d, v3.2d, v7.2d543; CHECK-GI-NEXT: ret544 %c = add <8 x i64> %a, %b545 %d = bitcast <8 x i64> %c to <16 x i32>546 ret <16 x i32> %d547}548 549define <4 x i64> @bitcast_v16i16_v4i64(<16 x i16> %a, <16 x i16> %b){550; CHECK-SD-LABEL: bitcast_v16i16_v4i64:551; CHECK-SD: // %bb.0:552; CHECK-SD-NEXT: add v1.8h, v1.8h, v3.8h553; CHECK-SD-NEXT: add v0.8h, v0.8h, v2.8h554; CHECK-SD-NEXT: ret555;556; CHECK-GI-LABEL: bitcast_v16i16_v4i64:557; CHECK-GI: // %bb.0:558; CHECK-GI-NEXT: add v0.8h, v0.8h, v2.8h559; CHECK-GI-NEXT: add v1.8h, v1.8h, v3.8h560; CHECK-GI-NEXT: mov x8, v0.d[1]561; CHECK-GI-NEXT: mov x9, v1.d[1]562; CHECK-GI-NEXT: mov v0.d[1], x8563; CHECK-GI-NEXT: mov v1.d[1], x9564; CHECK-GI-NEXT: ret565 %c = add <16 x i16> %a, %b566 %d = bitcast <16 x i16> %c to <4 x i64>567 ret <4 x i64> %d568}569 570define <8 x i32> @bitcast_v16i16_v8i32(<16 x i16> %a, <16 x i16> %b){571; CHECK-SD-LABEL: bitcast_v16i16_v8i32:572; CHECK-SD: // %bb.0:573; CHECK-SD-NEXT: add v1.8h, v1.8h, v3.8h574; CHECK-SD-NEXT: add v0.8h, v0.8h, v2.8h575; CHECK-SD-NEXT: ret576;577; CHECK-GI-LABEL: bitcast_v16i16_v8i32:578; CHECK-GI: // %bb.0:579; CHECK-GI-NEXT: add v0.8h, v0.8h, v2.8h580; CHECK-GI-NEXT: add v1.8h, v1.8h, v3.8h581; CHECK-GI-NEXT: ret582 %c = add <16 x i16> %a, %b583 %d = bitcast <16 x i16> %c to <8 x i32>584 ret <8 x i32> %d585}586 587define <8 x i64> @bitcast_v16i32_v8i64(<16 x i32> %a, <16 x i32> %b){588; CHECK-SD-LABEL: bitcast_v16i32_v8i64:589; CHECK-SD: // %bb.0:590; CHECK-SD-NEXT: add v2.4s, v2.4s, v6.4s591; CHECK-SD-NEXT: add v0.4s, v0.4s, v4.4s592; CHECK-SD-NEXT: add v1.4s, v1.4s, v5.4s593; CHECK-SD-NEXT: add v3.4s, v3.4s, v7.4s594; CHECK-SD-NEXT: ret595;596; CHECK-GI-LABEL: bitcast_v16i32_v8i64:597; CHECK-GI: // %bb.0:598; CHECK-GI-NEXT: add v0.4s, v0.4s, v4.4s599; CHECK-GI-NEXT: add v1.4s, v1.4s, v5.4s600; CHECK-GI-NEXT: add v2.4s, v2.4s, v6.4s601; CHECK-GI-NEXT: add v3.4s, v3.4s, v7.4s602; CHECK-GI-NEXT: mov x8, v0.d[1]603; CHECK-GI-NEXT: mov x9, v1.d[1]604; CHECK-GI-NEXT: mov x10, v2.d[1]605; CHECK-GI-NEXT: mov x11, v3.d[1]606; CHECK-GI-NEXT: mov v0.d[1], x8607; CHECK-GI-NEXT: mov v1.d[1], x9608; CHECK-GI-NEXT: mov v2.d[1], x10609; CHECK-GI-NEXT: mov v3.d[1], x11610; CHECK-GI-NEXT: ret611 %c = add <16 x i32> %a, %b612 %d = bitcast <16 x i32> %c to <8 x i64>613 ret <8 x i64> %d614}615 616define <8 x i32> @scalar_i128(<2 x i128> %a) {617; CHECK-SD-LABEL: scalar_i128:618; CHECK-SD: // %bb.0:619; CHECK-SD-NEXT: fmov d1, x2620; CHECK-SD-NEXT: fmov d0, x0621; CHECK-SD-NEXT: mov v1.d[1], x3622; CHECK-SD-NEXT: mov v0.d[1], x1623; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s624; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s625; CHECK-SD-NEXT: ret626;627; CHECK-GI-LABEL: scalar_i128:628; CHECK-GI: // %bb.0:629; CHECK-GI-NEXT: mov v0.d[0], x0630; CHECK-GI-NEXT: mov v1.d[0], x2631; CHECK-GI-NEXT: mov v0.d[1], x1632; CHECK-GI-NEXT: mov v1.d[1], x3633; CHECK-GI-NEXT: add v0.4s, v0.4s, v0.4s634; CHECK-GI-NEXT: add v1.4s, v1.4s, v1.4s635; CHECK-GI-NEXT: ret636 %c = bitcast <2 x i128> %a to <8 x i32>637 %d = add <8 x i32> %c, %c638 ret <8 x i32> %d639}640 641; ===== Vectors with Non-Pow 2 Widths =====642 643define <6 x i16> @bitcast_v3i32_v6i16(<3 x i32> %a, <3 x i32> %b){644; CHECK-LABEL: bitcast_v3i32_v6i16:645; CHECK: // %bb.0:646; CHECK-NEXT: add v0.4s, v0.4s, v1.4s647; CHECK-NEXT: ret648 %c = add <3 x i32> %a, %b649 %d = bitcast <3 x i32> %c to <6 x i16>650 ret <6 x i16> %d651}652