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1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s2 3@var32 = dso_local global i32 04@var64 = dso_local global i64 05 6define dso_local void @test_extendb32(i8 %var) {7; CHECK-LABEL: test_extendb32:8 9 %sxt32 = sext i8 %var to i3210 store volatile i32 %sxt32, ptr @var3211; CHECK: sxtb {{w[0-9]+}}, {{w[0-9]+}}12 13; N.b. this doesn't actually produce a bitfield instruction at the14; moment, but it's still a good test to have and the semantics are15; correct.16 %uxt32 = zext i8 %var to i3217 store volatile i32 %uxt32, ptr @var3218; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff19 ret void20}21 22define dso_local void @test_extendb64(i8 %var) {23; CHECK-LABEL: test_extendb64:24 25 %sxt64 = sext i8 %var to i6426 store volatile i64 %sxt64, ptr @var6427; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}28 29; N.b. this doesn't actually produce a bitfield instruction at the30; moment, but it's still a good test to have and the semantics are31; correct.32 %uxt64 = zext i8 %var to i6433 store volatile i64 %uxt64, ptr @var6434; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff35 ret void36}37 38define dso_local void @test_extendh32(i16 %var) {39; CHECK-LABEL: test_extendh32:40 41 %sxt32 = sext i16 %var to i3242 store volatile i32 %sxt32, ptr @var3243; CHECK: sxth {{w[0-9]+}}, {{w[0-9]+}}44 45; N.b. this doesn't actually produce a bitfield instruction at the46; moment, but it's still a good test to have and the semantics are47; correct.48 %uxt32 = zext i16 %var to i3249 store volatile i32 %uxt32, ptr @var3250; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff51 ret void52}53 54define dso_local void @test_extendh64(i16 %var) {55; CHECK-LABEL: test_extendh64:56 57 %sxt64 = sext i16 %var to i6458 store volatile i64 %sxt64, ptr @var6459; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}60 61; N.b. this doesn't actually produce a bitfield instruction at the62; moment, but it's still a good test to have and the semantics are63; correct.64 %uxt64 = zext i16 %var to i6465 store volatile i64 %uxt64, ptr @var6466; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff67 ret void68}69 70define dso_local void @test_extendw(i32 %var) {71; CHECK-LABEL: test_extendw:72 73 %sxt64 = sext i32 %var to i6474 store volatile i64 %sxt64, ptr @var6475; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}}76 77 %uxt64 = zext i32 %var to i6478 store volatile i64 %uxt64, ptr @var6479; CHECK: mov {{w[0-9]+}}, w080 ret void81}82 83define dso_local void @test_shifts(i32 %val32, i64 %val64) {84; CHECK-LABEL: test_shifts:85 86 %shift1 = ashr i32 %val32, 3187 store volatile i32 %shift1, ptr @var3288; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, #3189 90 %shift2 = lshr i32 %val32, 891 store volatile i32 %shift2, ptr @var3292; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #893 94 %shift3 = shl i32 %val32, 195 store volatile i32 %shift3, ptr @var3296; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #197 98 %shift4 = ashr i64 %val64, 3199 store volatile i64 %shift4, ptr @var64100; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #31101 102 %shift5 = lshr i64 %val64, 8103 store volatile i64 %shift5, ptr @var64104; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #8105 106 %shift6 = shl i64 %val64, 63107 store volatile i64 %shift6, ptr @var64108; CHECK: lsl {{x[0-9]+}}, {{x[0-9]+}}, #63109 110 %shift7 = ashr i64 %val64, 63111 store volatile i64 %shift7, ptr @var64112; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #63113 114 %shift8 = lshr i64 %val64, 63115 store volatile i64 %shift8, ptr @var64116; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #63117 118 %shift9 = lshr i32 %val32, 31119 store volatile i32 %shift9, ptr @var32120; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #31121 122 %shift10 = shl i32 %val32, 31123 store volatile i32 %shift10, ptr @var32124; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #31125 126 ret void127}128 129; LLVM can produce in-register extensions taking place entirely with130; 64-bit registers too.131define dso_local void @test_sext_inreg_64(i64 %in) {132; CHECK-LABEL: test_sext_inreg_64:133 134; i1 doesn't have an official alias, but crops up and is handled by135; the bitfield ops.136 %trunc_i1 = trunc i64 %in to i1137 %sext_i1 = sext i1 %trunc_i1 to i64138 store volatile i64 %sext_i1, ptr @var64139; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1140 141 %trunc_i8 = trunc i64 %in to i8142 %sext_i8 = sext i8 %trunc_i8 to i64143 store volatile i64 %sext_i8, ptr @var64144; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}145 146 %trunc_i16 = trunc i64 %in to i16147 %sext_i16 = sext i16 %trunc_i16 to i64148 store volatile i64 %sext_i16, ptr @var64149; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}150 151 %trunc_i32 = trunc i64 %in to i32152 %sext_i32 = sext i32 %trunc_i32 to i64153 store volatile i64 %sext_i32, ptr @var64154; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}}155 ret void156}157 158; These instructions don't actually select to official bitfield159; operations, but it's important that we select them somehow:160define dso_local void @test_zext_inreg_64(i64 %in) {161; CHECK-LABEL: test_zext_inreg_64:162 163 %trunc_i8 = trunc i64 %in to i8164 %zext_i8 = zext i8 %trunc_i8 to i64165 store volatile i64 %zext_i8, ptr @var64166; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff167 168 %trunc_i16 = trunc i64 %in to i16169 %zext_i16 = zext i16 %trunc_i16 to i64170 store volatile i64 %zext_i16, ptr @var64171; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff172 173 %trunc_i32 = trunc i64 %in to i32174 %zext_i32 = zext i32 %trunc_i32 to i64175 store volatile i64 %zext_i32, ptr @var64176; CHECK: mov {{w[0-9]+}}, {{w[0-9]+}}177 178 ret void179}180 181define dso_local i64 @test_sext_inreg_from_32(i32 %in) {182; CHECK-LABEL: test_sext_inreg_from_32:183 184 %small = trunc i32 %in to i1185 %ext = sext i1 %small to i64186 187 ; Different registers are of course, possible, though suboptimal. This is188 ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit189 ; sbfx rather than just 32-bits.190; CHECK: sbfx x0, x0, #0, #1191 ret i64 %ext192}193 194 195define dso_local i32 @test_ubfx32(ptr %addr) {196; CHECK-LABEL: test_ubfx32:197; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3198 199 %fields = load i32, ptr %addr200 %shifted = lshr i32 %fields, 23201 %masked = and i32 %shifted, 7202 ret i32 %masked203}204 205define dso_local i64 @test_ubfx64(ptr %addr) {206; CHECK-LABEL: test_ubfx64:207; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10208 %fields = load i64, ptr %addr209 %shifted = lshr i64 %fields, 25210 %masked = and i64 %shifted, 1023211 ret i64 %masked212}213 214define dso_local i32 @test_sbfx32(ptr %addr) {215; CHECK-LABEL: test_sbfx32:216; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3217 218 %fields = load i32, ptr %addr219 %shifted = shl i32 %fields, 23220 %extended = ashr i32 %shifted, 29221 ret i32 %extended222}223 224define dso_local i64 @test_sbfx64(ptr %addr) {225; CHECK-LABEL: test_sbfx64:226; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63227 228 %fields = load i64, ptr %addr229 %shifted = shl i64 %fields, 1230 %extended = ashr i64 %shifted, 1231 ret i64 %extended232}233 234define i32 @test_ubfx_mask(i32 %lhs, i32 %rhs) {235; CHECK-LABEL: test_ubfx_mask:236; CHECK: lsr w0, w1, #20237 %mask = and i32 %lhs, 20238 %i7 = add i32 %mask, 1239 %i8 = xor i32 %lhs, 20240 %i9 = xor i32 %i8, %i7241 %i10 = and i32 %i9, 20242 %shift = lshr i32 %rhs, %i10243 %shift.masked = and i32 %shift, 65535244 ret i32 %shift.masked245}246