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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,SDAG3; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes=CHECK,GISEL4 5; These tests just check that the plumbing is in place for @llvm.bitreverse.6 7declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone8 9define <2 x i16> @f(<2 x i16> %a) {10; SDAG-LABEL: f:11; SDAG: // %bb.0:12; SDAG-NEXT: rev32 v0.8b, v0.8b13; SDAG-NEXT: rbit v0.8b, v0.8b14; SDAG-NEXT: ushr v0.2s, v0.2s, #1615; SDAG-NEXT: ret16;17; GISEL-LABEL: f:18; GISEL: // %bb.0:19; GISEL-NEXT: uzp1 v0.4h, v0.4h, v0.4h20; GISEL-NEXT: rev16 v0.8b, v0.8b21; GISEL-NEXT: rbit v0.8b, v0.8b22; GISEL-NEXT: ushll v0.4s, v0.4h, #023; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q024; GISEL-NEXT: ret25 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)26 ret <2 x i16> %b27}28 29declare i8 @llvm.bitreverse.i8(i8) readnone30 31define i8 @g(i8 %a) {32; CHECK-LABEL: g:33; CHECK: // %bb.0:34; CHECK-NEXT: rbit w8, w035; CHECK-NEXT: lsr w0, w8, #2436; CHECK-NEXT: ret37 %b = call i8 @llvm.bitreverse.i8(i8 %a)38 ret i8 %b39}40 41declare i16 @llvm.bitreverse.i16(i16) readnone42 43define i16 @g_16(i16 %a) {44; CHECK-LABEL: g_16:45; CHECK: // %bb.0:46; CHECK-NEXT: rbit w8, w047; CHECK-NEXT: lsr w0, w8, #1648; CHECK-NEXT: ret49 %b = call i16 @llvm.bitreverse.i16(i16 %a)50 ret i16 %b51}52 53declare i32 @llvm.bitreverse.i32(i32) readnone54 55define i32 @g_32(i32 %a) {56; CHECK-LABEL: g_32:57; CHECK: // %bb.0:58; CHECK-NEXT: rbit w0, w059; CHECK-NEXT: ret60 %b = call i32 @llvm.bitreverse.i32(i32 %a)61 ret i32 %b62}63 64declare i64 @llvm.bitreverse.i64(i64) readnone65 66define i64 @g_64(i64 %a) {67; CHECK-LABEL: g_64:68; CHECK: // %bb.0:69; CHECK-NEXT: rbit x0, x070; CHECK-NEXT: ret71 %b = call i64 @llvm.bitreverse.i64(i64 %a)72 ret i64 %b73}74 75declare i128 @llvm.bitreverse.i128(i128) readnone76 77define i128 @g_128(i128 %a) {78; CHECK-LABEL: g_128:79; CHECK: // %bb.0:80; CHECK-NEXT: rbit x8, x181; CHECK-NEXT: rbit x1, x082; CHECK-NEXT: mov x0, x883; CHECK-NEXT: ret84 %b = call i128 @llvm.bitreverse.i128(i128 %a)85 ret i128 %b86}87 88declare <16 x i3> @llvm.bitreverse.v16i3(<16 x i3>) readnone89 90define <16 x i3> @g_vec_16x3(<16 x i3> %a) {91; CHECK-LABEL: g_vec_16x3:92; CHECK: // %bb.0:93; CHECK-NEXT: rbit v0.16b, v0.16b94; CHECK-NEXT: ushr v0.16b, v0.16b, #595; CHECK-NEXT: ret96 %b = call <16 x i3> @llvm.bitreverse.v16i3(<16 x i3> %a)97 ret <16 x i3> %b98}99 100declare <16 x i4> @llvm.bitreverse.v16i4(<16 x i4>) readnone101 102define <16 x i4> @g_vec_16x4(<16 x i4> %a) {103; CHECK-LABEL: g_vec_16x4:104; CHECK: // %bb.0:105; CHECK-NEXT: rbit v0.16b, v0.16b106; CHECK-NEXT: ushr v0.16b, v0.16b, #4107; CHECK-NEXT: ret108 %b = call <16 x i4> @llvm.bitreverse.v16i4(<16 x i4> %a)109 ret <16 x i4> %b110}111 112declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone113 114define <8 x i8> @g_vec(<8 x i8> %a) {115; CHECK-LABEL: g_vec:116; CHECK: // %bb.0:117; CHECK-NEXT: rbit v0.8b, v0.8b118; CHECK-NEXT: ret119 %b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)120 ret <8 x i8> %b121}122 123declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>) readnone124 125define <16 x i8> @g_vec_16x8(<16 x i8> %a) {126; CHECK-LABEL: g_vec_16x8:127; CHECK: // %bb.0:128; CHECK-NEXT: rbit v0.16b, v0.16b129; CHECK-NEXT: ret130 %b = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %a)131 ret <16 x i8> %b132}133 134declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>) readnone135 136define <32 x i8> @g_vec_32x8(<32 x i8> %a) {137; CHECK-LABEL: g_vec_32x8:138; CHECK: // %bb.0:139; CHECK-NEXT: rbit v0.16b, v0.16b140; CHECK-NEXT: rbit v1.16b, v1.16b141; CHECK-NEXT: ret142 %b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a)143 ret <32 x i8> %b144}145 146declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>) readnone147 148define <4 x i8> @g_vec_4x8(<4 x i8> %a) {149; SDAG-LABEL: g_vec_4x8:150; SDAG: // %bb.0:151; SDAG-NEXT: rev16 v0.8b, v0.8b152; SDAG-NEXT: rbit v0.8b, v0.8b153; SDAG-NEXT: ushr v0.4h, v0.4h, #8154; SDAG-NEXT: ret155;156; GISEL-LABEL: g_vec_4x8:157; GISEL: // %bb.0:158; GISEL-NEXT: uzp1 v0.8b, v0.8b, v0.8b159; GISEL-NEXT: rbit v0.8b, v0.8b160; GISEL-NEXT: ushll v0.8h, v0.8b, #0161; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0162; GISEL-NEXT: ret163 %b = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a)164 ret <4 x i8> %b165}166 167declare <9 x i8> @llvm.bitreverse.v9i8(<9 x i8>) readnone168 169define <9 x i8> @g_vec_9x8(<9 x i8> %a) {170; CHECK-LABEL: g_vec_9x8:171; CHECK: // %bb.0:172; CHECK-NEXT: rbit v0.16b, v0.16b173; CHECK-NEXT: ret174 %b = call <9 x i8> @llvm.bitreverse.v9i8(<9 x i8> %a)175 ret <9 x i8> %b176}177 178declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>) readnone179 180define <4 x i16> @g_vec_4x16(<4 x i16> %a) {181; CHECK-LABEL: g_vec_4x16:182; CHECK: // %bb.0:183; CHECK-NEXT: rev16 v0.8b, v0.8b184; CHECK-NEXT: rbit v0.8b, v0.8b185; CHECK-NEXT: ret186 %b = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a)187 ret <4 x i16> %b188}189 190declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>) readnone191 192define <8 x i16> @g_vec_8x16(<8 x i16> %a) {193; CHECK-LABEL: g_vec_8x16:194; CHECK: // %bb.0:195; CHECK-NEXT: rev16 v0.16b, v0.16b196; CHECK-NEXT: rbit v0.16b, v0.16b197; CHECK-NEXT: ret198 %b = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)199 ret <8 x i16> %b200}201 202declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>) readnone203 204define <16 x i16> @g_vec_16x16(<16 x i16> %a) {205; CHECK-LABEL: g_vec_16x16:206; CHECK: // %bb.0:207; CHECK-NEXT: rev16 v0.16b, v0.16b208; CHECK-NEXT: rev16 v1.16b, v1.16b209; CHECK-NEXT: rbit v0.16b, v0.16b210; CHECK-NEXT: rbit v1.16b, v1.16b211; CHECK-NEXT: ret212 %b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)213 ret <16 x i16> %b214}215 216declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) readnone217 218define <2 x i32> @g_vec_2x32(<2 x i32> %a) {219; CHECK-LABEL: g_vec_2x32:220; CHECK: // %bb.0:221; CHECK-NEXT: rev32 v0.8b, v0.8b222; CHECK-NEXT: rbit v0.8b, v0.8b223; CHECK-NEXT: ret224 %b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)225 ret <2 x i32> %b226}227 228declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) readnone229 230define <4 x i32> @g_vec_4x32(<4 x i32> %a) {231; CHECK-LABEL: g_vec_4x32:232; CHECK: // %bb.0:233; CHECK-NEXT: rev32 v0.16b, v0.16b234; CHECK-NEXT: rbit v0.16b, v0.16b235; CHECK-NEXT: ret236 %b = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)237 ret <4 x i32> %b238}239 240declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>) readnone241 242define <8 x i32> @g_vec_8x32(<8 x i32> %a) {243; CHECK-LABEL: g_vec_8x32:244; CHECK: // %bb.0:245; CHECK-NEXT: rev32 v0.16b, v0.16b246; CHECK-NEXT: rev32 v1.16b, v1.16b247; CHECK-NEXT: rbit v0.16b, v0.16b248; CHECK-NEXT: rbit v1.16b, v1.16b249; CHECK-NEXT: ret250 %b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)251 ret <8 x i32> %b252}253 254declare <1 x i64> @llvm.bitreverse.v1i64(<1 x i64>) readnone255 256define <1 x i64> @g_vec_1x64(<1 x i64> %a) {257; SDAG-LABEL: g_vec_1x64:258; SDAG: // %bb.0:259; SDAG-NEXT: rev64 v0.8b, v0.8b260; SDAG-NEXT: rbit v0.8b, v0.8b261; SDAG-NEXT: ret262;263; GISEL-LABEL: g_vec_1x64:264; GISEL: // %bb.0:265; GISEL-NEXT: fmov x8, d0266; GISEL-NEXT: rbit x8, x8267; GISEL-NEXT: fmov d0, x8268; GISEL-NEXT: ret269 %b = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %a)270 ret <1 x i64> %b271}272 273declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) readnone274 275define <2 x i64> @g_vec_2x64(<2 x i64> %a) {276; CHECK-LABEL: g_vec_2x64:277; CHECK: // %bb.0:278; CHECK-NEXT: rev64 v0.16b, v0.16b279; CHECK-NEXT: rbit v0.16b, v0.16b280; CHECK-NEXT: ret281 %b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)282 ret <2 x i64> %b283}284 285declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) readnone286 287define <4 x i64> @g_vec_4x64(<4 x i64> %a) {288; CHECK-LABEL: g_vec_4x64:289; CHECK: // %bb.0:290; CHECK-NEXT: rev64 v0.16b, v0.16b291; CHECK-NEXT: rev64 v1.16b, v1.16b292; CHECK-NEXT: rbit v0.16b, v0.16b293; CHECK-NEXT: rbit v1.16b, v1.16b294; CHECK-NEXT: ret295 %b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)296 ret <4 x i64> %b297}298 299declare <2 x i128> @llvm.bitreverse.v2i128(<2 x i128>) readnone300 301define <2 x i128> @g_vec_2x128(<2 x i128> %a) {302; CHECK-LABEL: g_vec_2x128:303; CHECK: // %bb.0:304; CHECK-NEXT: rbit x8, x1305; CHECK-NEXT: rbit x9, x3306; CHECK-NEXT: rbit x1, x0307; CHECK-NEXT: rbit x3, x2308; CHECK-NEXT: mov x0, x8309; CHECK-NEXT: mov x2, x9310; CHECK-NEXT: ret311 %b = call <2 x i128> @llvm.bitreverse.v2i128(<2 x i128> %a)312 ret <2 x i128> %b313}314