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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s3define i32 @test_asm_length(i32 %in) {4 ; It would be more natural to use just one "tbnz %false" here, but if the5 ; number of instructions in the asm is counted reasonably, that block is out6 ; of the limited range we gave tbz. So branch relaxation has to invert the7 ; condition.8; CHECK-LABEL: test_asm_length:9; CHECK: ; %bb.0:10; CHECK-NEXT: tbz w0, #0, LBB0_211; CHECK-NEXT: ; %bb.1:12; CHECK-NEXT: mov w0, wzr13; CHECK-NEXT: ret14; CHECK-NEXT: LBB0_2: ; %true15; CHECK-NEXT: mov w0, #416; CHECK-NEXT: ; InlineAsm Start17; CHECK-NEXT: nop18; CHECK-NEXT: nop19; CHECK-NEXT: nop20; CHECK-NEXT: nop21; CHECK-NEXT: nop22; CHECK-NEXT: nop23; CHECK-NEXT: ; InlineAsm End24; CHECK-NEXT: ret25 %val = and i32 %in, 126 %tst = icmp eq i32 %val, 027 br i1 %tst, label %true, label %false28 29true:30 call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()31 ret i32 432 33false:34 ret i32 035}36