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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2 3; RUN: llc -mtriple=aarch64-linux-gnu %s -o - -verify-machineinstrs \4; RUN: -start-before=aarch64-isel -stop-after=finalize-isel \5; RUN: -global-isel=0 -fast-isel=0 | FileCheck %s6 7; This file was initially generated via:8; $ opt -S -callbrprepare llvm/test/CodeGen/AArch64/callbr-prepare.ll -o \9; llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll10 11; TODO: should we remove test cases that don't use landingpad intrinsic?12; They're not interesting IMO.13 14; Removed is the test case for x86 machine specific physreg constraints.15 16define i32 @test0() {17 ; CHECK-LABEL: name: test018 ; CHECK: bb.0.entry:19 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %523 ; CHECK-NEXT: B %bb.224 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: bb.1.entry.indirect_crit_edge (inlineasm-br-indirect-target):26 ; CHECK-NEXT: successors: %bb.5(0x80000000)27 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %529 ; CHECK-NEXT: B %bb.530 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: bb.2.direct:32 ; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.3(0x00000000)33 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %7, 13 /* imm */, %bb.335 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %736 ; CHECK-NEXT: B %bb.437 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: bb.3.direct.indirect_crit_edge (inlineasm-br-indirect-target):39 ; CHECK-NEXT: successors: %bb.5(0x80000000)40 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY %742 ; CHECK-NEXT: B %bb.543 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: bb.4.direct2:45 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr46 ; CHECK-NEXT: $w0 = COPY [[COPY4]]47 ; CHECK-NEXT: RET_ReallyLR implicit $w048 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: bb.5.indirect:50 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY3]], %bb.351 ; CHECK-NEXT: $w0 = COPY [[PHI]]52 ; CHECK-NEXT: RET_ReallyLR implicit $w053entry:54 %out = callbr i32 asm "# $0", "=r,!i"()55 to label %direct [label %entry.indirect_crit_edge]56 57entry.indirect_crit_edge: ; preds = %entry58 %0 = call i32 @llvm.callbr.landingpad.i32(i32 %out)59 br label %indirect60 61direct: ; preds = %entry62 %out2 = callbr i32 asm "# $0", "=r,!i"()63 to label %direct2 [label %direct.indirect_crit_edge]64 65direct.indirect_crit_edge: ; preds = %direct66 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %out2)67 br label %indirect68 69direct2: ; preds = %direct70 ret i32 071 72indirect: ; preds = %direct.indirect_crit_edge, %entry.indirect_crit_edge73 %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ]74 ret i32 %out375}76 77define i32 @dont_split0() {78 ; CHECK-LABEL: name: dont_split079 ; CHECK: bb.0.entry:80 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)81 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.283 ; CHECK-NEXT: B %bb.184 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: bb.1.x:86 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4287 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]88 ; CHECK-NEXT: RET_ReallyLR implicit $w089 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: bb.2.y (inlineasm-br-indirect-target):91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $wzr92 ; CHECK-NEXT: $w0 = COPY [[COPY]]93 ; CHECK-NEXT: RET_ReallyLR implicit $w094entry:95 callbr void asm "", "!i"()96 to label %x [label %y]97 98x: ; preds = %entry99 ret i32 42100 101y: ; preds = %entry102 ret i32 0103}104 105define i32 @dont_split1() {106 ; CHECK-LABEL: name: dont_split1107 ; CHECK: bb.0.entry:108 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %1112 ; CHECK-NEXT: B %bb.1113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: bb.1.x:115 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42116 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]117 ; CHECK-NEXT: RET_ReallyLR implicit $w0118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: bb.2.y (inlineasm-br-indirect-target):120 ; CHECK-NEXT: $w0 = COPY %1121 ; CHECK-NEXT: RET_ReallyLR implicit $w0122entry:123 %0 = callbr i32 asm "", "=r,!i"()124 to label %x [label %y]125 126x: ; preds = %entry127 ret i32 42128 129y: ; preds = %entry130 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)131 ret i32 %1132}133 134define i32 @dont_split2() {135 ; CHECK-LABEL: name: dont_split2136 ; CHECK: bb.0.entry:137 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]141 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2142 ; CHECK-NEXT: B %bb.1143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: bb.1.x:145 ; CHECK-NEXT: successors: %bb.2(0x80000000)146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr148 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: bb.2.y (inlineasm-br-indirect-target):151 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY2]], %bb.1152 ; CHECK-NEXT: $w0 = COPY [[PHI]]153 ; CHECK-NEXT: RET_ReallyLR implicit $w0154entry:155 callbr void asm "", "!i"()156 to label %x [label %y]157 158x: ; preds = %entry159 br label %y160 161y: ; preds = %x, %entry162 %0 = phi i32 [ 0, %x ], [ 42, %entry ]163 ret i32 %0164}165 166define i32 @dont_split3() {167 ; CHECK-LABEL: name: dont_split3168 ; CHECK: bb.0.entry:169 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2172 ; CHECK-NEXT: B %bb.1173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: bb.1.x:175 ; CHECK-NEXT: successors: %bb.2(0x80000000)176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: bb.2.v (inlineasm-br-indirect-target):178 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42179 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]180 ; CHECK-NEXT: RET_ReallyLR implicit $w0181entry:182 %0 = callbr i32 asm "", "=r,!i"()183 to label %x [label %v]184 185x: ; preds = %entry186 br label %v187 188v: ; preds = %x, %entry189 ret i32 42190}191 192define i32 @split_me0() {193 ; CHECK-LABEL: name: split_me0194 ; CHECK: bb.0.entry:195 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)196 ; CHECK-NEXT: {{ $}}197 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1198 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3199 ; CHECK-NEXT: B %bb.2200 ; CHECK-NEXT: {{ $}}201 ; CHECK-NEXT: bb.1.entry.y_crit_edge (inlineasm-br-indirect-target):202 ; CHECK-NEXT: successors: %bb.3(0x80000000)203 ; CHECK-NEXT: {{ $}}204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3205 ; CHECK-NEXT: B %bb.3206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: bb.2.x:208 ; CHECK-NEXT: successors: %bb.3(0x80000000)209 ; CHECK-NEXT: {{ $}}210 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42211 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: bb.3.y:214 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2215 ; CHECK-NEXT: $w0 = COPY [[PHI]]216 ; CHECK-NEXT: RET_ReallyLR implicit $w0217entry:218 %0 = callbr i32 asm "", "=r,!i"()219 to label %x [label %entry.y_crit_edge]220 221entry.y_crit_edge: ; preds = %entry222 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)223 br label %y224 225x: ; preds = %entry226 br label %y227 228y: ; preds = %entry.y_crit_edge, %x229 %2 = phi i32 [ %1, %entry.y_crit_edge ], [ 42, %x ]230 ret i32 %2231}232 233define i32 @split_me1(i1 %z) {234 ; CHECK-LABEL: name: split_me1235 ; CHECK: bb.0.entry:236 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)237 ; CHECK-NEXT: liveins: $w0238 ; CHECK-NEXT: {{ $}}239 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0240 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32all = IMPLICIT_DEF241 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.4242 ; CHECK-NEXT: B %bb.1243 ; CHECK-NEXT: {{ $}}244 ; CHECK-NEXT: bb.1.w:245 ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000)246 ; CHECK-NEXT: {{ $}}247 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2248 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %5249 ; CHECK-NEXT: B %bb.3250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: bb.2.w.v_crit_edge (inlineasm-br-indirect-target):252 ; CHECK-NEXT: successors: %bb.4(0x80000000)253 ; CHECK-NEXT: {{ $}}254 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %5255 ; CHECK-NEXT: B %bb.4256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: bb.3.x:258 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42259 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]260 ; CHECK-NEXT: RET_ReallyLR implicit $w0261 ; CHECK-NEXT: {{ $}}262 ; CHECK-NEXT: bb.4.v:263 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[DEF]], %bb.0, [[COPY2]], %bb.2264 ; CHECK-NEXT: $w0 = COPY [[PHI]]265 ; CHECK-NEXT: RET_ReallyLR implicit $w0266entry:267 br i1 %z, label %w, label %v268 269w: ; preds = %entry270 %0 = callbr i32 asm "", "=r,!i,!i"()271 to label %x [label %w.v_crit_edge, label %w.v_crit_edge]272 273w.v_crit_edge: ; preds = %w, %w274 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)275 br label %v276 277x: ; preds = %w278 ret i32 42279 280v: ; preds = %w.v_crit_edge, %entry281 %2 = phi i32 [ %1, %w.v_crit_edge ], [ undef, %entry ]282 ret i32 %2283}284 285define i32 @split_me2(i1 %z) {286 ; CHECK-LABEL: name: split_me2287 ; CHECK: bb.0.entry:288 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)289 ; CHECK-NEXT: liveins: $w0290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0292 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42293 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]294 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.4295 ; CHECK-NEXT: B %bb.1296 ; CHECK-NEXT: {{ $}}297 ; CHECK-NEXT: bb.1.w:298 ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000)299 ; CHECK-NEXT: {{ $}}300 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2301 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %6302 ; CHECK-NEXT: B %bb.3303 ; CHECK-NEXT: {{ $}}304 ; CHECK-NEXT: bb.2.w.v_crit_edge (inlineasm-br-indirect-target):305 ; CHECK-NEXT: successors: %bb.4(0x80000000)306 ; CHECK-NEXT: {{ $}}307 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY %6308 ; CHECK-NEXT: B %bb.4309 ; CHECK-NEXT: {{ $}}310 ; CHECK-NEXT: bb.3.x:311 ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 42312 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm1]]313 ; CHECK-NEXT: RET_ReallyLR implicit $w0314 ; CHECK-NEXT: {{ $}}315 ; CHECK-NEXT: bb.4.v:316 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.0, [[COPY3]], %bb.2317 ; CHECK-NEXT: $w0 = COPY [[PHI]]318 ; CHECK-NEXT: RET_ReallyLR implicit $w0319entry:320 br i1 %z, label %w, label %v321 322w: ; preds = %entry323 %0 = callbr i32 asm "", "=r,!i,!i"()324 to label %x [label %w.v_crit_edge, label %w.v_crit_edge]325 326w.v_crit_edge: ; preds = %w, %w327 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)328 br label %v329 330x: ; preds = %w331 ret i32 42332 333v: ; preds = %w.v_crit_edge, %entry334 %2 = phi i32 [ %1, %w.v_crit_edge ], [ 42, %entry ]335 ret i32 %2336}337 338define i32 @dont_split4() {339 ; CHECK-LABEL: name: dont_split4340 ; CHECK: bb.0.entry:341 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)342 ; CHECK-NEXT: {{ $}}343 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2344 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3345 ; CHECK-NEXT: B %bb.1346 ; CHECK-NEXT: {{ $}}347 ; CHECK-NEXT: bb.1.x:348 ; CHECK-NEXT: successors: %bb.3(0x80000000)349 ; CHECK-NEXT: {{ $}}350 ; CHECK-NEXT: B %bb.3351 ; CHECK-NEXT: {{ $}}352 ; CHECK-NEXT: bb.2.y (inlineasm-br-indirect-target):353 ; CHECK-NEXT: successors: %bb.3(0x80000000)354 ; CHECK-NEXT: {{ $}}355 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3356 ; CHECK-NEXT: {{ $}}357 ; CHECK-NEXT: bb.3.out:358 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.2, [[COPY]], %bb.1359 ; CHECK-NEXT: $w0 = COPY [[PHI]]360 ; CHECK-NEXT: RET_ReallyLR implicit $w0361entry:362 %0 = callbr i32 asm "", "=r,!i"()363 to label %x [label %y]364 365x: ; preds = %entry366 br label %out367 368y: ; preds = %entry369 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)370 br label %out371 372out: ; preds = %y, %x373 %2 = phi i32 [ %1, %y ], [ %0, %x ]374 ret i32 %2375}376 377define i32 @dont_split5() {378 ; CHECK-LABEL: name: dont_split5379 ; CHECK: bb.0.entry:380 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)381 ; CHECK-NEXT: {{ $}}382 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1383 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3384 ; CHECK-NEXT: B %bb.2385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: bb.1.y (inlineasm-br-indirect-target):387 ; CHECK-NEXT: successors: %bb.2(0x80000000)388 ; CHECK-NEXT: {{ $}}389 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3390 ; CHECK-NEXT: {{ $}}391 ; CHECK-NEXT: bb.2.out:392 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1393 ; CHECK-NEXT: $w0 = COPY [[PHI]]394 ; CHECK-NEXT: RET_ReallyLR implicit $w0395entry:396 %0 = callbr i32 asm "", "=r,!i"()397 to label %out [label %y]398 399y: ; preds = %entry400 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)401 br label %out402 403out: ; preds = %y, %entry404 %2 = phi i32 [ %1, %y ], [ %0, %entry ]405 ret i32 %2406}407 408define i32 @split_me3() {409 ; CHECK-LABEL: name: split_me3410 ; CHECK: bb.0.entry:411 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)412 ; CHECK-NEXT: {{ $}}413 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1414 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3415 ; CHECK-NEXT: B %bb.2416 ; CHECK-NEXT: {{ $}}417 ; CHECK-NEXT: bb.1.entry.out_crit_edge (inlineasm-br-indirect-target):418 ; CHECK-NEXT: successors: %bb.3(0x80000000)419 ; CHECK-NEXT: {{ $}}420 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3421 ; CHECK-NEXT: B %bb.3422 ; CHECK-NEXT: {{ $}}423 ; CHECK-NEXT: bb.2.y:424 ; CHECK-NEXT: successors: %bb.3(0x80000000)425 ; CHECK-NEXT: {{ $}}426 ; CHECK-NEXT: bb.3.out:427 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2428 ; CHECK-NEXT: $w0 = COPY [[PHI]]429 ; CHECK-NEXT: RET_ReallyLR implicit $w0430entry:431 %0 = callbr i32 asm "", "=r,!i"()432 to label %y [label %entry.out_crit_edge]433 434entry.out_crit_edge: ; preds = %entry435 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)436 br label %out437 438y: ; preds = %entry439 br label %out440 441out: ; preds = %entry.out_crit_edge, %y442 %2 = phi i32 [ %1, %entry.out_crit_edge ], [ %0, %y ]443 ret i32 %2444}445 446define i32 @dont_split6(i32 %0) {447 ; CHECK-LABEL: name: dont_split6448 ; CHECK: bb.0.entry:449 ; CHECK-NEXT: successors: %bb.1(0x80000000)450 ; CHECK-NEXT: liveins: $w0451 ; CHECK-NEXT: {{ $}}452 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0453 ; CHECK-NEXT: {{ $}}454 ; CHECK-NEXT: bb.1.loop:455 ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000)456 ; CHECK-NEXT: {{ $}}457 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %2, %bb.2458 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY [[PHI]]459 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2460 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %4461 ; CHECK-NEXT: B %bb.3462 ; CHECK-NEXT: {{ $}}463 ; CHECK-NEXT: bb.2.loop.loop_crit_edge (inlineasm-br-indirect-target):464 ; CHECK-NEXT: successors: %bb.1(0x80000000)465 ; CHECK-NEXT: {{ $}}466 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY %4467 ; CHECK-NEXT: B %bb.1468 ; CHECK-NEXT: {{ $}}469 ; CHECK-NEXT: bb.3.exit:470 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr471 ; CHECK-NEXT: $w0 = COPY [[COPY4]]472 ; CHECK-NEXT: RET_ReallyLR implicit $w0473entry:474 br label %loop475 476loop: ; preds = %loop.loop_crit_edge, %entry477 %1 = phi i32 [ %0, %entry ], [ %3, %loop.loop_crit_edge ]478 %2 = callbr i32 asm "", "=r,0,!i"(i32 %1)479 to label %exit [label %loop.loop_crit_edge]480 481loop.loop_crit_edge: ; preds = %loop482 %3 = call i32 @llvm.callbr.landingpad.i32(i32 %2)483 br label %loop484 485exit: ; preds = %loop486 ret i32 0487}488 489define i32 @split_me4() {490 ; CHECK-LABEL: name: split_me4491 ; CHECK: bb.0.entry:492 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)493 ; CHECK-NEXT: {{ $}}494 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3496 ; CHECK-NEXT: B %bb.2497 ; CHECK-NEXT: {{ $}}498 ; CHECK-NEXT: bb.1.entry.same_crit_edge (inlineasm-br-indirect-target):499 ; CHECK-NEXT: successors: %bb.2(0x80000000)500 ; CHECK-NEXT: {{ $}}501 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3502 ; CHECK-NEXT: {{ $}}503 ; CHECK-NEXT: bb.2.same:504 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1505 ; CHECK-NEXT: $w0 = COPY [[PHI]]506 ; CHECK-NEXT: RET_ReallyLR implicit $w0507entry:508 %0 = callbr i32 asm "", "=r,!i"()509 to label %same [label %entry.same_crit_edge]510 511entry.same_crit_edge: ; preds = %entry512 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)513 br label %same514 515same: ; preds = %entry.same_crit_edge, %entry516 %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]517 ret i32 %2518}519 520define i32 @split_me5() {521 ; CHECK-LABEL: name: split_me5522 ; CHECK: bb.0.entry:523 ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)524 ; CHECK-NEXT: {{ $}}525 ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1526 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3527 ; CHECK-NEXT: B %bb.2528 ; CHECK-NEXT: {{ $}}529 ; CHECK-NEXT: bb.1.entry.same_crit_edge (inlineasm-br-indirect-target):530 ; CHECK-NEXT: successors: %bb.2(0x80000000)531 ; CHECK-NEXT: {{ $}}532 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3533 ; CHECK-NEXT: {{ $}}534 ; CHECK-NEXT: bb.2.same:535 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1536 ; CHECK-NEXT: $w0 = COPY [[PHI]]537 ; CHECK-NEXT: RET_ReallyLR implicit $w0538entry:539 %0 = callbr i32 asm "", "=r,!i"()540 to label %same [label %entry.same_crit_edge]541 542entry.same_crit_edge: ; preds = %entry543 %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)544 br label %same545 546same: ; preds = %entry.same_crit_edge, %entry547 %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]548 ret i32 %2549}550 551; Function Attrs: nounwind552declare i32 @llvm.callbr.landingpad.i32(i32) #0553 554; Function Attrs: nounwind555declare i64 @llvm.callbr.landingpad.i64(i64) #0556 557attributes #0 = { nounwind }558