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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s3 4; These tests make sure that the `cmp` instruction is rendered with an5; instruction that checks the sign bit of the original unextended data6; (%in) instead of the sign bit of the sign extended one that is7; created by the type legalization process.8;9; The tests are subdivided in tests that determine the sign bit10; looking through a `sign_extend_inreg` and tests that determine the11; sign bit looking through a `sign_extend`.12 13define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {14; CHECK-LABEL: f_i8_sign_extend_inreg:15; CHECK: // %bb.0: // %entry16; CHECK-NEXT: sxtb w8, w017; CHECK-NEXT: cmn w8, #118; CHECK-NEXT: csel w8, w1, w2, gt19; CHECK-NEXT: add w0, w8, w0, uxtb20; CHECK-NEXT: ret21entry:22 %cmp = icmp sgt i8 %in, -123 %ext = zext i8 %in to i3224 br i1 %cmp, label %A, label %B25 26A:27 %retA = add i32 %ext, %a28 ret i32 %retA29 30B:31 %retB = add i32 %ext, %b32 ret i32 %retB33}34 35define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {36; CHECK-LABEL: f_i16_sign_extend_inreg:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: sxth w8, w039; CHECK-NEXT: cmn w8, #140; CHECK-NEXT: csel w8, w1, w2, gt41; CHECK-NEXT: add w0, w8, w0, uxth42; CHECK-NEXT: ret43entry:44 %cmp = icmp sgt i16 %in, -145 %ext = zext i16 %in to i3246 br i1 %cmp, label %A, label %B47 48A:49 %retA = add i32 %ext, %a50 ret i32 %retA51 52B:53 %retB = add i32 %ext, %b54 ret i32 %retB55}56 57define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {58; CHECK-LABEL: f_i32_sign_extend_inreg:59; CHECK: // %bb.0: // %entry60; CHECK-NEXT: cmn w0, #161; CHECK-NEXT: csel x8, x1, x2, gt62; CHECK-NEXT: add x0, x8, w0, uxtw63; CHECK-NEXT: ret64entry:65 %cmp = icmp sgt i32 %in, -166 %ext = zext i32 %in to i6467 br i1 %cmp, label %A, label %B68 69A:70 %retA = add i64 %ext, %a71 ret i64 %retA72 73B:74 %retB = add i64 %ext, %b75 ret i64 %retB76}77 78define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {79; CHECK-LABEL: g_i8_sign_extend_inreg:80; CHECK: // %bb.0: // %entry81; CHECK-NEXT: tst w0, #0x8082; CHECK-NEXT: csel w8, w1, w2, ne83; CHECK-NEXT: add w0, w8, w0, uxtb84; CHECK-NEXT: ret85entry:86 %cmp = icmp slt i8 %in, 087 %ext = zext i8 %in to i3288 br i1 %cmp, label %A, label %B89 90A:91 %retA = add i32 %ext, %a92 ret i32 %retA93 94B:95 %retB = add i32 %ext, %b96 ret i32 %retB97}98 99define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {100; CHECK-LABEL: g_i16_sign_extend_inreg:101; CHECK: // %bb.0: // %entry102; CHECK-NEXT: tst w0, #0x8000103; CHECK-NEXT: csel w8, w1, w2, ne104; CHECK-NEXT: add w0, w8, w0, uxth105; CHECK-NEXT: ret106entry:107 %cmp = icmp slt i16 %in, 0108 %ext = zext i16 %in to i32109 br i1 %cmp, label %A, label %B110 111A:112 %retA = add i32 %ext, %a113 ret i32 %retA114 115B:116 %retB = add i32 %ext, %b117 ret i32 %retB118}119 120define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {121; CHECK-LABEL: g_i32_sign_extend_inreg:122; CHECK: // %bb.0: // %entry123; CHECK-NEXT: cmp w0, #0124; CHECK-NEXT: csel x8, x1, x2, mi125; CHECK-NEXT: add x0, x8, w0, uxtw126; CHECK-NEXT: ret127entry:128 %cmp = icmp slt i32 %in, 0129 %ext = zext i32 %in to i64130 br i1 %cmp, label %A, label %B131 132A:133 %retA = add i64 %ext, %a134 ret i64 %retA135 136B:137 %retB = add i64 %ext, %b138 ret i64 %retB139}140 141define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {142; CHECK-LABEL: f_i32_sign_extend_i64:143; CHECK: // %bb.0: // %entry144; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0145; CHECK-NEXT: sxtw x8, w0146; CHECK-NEXT: cmn x8, #1147; CHECK-NEXT: csel x8, x1, x2, gt148; CHECK-NEXT: add x0, x8, w0, uxtw149; CHECK-NEXT: ret150entry:151 %inext = sext i32 %in to i64152 %cmp = icmp sgt i64 %inext, -1153 %ext = zext i32 %in to i64154 br i1 %cmp, label %A, label %B155 156A:157 %retA = add i64 %ext, %a158 ret i64 %retA159 160B:161 %retB = add i64 %ext, %b162 ret i64 %retB163}164 165define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {166; CHECK-LABEL: g_i32_sign_extend_i64:167; CHECK: // %bb.0: // %entry168; CHECK-NEXT: tst w0, #0x80000000169; CHECK-NEXT: csel x8, x1, x2, ne170; CHECK-NEXT: add x0, x8, w0, uxtw171; CHECK-NEXT: ret172entry:173 %inext = sext i32 %in to i64174 %cmp = icmp slt i64 %inext, 0175 %ext = zext i32 %in to i64176 br i1 %cmp, label %A, label %B177 178A:179 %retA = add i64 %ext, %a180 ret i64 %retA181 182B:183 %retB = add i64 %ext, %b184 ret i64 %retB185}186