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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; Ensure chains of comparisons produce chains of `ccmp`6 7; (x0 < x1) && (x2 > x3)8define i32 @cmp_and2(i32 %0, i32 %1, i32 %2, i32 %3) {9; CHECK-SD-LABEL: cmp_and2:10; CHECK-SD: // %bb.0:11; CHECK-SD-NEXT: cmp w0, w112; CHECK-SD-NEXT: ccmp w2, w3, #0, lo13; CHECK-SD-NEXT: cset w0, hi14; CHECK-SD-NEXT: ret15;16; CHECK-GI-LABEL: cmp_and2:17; CHECK-GI: // %bb.0:18; CHECK-GI-NEXT: cmp w0, w119; CHECK-GI-NEXT: cset w8, lo20; CHECK-GI-NEXT: cmp w2, w321; CHECK-GI-NEXT: cset w9, hi22; CHECK-GI-NEXT: and w0, w8, w923; CHECK-GI-NEXT: ret24 %5 = icmp ult i32 %0, %125 %6 = icmp ugt i32 %2, %326 %7 = select i1 %5, i1 %6, i1 false27 %8 = zext i1 %7 to i3228 ret i32 %829}30 31; (x0 < x1) && (x2 > x3) && (x4 != x5)32define i32 @cmp_and3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {33; CHECK-SD-LABEL: cmp_and3:34; CHECK-SD: // %bb.0:35; CHECK-SD-NEXT: cmp w0, w136; CHECK-SD-NEXT: ccmp w2, w3, #0, lo37; CHECK-SD-NEXT: ccmp w4, w5, #4, hi38; CHECK-SD-NEXT: cset w0, ne39; CHECK-SD-NEXT: ret40;41; CHECK-GI-LABEL: cmp_and3:42; CHECK-GI: // %bb.0:43; CHECK-GI-NEXT: cmp w0, w144; CHECK-GI-NEXT: cset w8, lo45; CHECK-GI-NEXT: cmp w2, w346; CHECK-GI-NEXT: cset w9, hi47; CHECK-GI-NEXT: cmp w4, w548; CHECK-GI-NEXT: and w8, w8, w949; CHECK-GI-NEXT: cset w9, ne50; CHECK-GI-NEXT: and w0, w8, w951; CHECK-GI-NEXT: ret52 %7 = icmp ult i32 %0, %153 %8 = icmp ugt i32 %2, %354 %9 = select i1 %7, i1 %8, i1 false55 %10 = icmp ne i32 %4, %556 %11 = select i1 %9, i1 %10, i1 false57 %12 = zext i1 %11 to i3258 ret i32 %1259}60 61; (x0 < x1) && (x2 > x3) && (x4 != x5) && (x6 == x7)62define i32 @cmp_and4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {63; CHECK-SD-LABEL: cmp_and4:64; CHECK-SD: // %bb.0:65; CHECK-SD-NEXT: cmp w2, w366; CHECK-SD-NEXT: ccmp w0, w1, #2, hi67; CHECK-SD-NEXT: ccmp w4, w5, #4, lo68; CHECK-SD-NEXT: ccmp w6, w7, #0, ne69; CHECK-SD-NEXT: cset w0, eq70; CHECK-SD-NEXT: ret71;72; CHECK-GI-LABEL: cmp_and4:73; CHECK-GI: // %bb.0:74; CHECK-GI-NEXT: cmp w2, w375; CHECK-GI-NEXT: cset w8, hi76; CHECK-GI-NEXT: cmp w0, w177; CHECK-GI-NEXT: cset w9, lo78; CHECK-GI-NEXT: cmp w4, w579; CHECK-GI-NEXT: cset w10, ne80; CHECK-GI-NEXT: cmp w6, w781; CHECK-GI-NEXT: and w8, w8, w982; CHECK-GI-NEXT: cset w11, eq83; CHECK-GI-NEXT: and w9, w10, w1184; CHECK-GI-NEXT: and w0, w8, w985; CHECK-GI-NEXT: ret86 %9 = icmp ugt i32 %2, %387 %10 = icmp ult i32 %0, %188 %11 = select i1 %9, i1 %10, i1 false89 %12 = icmp ne i32 %4, %590 %13 = select i1 %11, i1 %12, i1 false91 %14 = icmp eq i32 %6, %792 %15 = select i1 %13, i1 %14, i1 false93 %16 = zext i1 %15 to i3294 ret i32 %1695}96 97; (x0 < x1) || (x2 > x3)98define i32 @cmp_or2(i32 %0, i32 %1, i32 %2, i32 %3) {99; CHECK-SD-LABEL: cmp_or2:100; CHECK-SD: // %bb.0:101; CHECK-SD-NEXT: cmp w0, w1102; CHECK-SD-NEXT: ccmp w2, w3, #0, hs103; CHECK-SD-NEXT: cset w0, ne104; CHECK-SD-NEXT: ret105;106; CHECK-GI-LABEL: cmp_or2:107; CHECK-GI: // %bb.0:108; CHECK-GI-NEXT: cmp w0, w1109; CHECK-GI-NEXT: cset w8, lo110; CHECK-GI-NEXT: cmp w2, w3111; CHECK-GI-NEXT: cset w9, ne112; CHECK-GI-NEXT: orr w8, w8, w9113; CHECK-GI-NEXT: and w0, w8, #0x1114; CHECK-GI-NEXT: ret115 %5 = icmp ult i32 %0, %1116 %6 = icmp ne i32 %2, %3117 %7 = select i1 %5, i1 true, i1 %6118 %8 = zext i1 %7 to i32119 ret i32 %8120}121 122; (x0 < x1) || (x2 > x3) || (x4 != x5)123define i32 @cmp_or3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {124; CHECK-SD-LABEL: cmp_or3:125; CHECK-SD: // %bb.0:126; CHECK-SD-NEXT: cmp w0, w1127; CHECK-SD-NEXT: ccmp w2, w3, #2, hs128; CHECK-SD-NEXT: ccmp w4, w5, #0, ls129; CHECK-SD-NEXT: cset w0, ne130; CHECK-SD-NEXT: ret131;132; CHECK-GI-LABEL: cmp_or3:133; CHECK-GI: // %bb.0:134; CHECK-GI-NEXT: cmp w0, w1135; CHECK-GI-NEXT: cset w8, lo136; CHECK-GI-NEXT: cmp w2, w3137; CHECK-GI-NEXT: cset w9, hi138; CHECK-GI-NEXT: cmp w4, w5139; CHECK-GI-NEXT: orr w8, w8, w9140; CHECK-GI-NEXT: cset w9, ne141; CHECK-GI-NEXT: orr w8, w8, w9142; CHECK-GI-NEXT: and w0, w8, #0x1143; CHECK-GI-NEXT: ret144 %7 = icmp ult i32 %0, %1145 %8 = icmp ugt i32 %2, %3146 %9 = select i1 %7, i1 true, i1 %8147 %10 = icmp ne i32 %4, %5148 %11 = select i1 %9, i1 true, i1 %10149 %12 = zext i1 %11 to i32150 ret i32 %12151}152 153; (x0 < x1) || (x2 > x3) || (x4 != x5) || (x6 == x7)154define i32 @cmp_or4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {155; CHECK-SD-LABEL: cmp_or4:156; CHECK-SD: // %bb.0:157; CHECK-SD-NEXT: cmp w0, w1158; CHECK-SD-NEXT: ccmp w2, w3, #2, hs159; CHECK-SD-NEXT: ccmp w4, w5, #0, ls160; CHECK-SD-NEXT: ccmp w6, w7, #4, eq161; CHECK-SD-NEXT: cset w0, eq162; CHECK-SD-NEXT: ret163;164; CHECK-GI-LABEL: cmp_or4:165; CHECK-GI: // %bb.0:166; CHECK-GI-NEXT: cmp w0, w1167; CHECK-GI-NEXT: cset w8, lo168; CHECK-GI-NEXT: cmp w2, w3169; CHECK-GI-NEXT: cset w9, hi170; CHECK-GI-NEXT: cmp w4, w5171; CHECK-GI-NEXT: cset w10, ne172; CHECK-GI-NEXT: cmp w6, w7173; CHECK-GI-NEXT: orr w8, w8, w9174; CHECK-GI-NEXT: cset w11, eq175; CHECK-GI-NEXT: orr w9, w10, w11176; CHECK-GI-NEXT: orr w8, w8, w9177; CHECK-GI-NEXT: and w0, w8, #0x1178; CHECK-GI-NEXT: ret179 %9 = icmp ult i32 %0, %1180 %10 = icmp ugt i32 %2, %3181 %11 = select i1 %9, i1 true, i1 %10182 %12 = icmp ne i32 %4, %5183 %13 = select i1 %11, i1 true, i1 %12184 %14 = icmp eq i32 %6, %7185 %15 = select i1 %13, i1 true, i1 %14186 %16 = zext i1 %15 to i32187 ret i32 %16188}189 190; (x0 != 0) || (x1 != 0)191define i32 @true_or2(i32 %0, i32 %1) {192; CHECK-SD-LABEL: true_or2:193; CHECK-SD: // %bb.0:194; CHECK-SD-NEXT: orr w8, w0, w1195; CHECK-SD-NEXT: cmp w8, #0196; CHECK-SD-NEXT: cset w0, ne197; CHECK-SD-NEXT: ret198;199; CHECK-GI-LABEL: true_or2:200; CHECK-GI: // %bb.0:201; CHECK-GI-NEXT: cmp w0, #0202; CHECK-GI-NEXT: cset w8, ne203; CHECK-GI-NEXT: cmp w1, #0204; CHECK-GI-NEXT: cset w9, ne205; CHECK-GI-NEXT: orr w8, w8, w9206; CHECK-GI-NEXT: and w0, w8, #0x1207; CHECK-GI-NEXT: ret208 %3 = icmp ne i32 %0, 0209 %4 = icmp ne i32 %1, 0210 %5 = select i1 %3, i1 true, i1 %4211 %6 = zext i1 %5 to i32212 ret i32 %6213}214 215; (x0 != 0) || (x1 != 0) || (x2 != 0)216define i32 @true_or3(i32 %0, i32 %1, i32 %2) {217; CHECK-SD-LABEL: true_or3:218; CHECK-SD: // %bb.0:219; CHECK-SD-NEXT: orr w8, w0, w1220; CHECK-SD-NEXT: orr w8, w8, w2221; CHECK-SD-NEXT: cmp w8, #0222; CHECK-SD-NEXT: cset w0, ne223; CHECK-SD-NEXT: ret224;225; CHECK-GI-LABEL: true_or3:226; CHECK-GI: // %bb.0:227; CHECK-GI-NEXT: cmp w0, #0228; CHECK-GI-NEXT: cset w8, ne229; CHECK-GI-NEXT: cmp w1, #0230; CHECK-GI-NEXT: cset w9, ne231; CHECK-GI-NEXT: cmp w2, #0232; CHECK-GI-NEXT: orr w8, w8, w9233; CHECK-GI-NEXT: cset w9, ne234; CHECK-GI-NEXT: orr w8, w8, w9235; CHECK-GI-NEXT: and w0, w8, #0x1236; CHECK-GI-NEXT: ret237 %4 = icmp ne i32 %0, 0238 %5 = icmp ne i32 %1, 0239 %6 = select i1 %4, i1 true, i1 %5240 %7 = icmp ne i32 %2, 0241 %8 = select i1 %6, i1 true, i1 %7242 %9 = zext i1 %8 to i32243 ret i32 %9244}245 246; (b > -3 && a < c)247define i32 @neg_range_int(i32 %a, i32 %b, i32 %c) {248; CHECK-LABEL: neg_range_int:249; CHECK: // %bb.0:250; CHECK-NEXT: cmp w0, w2251; CHECK-NEXT: ccmn w1, #3, #4, lt252; CHECK-NEXT: csel w0, w1, w0, gt253; CHECK-NEXT: ret254 %cmp = icmp sgt i32 %b, -3255 %cmp1 = icmp slt i32 %a, %c256 %or.cond = and i1 %cmp, %cmp1257 %retval.0 = select i1 %or.cond, i32 %b, i32 %a258 ret i32 %retval.0259}260 261; (b > -(d | 1) && a < c)262define i32 @neg_range_int_comp(i32 %a, i32 %b, i32 %c, i32 %d) {263; CHECK-SD-LABEL: neg_range_int_comp:264; CHECK-SD: // %bb.0:265; CHECK-SD-NEXT: orr w8, w3, #0x1266; CHECK-SD-NEXT: cmp w0, w2267; CHECK-SD-NEXT: ccmn w1, w8, #4, lt268; CHECK-SD-NEXT: csel w0, w1, w0, gt269; CHECK-SD-NEXT: ret270;271; CHECK-GI-LABEL: neg_range_int_comp:272; CHECK-GI: // %bb.0:273; CHECK-GI-NEXT: orr w8, w3, #0x1274; CHECK-GI-NEXT: cmp w0, w2275; CHECK-GI-NEXT: neg w8, w8276; CHECK-GI-NEXT: ccmp w1, w8, #4, lt277; CHECK-GI-NEXT: csel w0, w1, w0, gt278; CHECK-GI-NEXT: ret279 %dor = or i32 %d, 1280 %negd = sub i32 0, %dor281 %cmp = icmp sgt i32 %b, %negd282 %cmp1 = icmp slt i32 %a, %c283 %or.cond = and i1 %cmp, %cmp1284 %retval.0 = select i1 %or.cond, i32 %b, i32 %a285 ret i32 %retval.0286}287 288; (b >u -(d | 1) && a < c)289define i32 @neg_range_int_comp_u(i32 %a, i32 %b, i32 %c, i32 %d) {290; CHECK-SD-LABEL: neg_range_int_comp_u:291; CHECK-SD: // %bb.0:292; CHECK-SD-NEXT: orr w8, w3, #0x1293; CHECK-SD-NEXT: cmp w0, w2294; CHECK-SD-NEXT: ccmn w1, w8, #0, lt295; CHECK-SD-NEXT: csel w0, w1, w0, hi296; CHECK-SD-NEXT: ret297;298; CHECK-GI-LABEL: neg_range_int_comp_u:299; CHECK-GI: // %bb.0:300; CHECK-GI-NEXT: orr w8, w3, #0x1301; CHECK-GI-NEXT: cmp w0, w2302; CHECK-GI-NEXT: neg w8, w8303; CHECK-GI-NEXT: ccmp w1, w8, #0, lt304; CHECK-GI-NEXT: csel w0, w1, w0, hi305; CHECK-GI-NEXT: ret306 %dor = or i32 %d, 1307 %negd = sub i32 0, %dor308 %cmp = icmp ugt i32 %b, %negd309 %cmp1 = icmp slt i32 %a, %c310 %or.cond = and i1 %cmp, %cmp1311 %retval.0 = select i1 %or.cond, i32 %b, i32 %a312 ret i32 %retval.0313}314 315; (b > -(d | 1) && a u < c)316define i32 @neg_range_int_comp_ua(i32 %a, i32 %b, i32 %c, i32 %d) {317; CHECK-SD-LABEL: neg_range_int_comp_ua:318; CHECK-SD: // %bb.0:319; CHECK-SD-NEXT: orr w8, w3, #0x1320; CHECK-SD-NEXT: cmp w0, w2321; CHECK-SD-NEXT: ccmn w1, w8, #4, lo322; CHECK-SD-NEXT: csel w0, w1, w0, gt323; CHECK-SD-NEXT: ret324;325; CHECK-GI-LABEL: neg_range_int_comp_ua:326; CHECK-GI: // %bb.0:327; CHECK-GI-NEXT: orr w8, w3, #0x1328; CHECK-GI-NEXT: cmp w0, w2329; CHECK-GI-NEXT: neg w8, w8330; CHECK-GI-NEXT: ccmp w1, w8, #4, lo331; CHECK-GI-NEXT: csel w0, w1, w0, gt332; CHECK-GI-NEXT: ret333 %dor = or i32 %d, 1334 %negd = sub i32 0, %dor335 %cmp = icmp sgt i32 %b, %negd336 %cmp1 = icmp ult i32 %a, %c337 %or.cond = and i1 %cmp, %cmp1338 %retval.0 = select i1 %or.cond, i32 %b, i32 %a339 ret i32 %retval.0340}341 342; (b <= -3 && a > c)343define i32 @neg_range_int_2(i32 %a, i32 %b, i32 %c) {344; CHECK-SD-LABEL: neg_range_int_2:345; CHECK-SD: // %bb.0:346; CHECK-SD-NEXT: cmp w0, w2347; CHECK-SD-NEXT: ccmn w1, #4, #4, gt348; CHECK-SD-NEXT: csel w0, w1, w0, gt349; CHECK-SD-NEXT: ret350;351; CHECK-GI-LABEL: neg_range_int_2:352; CHECK-GI: // %bb.0:353; CHECK-GI-NEXT: cmp w0, w2354; CHECK-GI-NEXT: ccmn w1, #3, #8, gt355; CHECK-GI-NEXT: csel w0, w1, w0, ge356; CHECK-GI-NEXT: ret357 %cmp = icmp sge i32 %b, -3358 %cmp1 = icmp sgt i32 %a, %c359 %or.cond = and i1 %cmp, %cmp1360 %retval.0 = select i1 %or.cond, i32 %b, i32 %a361 ret i32 %retval.0362}363 364; (b < -(d | 1) && a >= c)365define i32 @neg_range_int_comp2(i32 %a, i32 %b, i32 %c, i32 %d) {366; CHECK-SD-LABEL: neg_range_int_comp2:367; CHECK-SD: // %bb.0:368; CHECK-SD-NEXT: orr w8, w3, #0x1369; CHECK-SD-NEXT: cmp w0, w2370; CHECK-SD-NEXT: ccmn w1, w8, #0, ge371; CHECK-SD-NEXT: csel w0, w1, w0, lt372; CHECK-SD-NEXT: ret373;374; CHECK-GI-LABEL: neg_range_int_comp2:375; CHECK-GI: // %bb.0:376; CHECK-GI-NEXT: orr w8, w3, #0x1377; CHECK-GI-NEXT: cmp w0, w2378; CHECK-GI-NEXT: neg w8, w8379; CHECK-GI-NEXT: ccmp w1, w8, #0, ge380; CHECK-GI-NEXT: csel w0, w1, w0, lt381; CHECK-GI-NEXT: ret382 %dor = or i32 %d, 1383 %negd = sub i32 0, %dor384 %cmp = icmp slt i32 %b, %negd385 %cmp1 = icmp sge i32 %a, %c386 %or.cond = and i1 %cmp, %cmp1387 %retval.0 = select i1 %or.cond, i32 %b, i32 %a388 ret i32 %retval.0389}390 391; (b <u -(d | 1) && a > c)392define i32 @neg_range_int_comp_u2(i32 %a, i32 %b, i32 %c, i32 %d) {393; CHECK-SD-LABEL: neg_range_int_comp_u2:394; CHECK-SD: // %bb.0:395; CHECK-SD-NEXT: orr w8, w3, #0x1396; CHECK-SD-NEXT: cmp w0, w2397; CHECK-SD-NEXT: ccmn w1, w8, #2, gt398; CHECK-SD-NEXT: csel w0, w1, w0, lo399; CHECK-SD-NEXT: ret400;401; CHECK-GI-LABEL: neg_range_int_comp_u2:402; CHECK-GI: // %bb.0:403; CHECK-GI-NEXT: orr w8, w3, #0x1404; CHECK-GI-NEXT: cmp w0, w2405; CHECK-GI-NEXT: neg w8, w8406; CHECK-GI-NEXT: ccmp w1, w8, #2, gt407; CHECK-GI-NEXT: csel w0, w1, w0, lo408; CHECK-GI-NEXT: ret409 %dor = or i32 %d, 1410 %negd = sub i32 0, %dor411 %cmp = icmp ult i32 %b, %negd412 %cmp1 = icmp sgt i32 %a, %c413 %or.cond = and i1 %cmp, %cmp1414 %retval.0 = select i1 %or.cond, i32 %b, i32 %a415 ret i32 %retval.0416}417 418; (b > -(d | 1) && a u > c)419define i32 @neg_range_int_comp_ua2(i32 %a, i32 %b, i32 %c, i32 %d) {420; CHECK-SD-LABEL: neg_range_int_comp_ua2:421; CHECK-SD: // %bb.0:422; CHECK-SD-NEXT: orr w8, w3, #0x1423; CHECK-SD-NEXT: cmp w0, w2424; CHECK-SD-NEXT: ccmn w1, w8, #4, hi425; CHECK-SD-NEXT: csel w0, w1, w0, gt426; CHECK-SD-NEXT: ret427;428; CHECK-GI-LABEL: neg_range_int_comp_ua2:429; CHECK-GI: // %bb.0:430; CHECK-GI-NEXT: orr w8, w3, #0x1431; CHECK-GI-NEXT: cmp w0, w2432; CHECK-GI-NEXT: neg w8, w8433; CHECK-GI-NEXT: ccmp w1, w8, #4, hi434; CHECK-GI-NEXT: csel w0, w1, w0, gt435; CHECK-GI-NEXT: ret436 %dor = or i32 %d, 1437 %negd = sub i32 0, %dor438 %cmp = icmp sgt i32 %b, %negd439 %cmp1 = icmp ugt i32 %a, %c440 %or.cond = and i1 %cmp, %cmp1441 %retval.0 = select i1 %or.cond, i32 %b, i32 %a442 ret i32 %retval.0443}444 445; (b > -(d | 1) && a u == c)446define i32 @neg_range_int_comp_ua3(i32 %a, i32 %b, i32 %c, i32 %d) {447; CHECK-SD-LABEL: neg_range_int_comp_ua3:448; CHECK-SD: // %bb.0:449; CHECK-SD-NEXT: orr w8, w3, #0x1450; CHECK-SD-NEXT: cmp w0, w2451; CHECK-SD-NEXT: ccmn w1, w8, #4, eq452; CHECK-SD-NEXT: csel w0, w1, w0, gt453; CHECK-SD-NEXT: ret454;455; CHECK-GI-LABEL: neg_range_int_comp_ua3:456; CHECK-GI: // %bb.0:457; CHECK-GI-NEXT: orr w8, w3, #0x1458; CHECK-GI-NEXT: cmp w0, w2459; CHECK-GI-NEXT: neg w8, w8460; CHECK-GI-NEXT: ccmp w1, w8, #4, eq461; CHECK-GI-NEXT: csel w0, w1, w0, gt462; CHECK-GI-NEXT: ret463 %dor = or i32 %d, 1464 %negd = sub i32 0, %dor465 %cmp = icmp sgt i32 %b, %negd466 %cmp1 = icmp eq i32 %a, %c467 %or.cond = and i1 %cmp, %cmp1468 %retval.0 = select i1 %or.cond, i32 %b, i32 %a469 ret i32 %retval.0470}471 472; -(a | 1) > (b | 3) && a < c473define i32 @neg_range_int_c(i32 %a, i32 %b, i32 %c) {474; CHECK-SD-LABEL: neg_range_int_c:475; CHECK-SD: // %bb.0: // %entry476; CHECK-SD-NEXT: orr w8, w0, #0x1477; CHECK-SD-NEXT: orr w9, w1, #0x3478; CHECK-SD-NEXT: cmn w9, w8479; CHECK-SD-NEXT: ccmp w2, w0, #2, lo480; CHECK-SD-NEXT: cset w0, lo481; CHECK-SD-NEXT: ret482;483; CHECK-GI-LABEL: neg_range_int_c:484; CHECK-GI: // %bb.0: // %entry485; CHECK-GI-NEXT: orr w8, w0, #0x1486; CHECK-GI-NEXT: orr w9, w1, #0x3487; CHECK-GI-NEXT: neg w8, w8488; CHECK-GI-NEXT: cmp w9, w8489; CHECK-GI-NEXT: cset w8, lo490; CHECK-GI-NEXT: cmp w2, w0491; CHECK-GI-NEXT: cset w9, lo492; CHECK-GI-NEXT: and w0, w8, w9493; CHECK-GI-NEXT: ret494entry:495 %or = or i32 %a, 1496 %sub = sub i32 0, %or497 %or1 = or i32 %b, 3498 %cmp = icmp ult i32 %or1, %sub499 %cmp2 = icmp ult i32 %c, %a500 %0 = and i1 %cmp, %cmp2501 %land.ext = zext i1 %0 to i32502 ret i32 %land.ext503}504