157 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=3 \3# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \4# RUN: FileCheck -check-prefix=RELAX %s5# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=9 \6# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \7# RUN: FileCheck -check-prefix=NO-RELAX %s8---9name: relax_cb10registers:11 - { id: 0, class: gpr32 }12 - { id: 1, class: gpr32 }13liveins:14 - { reg: '$w0', virtual-reg: '%0' }15 - { reg: '$w1', virtual-reg: '%1' }16body: |17 ; RELAX-LABEL: name: relax_cb18 ; RELAX: bb.0:19 ; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w020 ; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w121 ; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.122 ; RELAX-NEXT: B %bb.223 ; RELAX-NEXT: {{ $}}24 ; RELAX-NEXT: bb.1:25 ; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]26 ; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]27 ; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]28 ; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]29 ; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]30 ; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]31 ; RELAX-NEXT: {{ $}}32 ; RELAX-NEXT: bb.2:33 ; RELAX-NEXT: RET_ReallyLR implicit $w034 ;35 ; NO-RELAX-LABEL: name: relax_cb36 ; NO-RELAX: bb.0:37 ; NO-RELAX-NEXT: successors: %bb.1, %bb.238 ; NO-RELAX-NEXT: {{ $}}39 ; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w040 ; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w141 ; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.242 ; NO-RELAX-NEXT: {{ $}}43 ; NO-RELAX-NEXT: bb.1:44 ; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]45 ; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]46 ; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]47 ; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]48 ; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]49 ; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]50 ; NO-RELAX-NEXT: {{ $}}51 ; NO-RELAX-NEXT: bb.2:52 ; NO-RELAX-NEXT: RET_ReallyLR implicit $w053 bb.0:54 successors: %bb.1, %bb.255 %0:gpr32 = COPY $w056 %1:gpr32 = COPY $w157 CBWPrr 0, %0, %1, %bb.258 59 bb.1:60 successors: %bb.261 %2:gpr32 = ADDWrr %0, %162 %3:gpr32 = ADDWrr %2, %163 %4:gpr32 = ADDWrr %3, %264 %5:gpr32 = ADDWrr %4, %365 %6:gpr32 = ADDWrr %5, %466 $w0 = ADDWrr %6, %567 68 bb.2:69 RET_ReallyLR implicit $w070...71---72name: relax_and_split_block73tracksRegLiveness: true74registers:75 - { id: 0, class: gpr32 }76 - { id: 1, class: gpr32 }77liveins:78 - { reg: '$w0', virtual-reg: '%0' }79 - { reg: '$w1', virtual-reg: '%1' }80body: |81 ; RELAX-LABEL: name: relax_and_split_block82 ; RELAX: bb.0:83 ; RELAX-NEXT: liveins: $w0, $w184 ; RELAX-NEXT: {{ $}}85 ; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w086 ; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w187 ; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.388 ; RELAX-NEXT: B %bb.289 ; RELAX-NEXT: {{ $}}90 ; RELAX-NEXT: bb.3:91 ; RELAX-NEXT: liveins: $w0, $w192 ; RELAX-NEXT: {{ $}}93 ; RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.194 ; RELAX-NEXT: B %bb.295 ; RELAX-NEXT: {{ $}}96 ; RELAX-NEXT: bb.1:97 ; RELAX-NEXT: liveins: $w0, $w198 ; RELAX-NEXT: {{ $}}99 ; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]100 ; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]101 ; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]102 ; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]103 ; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]104 ; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]105 ; RELAX-NEXT: {{ $}}106 ; RELAX-NEXT: bb.2:107 ; RELAX-NEXT: liveins: $w0, $w1108 ; RELAX-NEXT: {{ $}}109 ; RELAX-NEXT: RET_ReallyLR implicit $w0110 ;111 ; NO-RELAX-LABEL: name: relax_and_split_block112 ; NO-RELAX: bb.0:113 ; NO-RELAX-NEXT: successors: %bb.1, %bb.2114 ; NO-RELAX-NEXT: liveins: $w0, $w1115 ; NO-RELAX-NEXT: {{ $}}116 ; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0117 ; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1118 ; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.2119 ; NO-RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.2120 ; NO-RELAX-NEXT: {{ $}}121 ; NO-RELAX-NEXT: bb.1:122 ; NO-RELAX-NEXT: liveins: $w0, $w1123 ; NO-RELAX-NEXT: {{ $}}124 ; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]125 ; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]126 ; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]127 ; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]128 ; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]129 ; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]130 ; NO-RELAX-NEXT: {{ $}}131 ; NO-RELAX-NEXT: bb.2:132 ; NO-RELAX-NEXT: liveins: $w0, $w1133 ; NO-RELAX-NEXT: {{ $}}134 ; NO-RELAX-NEXT: RET_ReallyLR implicit $w0135 bb.0:136 successors: %bb.1, %bb.2137 liveins: $w0, $w1138 %0:gpr32 = COPY $w0139 %1:gpr32 = COPY $w1140 CBWPrr 0, %0, %1, %bb.2141 CBWPrr 1, %0, %1, %bb.2142 143 bb.1:144 successors: %bb.2145 liveins: $w0, $w1146 %2:gpr32 = ADDWrr %0, %1147 %3:gpr32 = ADDWrr %2, %1148 %4:gpr32 = ADDWrr %3, %2149 %5:gpr32 = ADDWrr %4, %3150 %6:gpr32 = ADDWrr %5, %4151 $w0 = ADDWrr %6, %5152 153 bb.2:154 liveins: $w0, $w1155 RET_ReallyLR implicit $w0156...157