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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s3 4; PR48683 'Quadratic Reciprocity' - and(mul(x,x),2) -> 05 6define i1 @PR48683(i32 %x) {7; CHECK-LABEL: PR48683:8; CHECK: // %bb.0:9; CHECK-NEXT: mov w0, wzr10; CHECK-NEXT: ret11 %a = mul i32 %x, %x12 %b = and i32 %a, 213 %c = icmp ne i32 %b, 014 ret i1 %c15}16 17define <4 x i1> @PR48683_vec(<4 x i32> %x) {18; CHECK-LABEL: PR48683_vec:19; CHECK: // %bb.0:20; CHECK-NEXT: movi v0.2d, #000000000000000021; CHECK-NEXT: ret22 %a = mul <4 x i32> %x, %x23 %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>24 %c = icmp ne <4 x i32> %b, zeroinitializer25 ret <4 x i1> %c26}27 28define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {29; CHECK-LABEL: PR48683_vec_undef:30; CHECK: // %bb.0:31; CHECK-NEXT: movi v0.2d, #000000000000000032; CHECK-NEXT: ret33 %a = mul <4 x i32> %x, %x34 %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>35 %c = icmp ne <4 x i32> %b, zeroinitializer36 ret <4 x i1> %c37}38 39; mul(x,x) - bit[1] is 0, but if demanding the other bits the source must not be undef40 41define i64 @combine_mul_self_demandedbits(i64 %x) {42; CHECK-LABEL: combine_mul_self_demandedbits:43; CHECK: // %bb.0:44; CHECK-NEXT: mul x0, x0, x045; CHECK-NEXT: ret46 %1 = mul i64 %x, %x47 %2 = and i64 %1, -348 ret i64 %249}50 51define <4 x i32> @combine_mul_self_demandedbits_vector(<4 x i32> %x) {52; CHECK-LABEL: combine_mul_self_demandedbits_vector:53; CHECK: // %bb.0:54; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s55; CHECK-NEXT: ret56 %1 = freeze <4 x i32> %x57 %2 = mul <4 x i32> %1, %158 %3 = and <4 x i32> %2, <i32 -3, i32 -3, i32 -3, i32 -3>59 ret <4 x i32> %360}61 62define i8 @one_demanded_bit(i8 %x) {63; CHECK-LABEL: one_demanded_bit:64; CHECK: // %bb.0:65; CHECK-NEXT: lsl w8, w0, #666; CHECK-NEXT: orr w0, w8, #0xffffffbf67; CHECK-NEXT: ret68 %m = mul i8 %x, 192 ; 0b1100_000069 %r = or i8 %m, 191 ; 0b1011_111170 ret i8 %r71}72 73define <2 x i64> @one_demanded_bit_splat(<2 x i64> %x) {74; CHECK-LABEL: one_demanded_bit_splat:75; CHECK: // %bb.0:76; CHECK-NEXT: mov w8, #32 // =0x2077; CHECK-NEXT: shl v0.2d, v0.2d, #578; CHECK-NEXT: dup v1.2d, x879; CHECK-NEXT: and v0.16b, v0.16b, v1.16b80; CHECK-NEXT: ret81 %m = mul <2 x i64> %x, <i64 160, i64 160> ; 0b1010_000082 %r = and <2 x i64> %m, <i64 32, i64 32> ; 0b0010_000083 ret <2 x i64> %r84}85 86define i32 @one_demanded_low_bit(i32 %x) {87; CHECK-LABEL: one_demanded_low_bit:88; CHECK: // %bb.0:89; CHECK-NEXT: and w0, w0, #0x190; CHECK-NEXT: ret91 %m = mul i32 %x, -63 ; any odd number will do92 %r = and i32 %m, 193 ret i32 %r94}95 96define i16 @squared_one_demanded_low_bit(i16 %x) {97; CHECK-LABEL: squared_one_demanded_low_bit:98; CHECK: // %bb.0:99; CHECK-NEXT: and w0, w0, #0x1100; CHECK-NEXT: ret101 %mul = mul i16 %x, %x102 %and = and i16 %mul, 1103 ret i16 %and104}105 106define <4 x i32> @squared_one_demanded_low_bit_splat(<4 x i32> %x) {107; CHECK-LABEL: squared_one_demanded_low_bit_splat:108; CHECK: // %bb.0:109; CHECK-NEXT: mvni v1.4s, #1110; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b111; CHECK-NEXT: ret112 %mul = mul <4 x i32> %x, %x113 %and = or <4 x i32> %mul, <i32 -2, i32 -2, i32 -2, i32 -2>114 ret <4 x i32> %and115}116 117define i32 @squared_demanded_2_low_bits(i32 %x) {118; CHECK-LABEL: squared_demanded_2_low_bits:119; CHECK: // %bb.0:120; CHECK-NEXT: and w0, w0, #0x1121; CHECK-NEXT: ret122 %mul = mul i32 %x, %x123 %and = and i32 %mul, 3124 ret i32 %and125}126 127define <2 x i64> @squared_demanded_2_low_bits_splat(<2 x i64> %x) {128; CHECK-LABEL: squared_demanded_2_low_bits_splat:129; CHECK: // %bb.0:130; CHECK-NEXT: mov x8, #-2 // =0xfffffffffffffffe131; CHECK-NEXT: dup v1.2d, x8132; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b133; CHECK-NEXT: ret134 %mul = mul <2 x i64> %x, %x135 %and = or <2 x i64> %mul, <i64 -2, i64 -2>136 ret <2 x i64> %and137}138