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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; These tests are taken from the combine-sdiv.ll in X86.6define i32 @combine_sdiv_by_one(i32 %x) {7; CHECK-LABEL: combine_sdiv_by_one:8; CHECK: // %bb.0:9; CHECK-NEXT: ret10 %1 = sdiv i32 %x, 111 ret i32 %112}13 14define <4 x i32> @combine_vec_sdiv_by_one(<4 x i32> %x) {15; CHECK-LABEL: combine_vec_sdiv_by_one:16; CHECK: // %bb.0:17; CHECK-NEXT: ret18 %1 = sdiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>19 ret <4 x i32> %120}21 22define i32 @combine_sdiv_by_negone(i32 %x) {23; CHECK-LABEL: combine_sdiv_by_negone:24; CHECK: // %bb.0:25; CHECK-NEXT: neg w0, w026; CHECK-NEXT: ret27 %1 = sdiv i32 %x, -128 ret i32 %129}30 31define <4 x i32> @combine_vec_sdiv_by_negone(<4 x i32> %x) {32; CHECK-LABEL: combine_vec_sdiv_by_negone:33; CHECK: // %bb.0:34; CHECK-NEXT: neg v0.4s, v0.4s35; CHECK-NEXT: ret36 %1 = sdiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>37 ret <4 x i32> %138}39 40define i32 @combine_sdiv_by_minsigned(i32 %x) {41; CHECK-SD-LABEL: combine_sdiv_by_minsigned:42; CHECK-SD: // %bb.0:43; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x8000000044; CHECK-SD-NEXT: cmp w0, w845; CHECK-SD-NEXT: cset w0, eq46; CHECK-SD-NEXT: ret47;48; CHECK-GI-LABEL: combine_sdiv_by_minsigned:49; CHECK-GI: // %bb.0:50; CHECK-GI-NEXT: asr w8, w0, #3151; CHECK-GI-NEXT: add w8, w0, w8, lsr #152; CHECK-GI-NEXT: neg w0, w8, asr #3153; CHECK-GI-NEXT: ret54 %1 = sdiv i32 %x, -214748364855 ret i32 %156}57 58define <4 x i32> @combine_vec_sdiv_by_minsigned(<4 x i32> %x) {59; CHECK-SD-LABEL: combine_vec_sdiv_by_minsigned:60; CHECK-SD: // %bb.0:61; CHECK-SD-NEXT: movi v1.4s, #128, lsl #2462; CHECK-SD-NEXT: movi v2.4s, #163; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s64; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b65; CHECK-SD-NEXT: ret66;67; CHECK-GI-LABEL: combine_vec_sdiv_by_minsigned:68; CHECK-GI: // %bb.0:69; CHECK-GI-NEXT: cmlt v1.4s, v0.4s, #070; CHECK-GI-NEXT: usra v0.4s, v1.4s, #171; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #072; CHECK-GI-NEXT: neg v0.4s, v0.4s73; CHECK-GI-NEXT: ret74 %1 = sdiv <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>75 ret <4 x i32> %176}77 78define i32 @combine_sdiv_zero(i32 %x) {79; CHECK-LABEL: combine_sdiv_zero:80; CHECK: // %bb.0:81; CHECK-NEXT: mov w0, wzr82; CHECK-NEXT: ret83 %1 = sdiv i32 0, %x84 ret i32 %185}86 87define <4 x i32> @combine_vec_sdiv_zero(<4 x i32> %x) {88; CHECK-LABEL: combine_vec_sdiv_zero:89; CHECK: // %bb.0:90; CHECK-NEXT: movi v0.2d, #000000000000000091; CHECK-NEXT: ret92 %1 = sdiv <4 x i32> zeroinitializer, %x93 ret <4 x i32> %194}95 96define i32 @combine_sdiv_dupe(i32 %x) {97; CHECK-SD-LABEL: combine_sdiv_dupe:98; CHECK-SD: // %bb.0:99; CHECK-SD-NEXT: mov w0, #1 // =0x1100; CHECK-SD-NEXT: ret101;102; CHECK-GI-LABEL: combine_sdiv_dupe:103; CHECK-GI: // %bb.0:104; CHECK-GI-NEXT: sdiv w0, w0, w0105; CHECK-GI-NEXT: ret106 %1 = sdiv i32 %x, %x107 ret i32 %1108}109 110define <4 x i32> @combine_vec_sdiv_dupe(<4 x i32> %x) {111; CHECK-SD-LABEL: combine_vec_sdiv_dupe:112; CHECK-SD: // %bb.0:113; CHECK-SD-NEXT: movi v0.4s, #1114; CHECK-SD-NEXT: ret115;116; CHECK-GI-LABEL: combine_vec_sdiv_dupe:117; CHECK-GI: // %bb.0:118; CHECK-GI-NEXT: fmov w8, s0119; CHECK-GI-NEXT: mov w9, v0.s[1]120; CHECK-GI-NEXT: mov w10, v0.s[2]121; CHECK-GI-NEXT: mov w11, v0.s[3]122; CHECK-GI-NEXT: sdiv w8, w8, w8123; CHECK-GI-NEXT: sdiv w9, w9, w9124; CHECK-GI-NEXT: fmov s0, w8125; CHECK-GI-NEXT: sdiv w10, w10, w10126; CHECK-GI-NEXT: mov v0.s[1], w9127; CHECK-GI-NEXT: sdiv w8, w11, w11128; CHECK-GI-NEXT: mov v0.s[2], w10129; CHECK-GI-NEXT: mov v0.s[3], w8130; CHECK-GI-NEXT: ret131 %1 = sdiv <4 x i32> %x, %x132 ret <4 x i32> %1133}134 135define <4 x i32> @combine_vec_sdiv_by_pos0(<4 x i32> %x) {136; CHECK-SD-LABEL: combine_vec_sdiv_by_pos0:137; CHECK-SD: // %bb.0:138; CHECK-SD-NEXT: movi v1.2d, #0x0000ff000000ff139; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b140; CHECK-SD-NEXT: ushr v0.4s, v0.4s, #2141; CHECK-SD-NEXT: ret142;143; CHECK-GI-LABEL: combine_vec_sdiv_by_pos0:144; CHECK-GI: // %bb.0:145; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff146; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b147; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #2148; CHECK-GI-NEXT: ret149 %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>150 %2 = sdiv <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>151 ret <4 x i32> %2152}153 154define <4 x i32> @combine_vec_sdiv_by_pos1(<4 x i32> %x) {155; CHECK-SD-LABEL: combine_vec_sdiv_by_pos1:156; CHECK-SD: // %bb.0:157; CHECK-SD-NEXT: movi v1.2d, #0x0000ff000000ff158; CHECK-SD-NEXT: adrp x8, .LCPI11_0159; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b160; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI11_0]161; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s162; CHECK-SD-NEXT: ret163;164; CHECK-GI-LABEL: combine_vec_sdiv_by_pos1:165; CHECK-GI: // %bb.0:166; CHECK-GI-NEXT: mov w8, #1 // =0x1167; CHECK-GI-NEXT: mov w9, #0 // =0x0168; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff169; CHECK-GI-NEXT: fmov s1, w8170; CHECK-GI-NEXT: adrp x8, .LCPI11_0171; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI11_0]172; CHECK-GI-NEXT: mov v1.s[1], w9173; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b174; CHECK-GI-NEXT: neg v2.4s, v3.4s175; CHECK-GI-NEXT: sshl v2.4s, v0.4s, v2.4s176; CHECK-GI-NEXT: mov v1.s[2], w9177; CHECK-GI-NEXT: mov v1.s[3], w9178; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31179; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0180; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b181; CHECK-GI-NEXT: ret182 %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>183 %2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>184 ret <4 x i32> %2185}186 187define <4 x i32> @combine_vec_sdiv_by_pow2a(<4 x i32> %x) {188; CHECK-LABEL: combine_vec_sdiv_by_pow2a:189; CHECK: // %bb.0:190; CHECK-NEXT: cmlt v1.4s, v0.4s, #0191; CHECK-NEXT: usra v0.4s, v1.4s, #30192; CHECK-NEXT: sshr v0.4s, v0.4s, #2193; CHECK-NEXT: ret194 %1 = sdiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>195 ret <4 x i32> %1196}197 198define <4 x i32> @combine_vec_sdiv_by_pow2a_neg(<4 x i32> %x) {199; CHECK-LABEL: combine_vec_sdiv_by_pow2a_neg:200; CHECK: // %bb.0:201; CHECK-NEXT: cmlt v1.4s, v0.4s, #0202; CHECK-NEXT: usra v0.4s, v1.4s, #30203; CHECK-NEXT: sshr v0.4s, v0.4s, #2204; CHECK-NEXT: neg v0.4s, v0.4s205; CHECK-NEXT: ret206 %1 = sdiv <4 x i32> %x, <i32 -4, i32 -4, i32 -4, i32 -4>207 ret <4 x i32> %1208}209 210define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) {211; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v16i8:212; CHECK-SD: // %bb.0:213; CHECK-SD-NEXT: adrp x8, .LCPI14_0214; CHECK-SD-NEXT: cmlt v1.16b, v0.16b, #0215; CHECK-SD-NEXT: movi v3.2d, #0x000000000000ff216; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI14_0]217; CHECK-SD-NEXT: adrp x8, .LCPI14_1218; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v2.16b219; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]220; CHECK-SD-NEXT: add v1.16b, v0.16b, v1.16b221; CHECK-SD-NEXT: sshl v1.16b, v1.16b, v2.16b222; CHECK-SD-NEXT: bif v0.16b, v1.16b, v3.16b223; CHECK-SD-NEXT: ret224;225; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v16i8:226; CHECK-GI: // %bb.0:227; CHECK-GI-NEXT: adrp x8, .LCPI14_1228; CHECK-GI-NEXT: cmlt v2.16b, v0.16b, #0229; CHECK-GI-NEXT: adrp x9, .LCPI14_0230; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]231; CHECK-GI-NEXT: adrp x8, .LCPI14_2232; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI14_0]233; CHECK-GI-NEXT: neg v1.16b, v1.16b234; CHECK-GI-NEXT: shl v3.16b, v3.16b, #7235; CHECK-GI-NEXT: ushl v1.16b, v2.16b, v1.16b236; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI14_2]237; CHECK-GI-NEXT: neg v2.16b, v2.16b238; CHECK-GI-NEXT: add v1.16b, v0.16b, v1.16b239; CHECK-GI-NEXT: sshl v1.16b, v1.16b, v2.16b240; CHECK-GI-NEXT: cmlt v2.16b, v3.16b, #0241; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b242; CHECK-GI-NEXT: ret243 %1 = sdiv <16 x i8> %x, <i8 1, i8 4, i8 2, i8 16, i8 8, i8 32, i8 64, i8 2, i8 1, i8 4, i8 2, i8 16, i8 8, i8 32, i8 64, i8 2>244 ret <16 x i8> %1245}246 247define <8 x i16> @combine_vec_sdiv_by_pow2b_v8i16(<8 x i16> %x) {248; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v8i16:249; CHECK-SD: // %bb.0:250; CHECK-SD-NEXT: adrp x8, .LCPI15_0251; CHECK-SD-NEXT: cmlt v1.8h, v0.8h, #0252; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI15_0]253; CHECK-SD-NEXT: adrp x8, .LCPI15_1254; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v2.8h255; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]256; CHECK-SD-NEXT: adrp x8, .LCPI15_2257; CHECK-SD-NEXT: add v1.8h, v0.8h, v1.8h258; CHECK-SD-NEXT: sshl v1.8h, v1.8h, v2.8h259; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]260; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b261; CHECK-SD-NEXT: ret262;263; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v8i16:264; CHECK-GI: // %bb.0:265; CHECK-GI-NEXT: adrp x8, .LCPI15_1266; CHECK-GI-NEXT: cmlt v2.8h, v0.8h, #0267; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]268; CHECK-GI-NEXT: adrp x8, .LCPI15_0269; CHECK-GI-NEXT: ldr d3, [x8, :lo12:.LCPI15_0]270; CHECK-GI-NEXT: adrp x8, .LCPI15_2271; CHECK-GI-NEXT: neg v1.8h, v1.8h272; CHECK-GI-NEXT: ushl v1.8h, v2.8h, v1.8h273; CHECK-GI-NEXT: ushll v2.8h, v3.8b, #0274; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI15_2]275; CHECK-GI-NEXT: neg v3.8h, v3.8h276; CHECK-GI-NEXT: add v1.8h, v0.8h, v1.8h277; CHECK-GI-NEXT: shl v2.8h, v2.8h, #15278; CHECK-GI-NEXT: sshl v1.8h, v1.8h, v3.8h279; CHECK-GI-NEXT: cmlt v2.8h, v2.8h, #0280; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b281; CHECK-GI-NEXT: ret282 %1 = sdiv <8 x i16> %x, <i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2>283 ret <8 x i16> %1284}285 286define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) {287; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v16i16:288; CHECK-SD: // %bb.0:289; CHECK-SD-NEXT: adrp x8, .LCPI16_0290; CHECK-SD-NEXT: cmlt v2.8h, v0.8h, #0291; CHECK-SD-NEXT: cmlt v3.8h, v1.8h, #0292; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI16_0]293; CHECK-SD-NEXT: adrp x8, .LCPI16_1294; CHECK-SD-NEXT: ushl v2.8h, v2.8h, v4.8h295; CHECK-SD-NEXT: ushl v3.8h, v3.8h, v4.8h296; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI16_1]297; CHECK-SD-NEXT: adrp x8, .LCPI16_2298; CHECK-SD-NEXT: add v2.8h, v0.8h, v2.8h299; CHECK-SD-NEXT: add v3.8h, v1.8h, v3.8h300; CHECK-SD-NEXT: sshl v2.8h, v2.8h, v4.8h301; CHECK-SD-NEXT: sshl v3.8h, v3.8h, v4.8h302; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI16_2]303; CHECK-SD-NEXT: bif v0.16b, v2.16b, v4.16b304; CHECK-SD-NEXT: bif v1.16b, v3.16b, v4.16b305; CHECK-SD-NEXT: ret306;307; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v16i16:308; CHECK-GI: // %bb.0:309; CHECK-GI-NEXT: adrp x8, .LCPI16_1310; CHECK-GI-NEXT: cmlt v3.8h, v0.8h, #0311; CHECK-GI-NEXT: cmlt v4.8h, v1.8h, #0312; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI16_1]313; CHECK-GI-NEXT: adrp x8, .LCPI16_0314; CHECK-GI-NEXT: ldr d5, [x8, :lo12:.LCPI16_0]315; CHECK-GI-NEXT: adrp x8, .LCPI16_2316; CHECK-GI-NEXT: neg v2.8h, v2.8h317; CHECK-GI-NEXT: ushll v5.8h, v5.8b, #0318; CHECK-GI-NEXT: ushl v3.8h, v3.8h, v2.8h319; CHECK-GI-NEXT: ushl v2.8h, v4.8h, v2.8h320; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI16_2]321; CHECK-GI-NEXT: shl v5.8h, v5.8h, #15322; CHECK-GI-NEXT: neg v4.8h, v4.8h323; CHECK-GI-NEXT: add v3.8h, v0.8h, v3.8h324; CHECK-GI-NEXT: add v2.8h, v1.8h, v2.8h325; CHECK-GI-NEXT: sshl v3.8h, v3.8h, v4.8h326; CHECK-GI-NEXT: sshl v2.8h, v2.8h, v4.8h327; CHECK-GI-NEXT: cmlt v4.8h, v5.8h, #0328; CHECK-GI-NEXT: bif v0.16b, v3.16b, v4.16b329; CHECK-GI-NEXT: bif v1.16b, v2.16b, v4.16b330; CHECK-GI-NEXT: ret331 %1 = sdiv <16 x i16> %x, <i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2, i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2>332 ret <16 x i16> %1333}334 335define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) {336; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v32i16:337; CHECK-SD: // %bb.0:338; CHECK-SD-NEXT: adrp x8, .LCPI17_0339; CHECK-SD-NEXT: cmlt v4.8h, v0.8h, #0340; CHECK-SD-NEXT: cmlt v5.8h, v1.8h, #0341; CHECK-SD-NEXT: cmlt v7.8h, v2.8h, #0342; CHECK-SD-NEXT: cmlt v16.8h, v3.8h, #0343; CHECK-SD-NEXT: ldr q6, [x8, :lo12:.LCPI17_0]344; CHECK-SD-NEXT: adrp x8, .LCPI17_1345; CHECK-SD-NEXT: ushl v4.8h, v4.8h, v6.8h346; CHECK-SD-NEXT: ushl v5.8h, v5.8h, v6.8h347; CHECK-SD-NEXT: ushl v7.8h, v7.8h, v6.8h348; CHECK-SD-NEXT: ushl v6.8h, v16.8h, v6.8h349; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI17_1]350; CHECK-SD-NEXT: adrp x8, .LCPI17_2351; CHECK-SD-NEXT: add v4.8h, v0.8h, v4.8h352; CHECK-SD-NEXT: add v5.8h, v1.8h, v5.8h353; CHECK-SD-NEXT: add v7.8h, v2.8h, v7.8h354; CHECK-SD-NEXT: add v6.8h, v3.8h, v6.8h355; CHECK-SD-NEXT: sshl v4.8h, v4.8h, v16.8h356; CHECK-SD-NEXT: sshl v5.8h, v5.8h, v16.8h357; CHECK-SD-NEXT: sshl v7.8h, v7.8h, v16.8h358; CHECK-SD-NEXT: sshl v6.8h, v6.8h, v16.8h359; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI17_2]360; CHECK-SD-NEXT: bif v0.16b, v4.16b, v16.16b361; CHECK-SD-NEXT: bif v1.16b, v5.16b, v16.16b362; CHECK-SD-NEXT: bif v2.16b, v7.16b, v16.16b363; CHECK-SD-NEXT: bif v3.16b, v6.16b, v16.16b364; CHECK-SD-NEXT: ret365;366; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v32i16:367; CHECK-GI: // %bb.0:368; CHECK-GI-NEXT: adrp x8, .LCPI17_1369; CHECK-GI-NEXT: cmlt v5.8h, v0.8h, #0370; CHECK-GI-NEXT: cmlt v6.8h, v1.8h, #0371; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI17_1]372; CHECK-GI-NEXT: adrp x8, .LCPI17_0373; CHECK-GI-NEXT: cmlt v7.8h, v2.8h, #0374; CHECK-GI-NEXT: cmlt v16.8h, v3.8h, #0375; CHECK-GI-NEXT: ldr d17, [x8, :lo12:.LCPI17_0]376; CHECK-GI-NEXT: adrp x8, .LCPI17_2377; CHECK-GI-NEXT: neg v4.8h, v4.8h378; CHECK-GI-NEXT: ushll v17.8h, v17.8b, #0379; CHECK-GI-NEXT: ushl v5.8h, v5.8h, v4.8h380; CHECK-GI-NEXT: ushl v6.8h, v6.8h, v4.8h381; CHECK-GI-NEXT: ushl v7.8h, v7.8h, v4.8h382; CHECK-GI-NEXT: ushl v4.8h, v16.8h, v4.8h383; CHECK-GI-NEXT: ldr q16, [x8, :lo12:.LCPI17_2]384; CHECK-GI-NEXT: shl v17.8h, v17.8h, #15385; CHECK-GI-NEXT: neg v16.8h, v16.8h386; CHECK-GI-NEXT: add v5.8h, v0.8h, v5.8h387; CHECK-GI-NEXT: add v6.8h, v1.8h, v6.8h388; CHECK-GI-NEXT: add v7.8h, v2.8h, v7.8h389; CHECK-GI-NEXT: add v4.8h, v3.8h, v4.8h390; CHECK-GI-NEXT: cmlt v17.8h, v17.8h, #0391; CHECK-GI-NEXT: sshl v5.8h, v5.8h, v16.8h392; CHECK-GI-NEXT: sshl v6.8h, v6.8h, v16.8h393; CHECK-GI-NEXT: sshl v7.8h, v7.8h, v16.8h394; CHECK-GI-NEXT: sshl v4.8h, v4.8h, v16.8h395; CHECK-GI-NEXT: bif v0.16b, v5.16b, v17.16b396; CHECK-GI-NEXT: bif v1.16b, v6.16b, v17.16b397; CHECK-GI-NEXT: bif v2.16b, v7.16b, v17.16b398; CHECK-GI-NEXT: bif v3.16b, v4.16b, v17.16b399; CHECK-GI-NEXT: ret400 %1 = sdiv <32 x i16> %x, <i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2, i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2, i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2, i16 1, i16 4, i16 2, i16 16, i16 8, i16 32, i16 64, i16 2>401 ret <32 x i16> %1402}403 404define <4 x i32> @combine_vec_sdiv_by_pow2b_v4i32(<4 x i32> %x) {405; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v4i32:406; CHECK-SD: // %bb.0:407; CHECK-SD-NEXT: adrp x8, .LCPI18_0408; CHECK-SD-NEXT: cmlt v1.4s, v0.4s, #0409; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI18_0]410; CHECK-SD-NEXT: adrp x8, .LCPI18_1411; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v2.4s412; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI18_1]413; CHECK-SD-NEXT: adrp x8, .LCPI18_2414; CHECK-SD-NEXT: add v1.4s, v0.4s, v1.4s415; CHECK-SD-NEXT: sshl v1.4s, v1.4s, v2.4s416; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI18_2]417; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b418; CHECK-SD-NEXT: ret419;420; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v4i32:421; CHECK-GI: // %bb.0:422; CHECK-GI-NEXT: mov w8, #1 // =0x1423; CHECK-GI-NEXT: mov w9, #0 // =0x0424; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0425; CHECK-GI-NEXT: fmov s1, w8426; CHECK-GI-NEXT: adrp x8, .LCPI18_0427; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI18_0]428; CHECK-GI-NEXT: adrp x8, .LCPI18_1429; CHECK-GI-NEXT: mov v1.s[1], w9430; CHECK-GI-NEXT: neg v2.4s, v2.4s431; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s432; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI18_1]433; CHECK-GI-NEXT: mov v1.s[2], w9434; CHECK-GI-NEXT: neg v3.4s, v3.4s435; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s436; CHECK-GI-NEXT: mov v1.s[3], w9437; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v3.4s438; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31439; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0440; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b441; CHECK-GI-NEXT: ret442 %1 = sdiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>443 ret <4 x i32> %1444}445 446define <8 x i32> @combine_vec_sdiv_by_pow2b_v8i32(<8 x i32> %x) {447; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v8i32:448; CHECK-SD: // %bb.0:449; CHECK-SD-NEXT: adrp x8, .LCPI19_0450; CHECK-SD-NEXT: cmlt v2.4s, v0.4s, #0451; CHECK-SD-NEXT: cmlt v3.4s, v1.4s, #0452; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI19_0]453; CHECK-SD-NEXT: adrp x8, .LCPI19_1454; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v4.4s455; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v4.4s456; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI19_1]457; CHECK-SD-NEXT: adrp x8, .LCPI19_2458; CHECK-SD-NEXT: add v2.4s, v0.4s, v2.4s459; CHECK-SD-NEXT: add v3.4s, v1.4s, v3.4s460; CHECK-SD-NEXT: sshl v2.4s, v2.4s, v4.4s461; CHECK-SD-NEXT: sshl v3.4s, v3.4s, v4.4s462; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI19_2]463; CHECK-SD-NEXT: bif v0.16b, v2.16b, v4.16b464; CHECK-SD-NEXT: bif v1.16b, v3.16b, v4.16b465; CHECK-SD-NEXT: ret466;467; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v8i32:468; CHECK-GI: // %bb.0:469; CHECK-GI-NEXT: mov w8, #1 // =0x1470; CHECK-GI-NEXT: mov w9, #0 // =0x0471; CHECK-GI-NEXT: cmlt v4.4s, v0.4s, #0472; CHECK-GI-NEXT: fmov s2, w8473; CHECK-GI-NEXT: adrp x8, .LCPI19_0474; CHECK-GI-NEXT: cmlt v5.4s, v1.4s, #0475; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI19_0]476; CHECK-GI-NEXT: adrp x8, .LCPI19_1477; CHECK-GI-NEXT: mov v2.h[1], w9478; CHECK-GI-NEXT: neg v3.4s, v3.4s479; CHECK-GI-NEXT: ushl v4.4s, v4.4s, v3.4s480; CHECK-GI-NEXT: ushl v3.4s, v5.4s, v3.4s481; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI19_1]482; CHECK-GI-NEXT: mov v2.h[2], w9483; CHECK-GI-NEXT: neg v5.4s, v5.4s484; CHECK-GI-NEXT: add v4.4s, v0.4s, v4.4s485; CHECK-GI-NEXT: add v3.4s, v1.4s, v3.4s486; CHECK-GI-NEXT: mov v2.h[3], w9487; CHECK-GI-NEXT: sshl v4.4s, v4.4s, v5.4s488; CHECK-GI-NEXT: sshl v3.4s, v3.4s, v5.4s489; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0490; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31491; CHECK-GI-NEXT: cmlt v2.4s, v2.4s, #0492; CHECK-GI-NEXT: bif v0.16b, v4.16b, v2.16b493; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b494; CHECK-GI-NEXT: ret495 %1 = sdiv <8 x i32> %x, <i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16>496 ret <8 x i32> %1497}498 499define <16 x i32> @combine_vec_sdiv_by_pow2b_v16i32(<16 x i32> %x) {500; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v16i32:501; CHECK-SD: // %bb.0:502; CHECK-SD-NEXT: adrp x8, .LCPI20_0503; CHECK-SD-NEXT: cmlt v4.4s, v0.4s, #0504; CHECK-SD-NEXT: cmlt v5.4s, v1.4s, #0505; CHECK-SD-NEXT: cmlt v7.4s, v2.4s, #0506; CHECK-SD-NEXT: cmlt v16.4s, v3.4s, #0507; CHECK-SD-NEXT: ldr q6, [x8, :lo12:.LCPI20_0]508; CHECK-SD-NEXT: adrp x8, .LCPI20_1509; CHECK-SD-NEXT: ushl v4.4s, v4.4s, v6.4s510; CHECK-SD-NEXT: ushl v5.4s, v5.4s, v6.4s511; CHECK-SD-NEXT: ushl v7.4s, v7.4s, v6.4s512; CHECK-SD-NEXT: ushl v6.4s, v16.4s, v6.4s513; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI20_1]514; CHECK-SD-NEXT: adrp x8, .LCPI20_2515; CHECK-SD-NEXT: add v4.4s, v0.4s, v4.4s516; CHECK-SD-NEXT: add v5.4s, v1.4s, v5.4s517; CHECK-SD-NEXT: add v7.4s, v2.4s, v7.4s518; CHECK-SD-NEXT: add v6.4s, v3.4s, v6.4s519; CHECK-SD-NEXT: sshl v4.4s, v4.4s, v16.4s520; CHECK-SD-NEXT: sshl v5.4s, v5.4s, v16.4s521; CHECK-SD-NEXT: sshl v7.4s, v7.4s, v16.4s522; CHECK-SD-NEXT: sshl v6.4s, v6.4s, v16.4s523; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI20_2]524; CHECK-SD-NEXT: bif v0.16b, v4.16b, v16.16b525; CHECK-SD-NEXT: bif v1.16b, v5.16b, v16.16b526; CHECK-SD-NEXT: bif v2.16b, v7.16b, v16.16b527; CHECK-SD-NEXT: bif v3.16b, v6.16b, v16.16b528; CHECK-SD-NEXT: ret529;530; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v16i32:531; CHECK-GI: // %bb.0:532; CHECK-GI-NEXT: mov w8, #1 // =0x1533; CHECK-GI-NEXT: mov w9, #0 // =0x0534; CHECK-GI-NEXT: cmlt v6.4s, v0.4s, #0535; CHECK-GI-NEXT: fmov s4, w8536; CHECK-GI-NEXT: adrp x8, .LCPI20_0537; CHECK-GI-NEXT: cmlt v7.4s, v1.4s, #0538; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI20_0]539; CHECK-GI-NEXT: cmlt v16.4s, v2.4s, #0540; CHECK-GI-NEXT: cmlt v17.4s, v3.4s, #0541; CHECK-GI-NEXT: adrp x8, .LCPI20_1542; CHECK-GI-NEXT: mov v4.h[1], w9543; CHECK-GI-NEXT: neg v5.4s, v5.4s544; CHECK-GI-NEXT: ushl v6.4s, v6.4s, v5.4s545; CHECK-GI-NEXT: ushl v7.4s, v7.4s, v5.4s546; CHECK-GI-NEXT: ushl v16.4s, v16.4s, v5.4s547; CHECK-GI-NEXT: mov v4.h[2], w9548; CHECK-GI-NEXT: ushl v5.4s, v17.4s, v5.4s549; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI20_1]550; CHECK-GI-NEXT: neg v17.4s, v17.4s551; CHECK-GI-NEXT: add v6.4s, v0.4s, v6.4s552; CHECK-GI-NEXT: add v7.4s, v1.4s, v7.4s553; CHECK-GI-NEXT: add v16.4s, v2.4s, v16.4s554; CHECK-GI-NEXT: add v5.4s, v3.4s, v5.4s555; CHECK-GI-NEXT: mov v4.h[3], w9556; CHECK-GI-NEXT: sshl v6.4s, v6.4s, v17.4s557; CHECK-GI-NEXT: sshl v7.4s, v7.4s, v17.4s558; CHECK-GI-NEXT: sshl v16.4s, v16.4s, v17.4s559; CHECK-GI-NEXT: sshl v5.4s, v5.4s, v17.4s560; CHECK-GI-NEXT: ushll v4.4s, v4.4h, #0561; CHECK-GI-NEXT: shl v4.4s, v4.4s, #31562; CHECK-GI-NEXT: cmlt v4.4s, v4.4s, #0563; CHECK-GI-NEXT: bif v0.16b, v6.16b, v4.16b564; CHECK-GI-NEXT: bif v1.16b, v7.16b, v4.16b565; CHECK-GI-NEXT: bif v2.16b, v16.16b, v4.16b566; CHECK-GI-NEXT: bif v3.16b, v5.16b, v4.16b567; CHECK-GI-NEXT: ret568 %1 = sdiv <16 x i32> %x, <i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16>569 ret <16 x i32> %1570}571 572define <2 x i64> @combine_vec_sdiv_by_pow2b_v2i64(<2 x i64> %x) {573; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v2i64:574; CHECK-SD: // %bb.0:575; CHECK-SD-NEXT: adrp x8, .LCPI21_0576; CHECK-SD-NEXT: cmlt v1.2d, v0.2d, #0577; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]578; CHECK-SD-NEXT: adrp x8, .LCPI21_1579; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v2.2d580; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI21_1]581; CHECK-SD-NEXT: adrp x8, .LCPI21_2582; CHECK-SD-NEXT: add v1.2d, v0.2d, v1.2d583; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v2.2d584; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI21_2]585; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b586; CHECK-SD-NEXT: ret587;588; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v2i64:589; CHECK-GI: // %bb.0:590; CHECK-GI-NEXT: adrp x8, .LCPI21_1591; CHECK-GI-NEXT: cmlt v2.2d, v0.2d, #0592; CHECK-GI-NEXT: adrp x9, .LCPI21_0593; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI21_1]594; CHECK-GI-NEXT: adrp x8, .LCPI21_2595; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI21_0]596; CHECK-GI-NEXT: neg v1.2d, v1.2d597; CHECK-GI-NEXT: shl v3.2d, v3.2d, #63598; CHECK-GI-NEXT: ushl v1.2d, v2.2d, v1.2d599; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI21_2]600; CHECK-GI-NEXT: neg v2.2d, v2.2d601; CHECK-GI-NEXT: add v1.2d, v0.2d, v1.2d602; CHECK-GI-NEXT: sshl v1.2d, v1.2d, v2.2d603; CHECK-GI-NEXT: cmlt v2.2d, v3.2d, #0604; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b605; CHECK-GI-NEXT: ret606 %1 = sdiv <2 x i64> %x, <i64 1, i64 4>607 ret <2 x i64> %1608}609 610define <4 x i64> @combine_vec_sdiv_by_pow2b_v4i64(<4 x i64> %x) {611; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v4i64:612; CHECK-SD: // %bb.0:613; CHECK-SD-NEXT: adrp x8, .LCPI22_0614; CHECK-SD-NEXT: cmlt v2.2d, v0.2d, #0615; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI22_0]616; CHECK-SD-NEXT: adrp x8, .LCPI22_3617; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]618; CHECK-SD-NEXT: adrp x8, .LCPI22_1619; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v3.2d620; CHECK-SD-NEXT: cmlt v3.2d, v1.2d, #0621; CHECK-SD-NEXT: add v2.2d, v0.2d, v2.2d622; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v4.2d623; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_1]624; CHECK-SD-NEXT: adrp x8, .LCPI22_2625; CHECK-SD-NEXT: sshl v2.2d, v2.2d, v4.2d626; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_2]627; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d628; CHECK-SD-NEXT: adrp x8, .LCPI22_4629; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI22_4]630; CHECK-SD-NEXT: bif v0.16b, v2.16b, v4.16b631; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v3.2d632; CHECK-SD-NEXT: ret633;634; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v4i64:635; CHECK-GI: // %bb.0:636; CHECK-GI-NEXT: adrp x8, .LCPI22_2637; CHECK-GI-NEXT: cmlt v3.2d, v0.2d, #0638; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI22_2]639; CHECK-GI-NEXT: adrp x8, .LCPI22_1640; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI22_1]641; CHECK-GI-NEXT: adrp x8, .LCPI22_4642; CHECK-GI-NEXT: neg v2.2d, v2.2d643; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI22_4]644; CHECK-GI-NEXT: adrp x8, .LCPI22_0645; CHECK-GI-NEXT: neg v4.2d, v4.2d646; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI22_0]647; CHECK-GI-NEXT: adrp x8, .LCPI22_3648; CHECK-GI-NEXT: neg v5.2d, v5.2d649; CHECK-GI-NEXT: ushl v2.2d, v3.2d, v2.2d650; CHECK-GI-NEXT: cmlt v3.2d, v1.2d, #0651; CHECK-GI-NEXT: shl v6.2d, v6.2d, #63652; CHECK-GI-NEXT: add v2.2d, v0.2d, v2.2d653; CHECK-GI-NEXT: ushl v3.2d, v3.2d, v4.2d654; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]655; CHECK-GI-NEXT: sshl v2.2d, v2.2d, v5.2d656; CHECK-GI-NEXT: cmlt v5.2d, v6.2d, #0657; CHECK-GI-NEXT: add v1.2d, v1.2d, v3.2d658; CHECK-GI-NEXT: neg v3.2d, v4.2d659; CHECK-GI-NEXT: bif v0.16b, v2.16b, v5.16b660; CHECK-GI-NEXT: sshl v1.2d, v1.2d, v3.2d661; CHECK-GI-NEXT: ret662 %1 = sdiv <4 x i64> %x, <i64 1, i64 4, i64 8, i64 16>663 ret <4 x i64> %1664}665 666define <8 x i64> @combine_vec_sdiv_by_pow2b_v8i64(<8 x i64> %x) {667; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_v8i64:668; CHECK-SD: // %bb.0:669; CHECK-SD-NEXT: adrp x8, .LCPI23_0670; CHECK-SD-NEXT: cmlt v4.2d, v0.2d, #0671; CHECK-SD-NEXT: cmlt v6.2d, v2.2d, #0672; CHECK-SD-NEXT: ldr q5, [x8, :lo12:.LCPI23_0]673; CHECK-SD-NEXT: adrp x8, .LCPI23_3674; CHECK-SD-NEXT: cmlt v7.2d, v3.2d, #0675; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI23_3]676; CHECK-SD-NEXT: adrp x8, .LCPI23_1677; CHECK-SD-NEXT: ushl v4.2d, v4.2d, v5.2d678; CHECK-SD-NEXT: ushl v5.2d, v6.2d, v5.2d679; CHECK-SD-NEXT: cmlt v6.2d, v1.2d, #0680; CHECK-SD-NEXT: ldr q17, [x8, :lo12:.LCPI23_1]681; CHECK-SD-NEXT: ushl v7.2d, v7.2d, v16.2d682; CHECK-SD-NEXT: adrp x8, .LCPI23_2683; CHECK-SD-NEXT: add v4.2d, v0.2d, v4.2d684; CHECK-SD-NEXT: add v5.2d, v2.2d, v5.2d685; CHECK-SD-NEXT: ushl v6.2d, v6.2d, v16.2d686; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI23_2]687; CHECK-SD-NEXT: adrp x8, .LCPI23_4688; CHECK-SD-NEXT: add v3.2d, v3.2d, v7.2d689; CHECK-SD-NEXT: sshl v4.2d, v4.2d, v17.2d690; CHECK-SD-NEXT: sshl v5.2d, v5.2d, v17.2d691; CHECK-SD-NEXT: add v1.2d, v1.2d, v6.2d692; CHECK-SD-NEXT: ldr q6, [x8, :lo12:.LCPI23_4]693; CHECK-SD-NEXT: bif v0.16b, v4.16b, v16.16b694; CHECK-SD-NEXT: bif v2.16b, v5.16b, v16.16b695; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v6.2d696; CHECK-SD-NEXT: sshl v3.2d, v3.2d, v6.2d697; CHECK-SD-NEXT: ret698;699; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v8i64:700; CHECK-GI: // %bb.0:701; CHECK-GI-NEXT: mov w8, #1 // =0x1702; CHECK-GI-NEXT: mov w9, #0 // =0x0703; CHECK-GI-NEXT: cmlt v7.2d, v0.2d, #0704; CHECK-GI-NEXT: fmov s4, w8705; CHECK-GI-NEXT: adrp x8, .LCPI23_1706; CHECK-GI-NEXT: cmlt v16.2d, v1.2d, #0707; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI23_1]708; CHECK-GI-NEXT: cmlt v17.2d, v2.2d, #0709; CHECK-GI-NEXT: cmlt v18.2d, v3.2d, #0710; CHECK-GI-NEXT: adrp x8, .LCPI23_3711; CHECK-GI-NEXT: mov v4.h[1], w9712; CHECK-GI-NEXT: neg v5.2d, v5.2d713; CHECK-GI-NEXT: ldr q19, [x8, :lo12:.LCPI23_3]714; CHECK-GI-NEXT: neg v19.2d, v19.2d715; CHECK-GI-NEXT: ushl v7.2d, v7.2d, v5.2d716; CHECK-GI-NEXT: ushl v5.2d, v17.2d, v5.2d717; CHECK-GI-NEXT: mov v4.h[2], w9718; CHECK-GI-NEXT: add v7.2d, v0.2d, v7.2d719; CHECK-GI-NEXT: add v5.2d, v2.2d, v5.2d720; CHECK-GI-NEXT: mov v4.h[3], w9721; CHECK-GI-NEXT: adrp x9, .LCPI23_0722; CHECK-GI-NEXT: ldr q6, [x9, :lo12:.LCPI23_0]723; CHECK-GI-NEXT: adrp x9, .LCPI23_2724; CHECK-GI-NEXT: sshl v7.2d, v7.2d, v19.2d725; CHECK-GI-NEXT: ldr q20, [x9, :lo12:.LCPI23_2]726; CHECK-GI-NEXT: sshl v5.2d, v5.2d, v19.2d727; CHECK-GI-NEXT: neg v6.2d, v6.2d728; CHECK-GI-NEXT: ushll v4.4s, v4.4h, #0729; CHECK-GI-NEXT: neg v20.2d, v20.2d730; CHECK-GI-NEXT: ushl v16.2d, v16.2d, v6.2d731; CHECK-GI-NEXT: ushl v6.2d, v18.2d, v6.2d732; CHECK-GI-NEXT: ushll v17.2d, v4.2s, #0733; CHECK-GI-NEXT: ushll2 v18.2d, v4.4s, #0734; CHECK-GI-NEXT: ushll v4.2d, v4.2s, #0735; CHECK-GI-NEXT: add v16.2d, v1.2d, v16.2d736; CHECK-GI-NEXT: add v6.2d, v3.2d, v6.2d737; CHECK-GI-NEXT: shl v17.2d, v17.2d, #63738; CHECK-GI-NEXT: shl v18.2d, v18.2d, #63739; CHECK-GI-NEXT: shl v4.2d, v4.2d, #63740; CHECK-GI-NEXT: sshl v16.2d, v16.2d, v20.2d741; CHECK-GI-NEXT: sshl v6.2d, v6.2d, v20.2d742; CHECK-GI-NEXT: cmlt v17.2d, v17.2d, #0743; CHECK-GI-NEXT: cmlt v18.2d, v18.2d, #0744; CHECK-GI-NEXT: cmlt v4.2d, v4.2d, #0745; CHECK-GI-NEXT: bif v0.16b, v7.16b, v17.16b746; CHECK-GI-NEXT: bif v1.16b, v16.16b, v18.16b747; CHECK-GI-NEXT: bif v2.16b, v5.16b, v4.16b748; CHECK-GI-NEXT: bif v3.16b, v6.16b, v18.16b749; CHECK-GI-NEXT: ret750 %1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16>751 ret <8 x i64> %1752}753 754define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {755; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:756; CHECK-SD: // %bb.0:757; CHECK-SD-NEXT: adrp x8, .LCPI24_0758; CHECK-SD-NEXT: cmlt v1.4s, v0.4s, #0759; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI24_0]760; CHECK-SD-NEXT: adrp x8, .LCPI24_1761; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v2.4s762; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI24_1]763; CHECK-SD-NEXT: adrp x8, .LCPI24_2764; CHECK-SD-NEXT: add v1.4s, v0.4s, v1.4s765; CHECK-SD-NEXT: sshl v1.4s, v1.4s, v2.4s766; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI24_2]767; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b768; CHECK-SD-NEXT: movi v1.2d, #0xffffffff00000000769; CHECK-SD-NEXT: neg v2.4s, v0.4s770; CHECK-SD-NEXT: bit v0.16b, v2.16b, v1.16b771; CHECK-SD-NEXT: ret772;773; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:774; CHECK-GI: // %bb.0:775; CHECK-GI-NEXT: mov w8, #1 // =0x1776; CHECK-GI-NEXT: mov w9, #0 // =0x0777; CHECK-GI-NEXT: adrp x10, .LCPI24_0778; CHECK-GI-NEXT: fmov s1, w8779; CHECK-GI-NEXT: ldr q2, [x10, :lo12:.LCPI24_0]780; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0781; CHECK-GI-NEXT: fmov s4, w9782; CHECK-GI-NEXT: adrp x10, .LCPI24_1783; CHECK-GI-NEXT: neg v2.4s, v2.4s784; CHECK-GI-NEXT: mov v1.s[1], w9785; CHECK-GI-NEXT: mov v4.s[1], w8786; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s787; CHECK-GI-NEXT: ldr q3, [x10, :lo12:.LCPI24_1]788; CHECK-GI-NEXT: mov v1.s[2], w9789; CHECK-GI-NEXT: neg v3.4s, v3.4s790; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s791; CHECK-GI-NEXT: mov v4.d[1], v4.d[0]792; CHECK-GI-NEXT: mov v1.s[3], w9793; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v3.4s794; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31795; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0796; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b797; CHECK-GI-NEXT: shl v1.4s, v4.4s, #31798; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0799; CHECK-GI-NEXT: neg v2.4s, v0.4s800; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b801; CHECK-GI-NEXT: ret802 %1 = sdiv <4 x i32> %x, <i32 1, i32 -4, i32 8, i32 -16>803 ret <4 x i32> %1804}805 806; PR37119807define <16 x i8> @non_splat_minus_one_divisor_0(<16 x i8> %A) {808; CHECK-SD-LABEL: non_splat_minus_one_divisor_0:809; CHECK-SD: // %bb.0:810; CHECK-SD-NEXT: umov w9, v0.b[0]811; CHECK-SD-NEXT: mov w8, wzr812; CHECK-SD-NEXT: umov w10, v0.b[1]813; CHECK-SD-NEXT: sub w9, w8, w9, sxtb814; CHECK-SD-NEXT: sub w10, w8, w10, sxtb815; CHECK-SD-NEXT: fmov s1, w9816; CHECK-SD-NEXT: smov w9, v0.b[2]817; CHECK-SD-NEXT: mov v1.b[1], w10818; CHECK-SD-NEXT: umov w10, v0.b[3]819; CHECK-SD-NEXT: mov v1.b[2], w9820; CHECK-SD-NEXT: sub w9, w8, w10, sxtb821; CHECK-SD-NEXT: umov w10, v0.b[4]822; CHECK-SD-NEXT: mov v1.b[3], w9823; CHECK-SD-NEXT: sub w9, w8, w10, sxtb824; CHECK-SD-NEXT: umov w10, v0.b[5]825; CHECK-SD-NEXT: mov v1.b[4], w9826; CHECK-SD-NEXT: sub w9, w8, w10, sxtb827; CHECK-SD-NEXT: umov w10, v0.b[7]828; CHECK-SD-NEXT: mov v1.b[5], w9829; CHECK-SD-NEXT: smov w9, v0.b[6]830; CHECK-SD-NEXT: mov v1.b[6], w9831; CHECK-SD-NEXT: sub w9, w8, w10, sxtb832; CHECK-SD-NEXT: umov w10, v0.b[8]833; CHECK-SD-NEXT: mov v1.b[7], w9834; CHECK-SD-NEXT: sub w8, w8, w10, sxtb835; CHECK-SD-NEXT: mov v1.b[8], w8836; CHECK-SD-NEXT: smov w8, v0.b[9]837; CHECK-SD-NEXT: mov v1.b[9], w8838; CHECK-SD-NEXT: smov w8, v0.b[10]839; CHECK-SD-NEXT: mov v1.b[10], w8840; CHECK-SD-NEXT: smov w8, v0.b[11]841; CHECK-SD-NEXT: mov v1.b[11], w8842; CHECK-SD-NEXT: smov w8, v0.b[12]843; CHECK-SD-NEXT: mov v1.b[12], w8844; CHECK-SD-NEXT: smov w8, v0.b[13]845; CHECK-SD-NEXT: mov v1.b[13], w8846; CHECK-SD-NEXT: smov w8, v0.b[14]847; CHECK-SD-NEXT: mov v1.b[14], w8848; CHECK-SD-NEXT: smov w8, v0.b[15]849; CHECK-SD-NEXT: mov v1.b[15], w8850; CHECK-SD-NEXT: mov v0.16b, v1.16b851; CHECK-SD-NEXT: ret852;853; CHECK-GI-LABEL: non_splat_minus_one_divisor_0:854; CHECK-GI: // %bb.0:855; CHECK-GI-NEXT: adrp x8, .LCPI25_0856; CHECK-GI-NEXT: neg v2.16b, v0.16b857; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI25_0]858; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7859; CHECK-GI-NEXT: cmlt v1.16b, v1.16b, #0860; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b861; CHECK-GI-NEXT: ret862 %div = sdiv <16 x i8> %A, <i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>863 ret <16 x i8> %div864}865 866define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) {867; CHECK-SD-LABEL: non_splat_minus_one_divisor_1:868; CHECK-SD: // %bb.0:869; CHECK-SD-NEXT: adrp x8, .LCPI26_0870; CHECK-SD-NEXT: cmlt v1.16b, v0.16b, #0871; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI26_0]872; CHECK-SD-NEXT: adrp x8, .LCPI26_1873; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v2.16b874; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI26_1]875; CHECK-SD-NEXT: adrp x8, .LCPI26_2876; CHECK-SD-NEXT: add v1.16b, v0.16b, v1.16b877; CHECK-SD-NEXT: sshl v1.16b, v1.16b, v2.16b878; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI26_2]879; CHECK-SD-NEXT: adrp x8, .LCPI26_3880; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b881; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI26_3]882; CHECK-SD-NEXT: neg v1.16b, v0.16b883; CHECK-SD-NEXT: bit v0.16b, v1.16b, v2.16b884; CHECK-SD-NEXT: ret885;886; CHECK-GI-LABEL: non_splat_minus_one_divisor_1:887; CHECK-GI: // %bb.0:888; CHECK-GI-NEXT: adrp x8, .LCPI26_2889; CHECK-GI-NEXT: cmlt v2.16b, v0.16b, #0890; CHECK-GI-NEXT: adrp x9, .LCPI26_1891; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI26_2]892; CHECK-GI-NEXT: adrp x8, .LCPI26_3893; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI26_1]894; CHECK-GI-NEXT: neg v1.16b, v1.16b895; CHECK-GI-NEXT: shl v3.16b, v3.16b, #7896; CHECK-GI-NEXT: ushl v1.16b, v2.16b, v1.16b897; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI26_3]898; CHECK-GI-NEXT: adrp x8, .LCPI26_0899; CHECK-GI-NEXT: neg v2.16b, v2.16b900; CHECK-GI-NEXT: add v1.16b, v0.16b, v1.16b901; CHECK-GI-NEXT: sshl v1.16b, v1.16b, v2.16b902; CHECK-GI-NEXT: cmlt v2.16b, v3.16b, #0903; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI26_0]904; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b905; CHECK-GI-NEXT: shl v1.16b, v3.16b, #7906; CHECK-GI-NEXT: cmlt v1.16b, v1.16b, #0907; CHECK-GI-NEXT: neg v2.16b, v0.16b908; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b909; CHECK-GI-NEXT: ret910 %div = sdiv <16 x i8> %A, <i8 -1, i8 -1, i8 2, i8 -1, i8 -1, i8 -1, i8 2, i8 -1, i8 -1, i8 2, i8 2, i8 2, i8 2, i8 -128, i8 2, i8 -128>911 ret <16 x i8> %div912}913 914define <4 x i32> @non_splat_minus_one_divisor_2(<4 x i32> %A) {915; CHECK-SD-LABEL: non_splat_minus_one_divisor_2:916; CHECK-SD: // %bb.0:917; CHECK-SD-NEXT: adrp x8, .LCPI27_0918; CHECK-SD-NEXT: cmlt v1.4s, v0.4s, #0919; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_0]920; CHECK-SD-NEXT: adrp x8, .LCPI27_1921; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v2.4s922; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_1]923; CHECK-SD-NEXT: adrp x8, .LCPI27_2924; CHECK-SD-NEXT: add v1.4s, v0.4s, v1.4s925; CHECK-SD-NEXT: sshl v1.4s, v1.4s, v2.4s926; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_2]927; CHECK-SD-NEXT: adrp x8, .LCPI27_3928; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b929; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_3]930; CHECK-SD-NEXT: neg v1.4s, v0.4s931; CHECK-SD-NEXT: bit v0.16b, v1.16b, v2.16b932; CHECK-SD-NEXT: ret933;934; CHECK-GI-LABEL: non_splat_minus_one_divisor_2:935; CHECK-GI: // %bb.0:936; CHECK-GI-NEXT: mov w8, #1 // =0x1937; CHECK-GI-NEXT: adrp x9, .LCPI27_0938; CHECK-GI-NEXT: mov w10, #0 // =0x0939; CHECK-GI-NEXT: fmov s1, w8940; CHECK-GI-NEXT: ldr q2, [x9, :lo12:.LCPI27_0]941; CHECK-GI-NEXT: fmov s4, w8942; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0943; CHECK-GI-NEXT: adrp x9, .LCPI27_1944; CHECK-GI-NEXT: neg v2.4s, v2.4s945; CHECK-GI-NEXT: mov v1.s[1], w8946; CHECK-GI-NEXT: mov v4.s[1], w10947; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s948; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI27_1]949; CHECK-GI-NEXT: mov v1.s[2], w10950; CHECK-GI-NEXT: mov v4.s[2], w10951; CHECK-GI-NEXT: neg v3.4s, v3.4s952; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s953; CHECK-GI-NEXT: mov v1.s[3], w10954; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v3.4s955; CHECK-GI-NEXT: mov v4.s[3], w8956; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31957; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0958; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b959; CHECK-GI-NEXT: shl v1.4s, v4.4s, #31960; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0961; CHECK-GI-NEXT: neg v2.4s, v0.4s962; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b963; CHECK-GI-NEXT: ret964 %div = sdiv <4 x i32> %A, <i32 -1, i32 1, i32 2, i32 -2>965 ret <4 x i32> %div966}967 968define <8 x i16> @combine_vec_sdiv_nonuniform(<8 x i16> %x) {969; CHECK-LABEL: combine_vec_sdiv_nonuniform:970; CHECK: // %bb.0:971; CHECK-NEXT: adrp x8, .LCPI28_0972; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI28_0]973; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h974; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h975; CHECK-NEXT: uzp2 v0.8h, v0.8h, v2.8h976; CHECK-NEXT: usra v0.8h, v0.8h, #15977; CHECK-NEXT: ret978 %1 = sdiv <8 x i16> %x, <i16 3, i16 3, i16 3, i16 3, i16 22, i16 22, i16 22, i16 22>979 ret <8 x i16> %1980}981 982define <8 x i16> @combine_vec_sdiv_nonuniform2(<8 x i16> %x) {983; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform2:984; CHECK-SD: // %bb.0:985; CHECK-SD-NEXT: adrp x8, .LCPI29_0986; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI29_0]987; CHECK-SD-NEXT: adrp x8, .LCPI29_1988; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h989; CHECK-SD-NEXT: smull v0.4s, v0.4h, v1.4h990; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI29_1]991; CHECK-SD-NEXT: uzp2 v0.8h, v0.8h, v2.8h992; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h993; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15994; CHECK-SD-NEXT: ret995;996; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform2:997; CHECK-GI: // %bb.0:998; CHECK-GI-NEXT: adrp x8, .LCPI29_1999; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI29_1]1000; CHECK-GI-NEXT: adrp x8, .LCPI29_01001; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h1002; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h1003; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI29_0]1004; CHECK-GI-NEXT: neg v1.8h, v1.8h1005; CHECK-GI-NEXT: uzp2 v0.8h, v0.8h, v2.8h1006; CHECK-GI-NEXT: sshl v0.8h, v0.8h, v1.8h1007; CHECK-GI-NEXT: usra v0.8h, v0.8h, #151008; CHECK-GI-NEXT: ret1009 %1 = sdiv <8 x i16> %x, <i16 24, i16 24, i16 24, i16 24, i16 25, i16 25, i16 25, i16 25>1010 ret <8 x i16> %11011}1012 1013define <8 x i16> @combine_vec_sdiv_nonuniform3(<8 x i16> %x) {1014; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform3:1015; CHECK-SD: // %bb.0:1016; CHECK-SD-NEXT: adrp x8, .LCPI30_01017; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]1018; CHECK-SD-NEXT: adrp x8, .LCPI30_11019; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h1020; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h1021; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h1022; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h1023; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]1024; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h1025; CHECK-SD-NEXT: usra v0.8h, v0.8h, #151026; CHECK-SD-NEXT: ret1027;1028; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform3:1029; CHECK-GI: // %bb.0:1030; CHECK-GI-NEXT: adrp x8, .LCPI30_11031; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]1032; CHECK-GI-NEXT: adrp x8, .LCPI30_01033; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h1034; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h1035; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h1036; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_0]1037; CHECK-GI-NEXT: add v0.8h, v1.8h, v0.8h1038; CHECK-GI-NEXT: neg v1.8h, v2.8h1039; CHECK-GI-NEXT: sshl v0.8h, v0.8h, v1.8h1040; CHECK-GI-NEXT: usra v0.8h, v0.8h, #151041; CHECK-GI-NEXT: ret1042 %1 = sdiv <8 x i16> %x, <i16 23, i16 23, i16 23, i16 23, i16 511, i16 511, i16 511, i16 511>1043 ret <8 x i16> %11044}1045 1046define <8 x i16> @combine_vec_sdiv_nonuniform4(<8 x i16> %x) {1047; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform4:1048; CHECK-SD: // %bb.0:1049; CHECK-SD-NEXT: adrp x8, .LCPI31_01050; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI31_0]1051; CHECK-SD-NEXT: adrp x8, .LCPI31_11052; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h1053; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h1054; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h1055; CHECK-SD-NEXT: sub v0.8h, v1.8h, v0.8h1056; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI31_1]1057; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h1058; CHECK-SD-NEXT: usra v0.8h, v0.8h, #151059; CHECK-SD-NEXT: ret1060;1061; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform4:1062; CHECK-GI: // %bb.0:1063; CHECK-GI-NEXT: adrp x8, .LCPI31_11064; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI31_1]1065; CHECK-GI-NEXT: adrp x8, .LCPI31_01066; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h1067; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h1068; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h1069; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]1070; CHECK-GI-NEXT: sub v0.8h, v1.8h, v0.8h1071; CHECK-GI-NEXT: neg v1.8h, v2.8h1072; CHECK-GI-NEXT: sshl v0.8h, v0.8h, v1.8h1073; CHECK-GI-NEXT: usra v0.8h, v0.8h, #151074; CHECK-GI-NEXT: ret1075 %1 = sdiv <8 x i16> %x, <i16 -23, i16 -23, i16 -23, i16 -23, i16 -510, i16 -510, i16 -510, i16 -510>1076 ret <8 x i16> %11077}1078 1079define <8 x i16> @combine_vec_sdiv_nonuniform5(<8 x i16> %x) {1080; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform5:1081; CHECK-SD: // %bb.0:1082; CHECK-SD-NEXT: adrp x8, .LCPI32_01083; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI32_0]1084; CHECK-SD-NEXT: adrp x8, .LCPI32_11085; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h1086; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h1087; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h1088; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI32_1]1089; CHECK-SD-NEXT: adrp x8, .LCPI32_21090; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h1091; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI32_2]1092; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h1093; CHECK-SD-NEXT: usra v0.8h, v0.8h, #151094; CHECK-SD-NEXT: ret1095;1096; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform5:1097; CHECK-GI: // %bb.0:1098; CHECK-GI-NEXT: adrp x8, .LCPI32_21099; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI32_2]1100; CHECK-GI-NEXT: adrp x8, .LCPI32_11101; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h1102; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h1103; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h1104; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI32_1]1105; CHECK-GI-NEXT: adrp x8, .LCPI32_01106; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI32_0]1107; CHECK-GI-NEXT: mla v1.8h, v0.8h, v2.8h1108; CHECK-GI-NEXT: neg v0.8h, v3.8h1109; CHECK-GI-NEXT: sshl v0.8h, v1.8h, v0.8h1110; CHECK-GI-NEXT: usra v0.8h, v0.8h, #151111; CHECK-GI-NEXT: ret1112 %1 = sdiv <8 x i16> %x, <i16 -510, i16 -24, i16 -23, i16 3, i16 22, i16 25, i16 255, i16 511>1113 ret <8 x i16> %11114}1115 1116define <8 x i16> @combine_vec_sdiv_nonuniform6(<8 x i16> %x) {1117; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform6:1118; CHECK-SD: // %bb.0:1119; CHECK-SD-NEXT: adrp x8, .LCPI33_01120; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI33_0]1121; CHECK-SD-NEXT: adrp x8, .LCPI33_11122; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h1123; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h1124; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h1125; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]1126; CHECK-SD-NEXT: adrp x8, .LCPI33_21127; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h1128; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI33_2]1129; CHECK-SD-NEXT: adrp x8, .LCPI33_31130; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_3]1131; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h1132; CHECK-SD-NEXT: ushr v1.8h, v0.8h, #151133; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1134; CHECK-SD-NEXT: add v0.8h, v0.8h, v1.8h1135; CHECK-SD-NEXT: ret1136;1137; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform6:1138; CHECK-GI: // %bb.0:1139; CHECK-GI-NEXT: adrp x8, .LCPI33_31140; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI33_3]1141; CHECK-GI-NEXT: adrp x8, .LCPI33_21142; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h1143; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h1144; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h1145; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_2]1146; CHECK-GI-NEXT: adrp x8, .LCPI33_11147; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI33_1]1148; CHECK-GI-NEXT: adrp x8, .LCPI33_01149; CHECK-GI-NEXT: mla v1.8h, v0.8h, v2.8h1150; CHECK-GI-NEXT: neg v0.8h, v3.8h1151; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]1152; CHECK-GI-NEXT: sshl v0.8h, v1.8h, v0.8h1153; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #151154; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b1155; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h1156; CHECK-GI-NEXT: ret1157 %1 = sdiv <8 x i16> %x, <i16 -32768, i16 -512, i16 -511, i16 -1, i16 1, i16 255, i16 512, i16 32767>1158 ret <8 x i16> %11159}1160 1161define <8 x i16> @combine_vec_sdiv_nonuniform7(<8 x i16> %x) {1162; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform7:1163; CHECK-SD: // %bb.0:1164; CHECK-SD-NEXT: umov w9, v0.h[0]1165; CHECK-SD-NEXT: mov w8, wzr1166; CHECK-SD-NEXT: umov w10, v0.h[1]1167; CHECK-SD-NEXT: umov w11, v0.h[2]1168; CHECK-SD-NEXT: sub w9, w8, w9, sxth1169; CHECK-SD-NEXT: sub w10, w8, w10, sxth1170; CHECK-SD-NEXT: fmov s1, w91171; CHECK-SD-NEXT: sub w9, w8, w11, sxth1172; CHECK-SD-NEXT: mov v1.h[1], w101173; CHECK-SD-NEXT: umov w10, v0.h[3]1174; CHECK-SD-NEXT: mov v1.h[2], w91175; CHECK-SD-NEXT: sub w8, w8, w10, sxth1176; CHECK-SD-NEXT: mov v1.h[3], w81177; CHECK-SD-NEXT: smov w8, v0.h[4]1178; CHECK-SD-NEXT: mov v1.h[4], w81179; CHECK-SD-NEXT: smov w8, v0.h[5]1180; CHECK-SD-NEXT: mov v1.h[5], w81181; CHECK-SD-NEXT: smov w8, v0.h[6]1182; CHECK-SD-NEXT: mov v1.h[6], w81183; CHECK-SD-NEXT: smov w8, v0.h[7]1184; CHECK-SD-NEXT: mov v1.h[7], w81185; CHECK-SD-NEXT: mov v0.16b, v1.16b1186; CHECK-SD-NEXT: ret1187;1188; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform7:1189; CHECK-GI: // %bb.0:1190; CHECK-GI-NEXT: adrp x8, .LCPI34_01191; CHECK-GI-NEXT: neg v2.8h, v0.8h1192; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI34_0]1193; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #01194; CHECK-GI-NEXT: shl v1.8h, v1.8h, #151195; CHECK-GI-NEXT: cmlt v1.8h, v1.8h, #01196; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b1197; CHECK-GI-NEXT: ret1198 %1 = sdiv <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 1, i16 1, i16 1, i16 1>1199 ret <8 x i16> %11200}1201 1202define <16 x i8> @pr38658(<16 x i8> %x) {1203; CHECK-SD-LABEL: pr38658:1204; CHECK-SD: // %bb.0:1205; CHECK-SD-NEXT: adrp x8, .LCPI35_01206; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_0]1207; CHECK-SD-NEXT: adrp x8, .LCPI35_11208; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b1209; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b1210; CHECK-SD-NEXT: uzp2 v1.16b, v1.16b, v2.16b1211; CHECK-SD-NEXT: add v0.16b, v1.16b, v0.16b1212; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_1]1213; CHECK-SD-NEXT: sshl v0.16b, v0.16b, v1.16b1214; CHECK-SD-NEXT: movi v1.2d, #00000000000000001215; CHECK-SD-NEXT: ushr v2.16b, v0.16b, #71216; CHECK-SD-NEXT: mov v1.b[15], v2.b[15]1217; CHECK-SD-NEXT: add v0.16b, v0.16b, v1.16b1218; CHECK-SD-NEXT: ret1219;1220; CHECK-GI-LABEL: pr38658:1221; CHECK-GI: // %bb.0:1222; CHECK-GI-NEXT: adrp x8, .LCPI35_21223; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI35_2]1224; CHECK-GI-NEXT: adrp x8, .LCPI35_11225; CHECK-GI-NEXT: smull2 v2.8h, v0.16b, v1.16b1226; CHECK-GI-NEXT: smull v1.8h, v0.8b, v1.8b1227; CHECK-GI-NEXT: uzp2 v1.16b, v1.16b, v2.16b1228; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI35_1]1229; CHECK-GI-NEXT: adrp x8, .LCPI35_01230; CHECK-GI-NEXT: add v0.16b, v1.16b, v0.16b1231; CHECK-GI-NEXT: neg v1.16b, v2.16b1232; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI35_0]1233; CHECK-GI-NEXT: sshl v0.16b, v0.16b, v1.16b1234; CHECK-GI-NEXT: ushr v1.16b, v0.16b, #71235; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b1236; CHECK-GI-NEXT: add v0.16b, v0.16b, v1.16b1237; CHECK-GI-NEXT: ret1238 %1 = sdiv <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 7>1239 ret <16 x i8> %11240}1241 1242define i1 @bool_sdiv(i1 %x, i1 %y) {1243; CHECK-SD-LABEL: bool_sdiv:1244; CHECK-SD: // %bb.0:1245; CHECK-SD-NEXT: and w0, w0, #0x11246; CHECK-SD-NEXT: ret1247;1248; CHECK-GI-LABEL: bool_sdiv:1249; CHECK-GI: // %bb.0:1250; CHECK-GI-NEXT: sbfx w8, w0, #0, #11251; CHECK-GI-NEXT: sbfx w9, w1, #0, #11252; CHECK-GI-NEXT: sdiv w8, w8, w91253; CHECK-GI-NEXT: and w0, w8, #0x11254; CHECK-GI-NEXT: ret1255 %r = sdiv i1 %x, %y1256 ret i1 %r1257}1258 1259define <4 x i1> @boolvec_sdiv(<4 x i1> %x, <4 x i1> %y) {1260; CHECK-SD-LABEL: boolvec_sdiv:1261; CHECK-SD: // %bb.0:1262; CHECK-SD-NEXT: ret1263;1264; CHECK-GI-LABEL: boolvec_sdiv:1265; CHECK-GI: // %bb.0:1266; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01267; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11268; CHECK-GI-NEXT: umov w8, v0.h[0]1269; CHECK-GI-NEXT: umov w9, v1.h[0]1270; CHECK-GI-NEXT: umov w10, v1.h[1]1271; CHECK-GI-NEXT: umov w11, v1.h[2]1272; CHECK-GI-NEXT: umov w12, v1.h[3]1273; CHECK-GI-NEXT: sbfx w8, w8, #0, #11274; CHECK-GI-NEXT: sbfx w9, w9, #0, #11275; CHECK-GI-NEXT: sbfx w10, w10, #0, #11276; CHECK-GI-NEXT: sbfx w11, w11, #0, #11277; CHECK-GI-NEXT: sbfx w12, w12, #0, #11278; CHECK-GI-NEXT: sdiv w8, w8, w91279; CHECK-GI-NEXT: umov w9, v0.h[1]1280; CHECK-GI-NEXT: sbfx w9, w9, #0, #11281; CHECK-GI-NEXT: sdiv w9, w9, w101282; CHECK-GI-NEXT: umov w10, v0.h[2]1283; CHECK-GI-NEXT: sbfx w10, w10, #0, #11284; CHECK-GI-NEXT: sdiv w10, w10, w111285; CHECK-GI-NEXT: umov w11, v0.h[3]1286; CHECK-GI-NEXT: fmov s0, w81287; CHECK-GI-NEXT: mov v0.h[1], w91288; CHECK-GI-NEXT: sbfx w11, w11, #0, #11289; CHECK-GI-NEXT: sdiv w8, w11, w121290; CHECK-GI-NEXT: mov v0.h[2], w101291; CHECK-GI-NEXT: mov v0.h[3], w81292; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01293; CHECK-GI-NEXT: ret1294 %r = sdiv <4 x i1> %x, %y1295 ret <4 x i1> %r1296}1297 1298define i32 @combine_sdiv_two(i32 %x) {1299; CHECK-SD-LABEL: combine_sdiv_two:1300; CHECK-SD: // %bb.0:1301; CHECK-SD-NEXT: add w8, w0, w0, lsr #311302; CHECK-SD-NEXT: asr w0, w8, #11303; CHECK-SD-NEXT: ret1304;1305; CHECK-GI-LABEL: combine_sdiv_two:1306; CHECK-GI: // %bb.0:1307; CHECK-GI-NEXT: asr w8, w0, #311308; CHECK-GI-NEXT: add w8, w0, w8, lsr #311309; CHECK-GI-NEXT: asr w0, w8, #11310; CHECK-GI-NEXT: ret1311 %1 = sdiv i32 %x, 21312 ret i32 %11313}1314 1315define i32 @combine_sdiv_negtwo(i32 %x) {1316; CHECK-SD-LABEL: combine_sdiv_negtwo:1317; CHECK-SD: // %bb.0:1318; CHECK-SD-NEXT: add w8, w0, w0, lsr #311319; CHECK-SD-NEXT: neg w0, w8, asr #11320; CHECK-SD-NEXT: ret1321;1322; CHECK-GI-LABEL: combine_sdiv_negtwo:1323; CHECK-GI: // %bb.0:1324; CHECK-GI-NEXT: asr w8, w0, #311325; CHECK-GI-NEXT: add w8, w0, w8, lsr #311326; CHECK-GI-NEXT: neg w0, w8, asr #11327; CHECK-GI-NEXT: ret1328 %1 = sdiv i32 %x, -21329 ret i32 %11330}1331 1332define i8 @combine_i8_sdiv_pow2(i8 %x) {1333; CHECK-SD-LABEL: combine_i8_sdiv_pow2:1334; CHECK-SD: // %bb.0:1335; CHECK-SD-NEXT: sxtb w8, w01336; CHECK-SD-NEXT: ubfx w8, w8, #11, #41337; CHECK-SD-NEXT: add w8, w0, w81338; CHECK-SD-NEXT: sbfx w0, w8, #4, #41339; CHECK-SD-NEXT: ret1340;1341; CHECK-GI-LABEL: combine_i8_sdiv_pow2:1342; CHECK-GI: // %bb.0:1343; CHECK-GI-NEXT: sbfx w8, w0, #7, #11344; CHECK-GI-NEXT: ubfx w8, w8, #4, #41345; CHECK-GI-NEXT: add w8, w0, w81346; CHECK-GI-NEXT: sbfx w0, w8, #4, #41347; CHECK-GI-NEXT: ret1348 %1 = sdiv i8 %x, 161349 ret i8 %11350}1351 1352define i8 @combine_i8_sdiv_negpow2(i8 %x) {1353; CHECK-SD-LABEL: combine_i8_sdiv_negpow2:1354; CHECK-SD: // %bb.0:1355; CHECK-SD-NEXT: sxtb w8, w01356; CHECK-SD-NEXT: ubfx w8, w8, #9, #61357; CHECK-SD-NEXT: add w8, w0, w81358; CHECK-SD-NEXT: sxtb w8, w81359; CHECK-SD-NEXT: neg w0, w8, asr #61360; CHECK-SD-NEXT: ret1361;1362; CHECK-GI-LABEL: combine_i8_sdiv_negpow2:1363; CHECK-GI: // %bb.0:1364; CHECK-GI-NEXT: sbfx w8, w0, #7, #11365; CHECK-GI-NEXT: ubfx w8, w8, #2, #61366; CHECK-GI-NEXT: add w8, w0, w81367; CHECK-GI-NEXT: sxtb w8, w81368; CHECK-GI-NEXT: neg w0, w8, asr #61369; CHECK-GI-NEXT: ret1370 %1 = sdiv i8 %x, -641371 ret i8 %11372}1373 1374define i16 @combine_i16_sdiv_pow2(i16 %x) {1375; CHECK-SD-LABEL: combine_i16_sdiv_pow2:1376; CHECK-SD: // %bb.0:1377; CHECK-SD-NEXT: sxth w8, w01378; CHECK-SD-NEXT: ubfx w8, w8, #27, #41379; CHECK-SD-NEXT: add w8, w0, w81380; CHECK-SD-NEXT: sbfx w0, w8, #4, #121381; CHECK-SD-NEXT: ret1382;1383; CHECK-GI-LABEL: combine_i16_sdiv_pow2:1384; CHECK-GI: // %bb.0:1385; CHECK-GI-NEXT: sbfx w8, w0, #15, #11386; CHECK-GI-NEXT: ubfx w8, w8, #12, #41387; CHECK-GI-NEXT: add w8, w0, w81388; CHECK-GI-NEXT: sbfx w0, w8, #4, #121389; CHECK-GI-NEXT: ret1390 %1 = sdiv i16 %x, 161391 ret i16 %11392}1393 1394define i16 @combine_i16_sdiv_negpow2(i16 %x) {1395; CHECK-SD-LABEL: combine_i16_sdiv_negpow2:1396; CHECK-SD: // %bb.0:1397; CHECK-SD-NEXT: sxth w8, w01398; CHECK-SD-NEXT: lsr w8, w8, #231399; CHECK-SD-NEXT: add w8, w0, w8, uxtb1400; CHECK-SD-NEXT: sxth w8, w81401; CHECK-SD-NEXT: neg w0, w8, asr #81402; CHECK-SD-NEXT: ret1403;1404; CHECK-GI-LABEL: combine_i16_sdiv_negpow2:1405; CHECK-GI: // %bb.0:1406; CHECK-GI-NEXT: sbfx w8, w0, #15, #11407; CHECK-GI-NEXT: ubfx w8, w8, #8, #81408; CHECK-GI-NEXT: add w8, w0, w81409; CHECK-GI-NEXT: sxth w8, w81410; CHECK-GI-NEXT: neg w0, w8, asr #81411; CHECK-GI-NEXT: ret1412 %1 = sdiv i16 %x, -2561413 ret i16 %11414}1415 1416define i32 @combine_i32_sdiv_pow2(i32 %x) {1417; CHECK-SD-LABEL: combine_i32_sdiv_pow2:1418; CHECK-SD: // %bb.0:1419; CHECK-SD-NEXT: add w8, w0, #151420; CHECK-SD-NEXT: cmp w0, #01421; CHECK-SD-NEXT: csel w8, w8, w0, mi1422; CHECK-SD-NEXT: asr w0, w8, #41423; CHECK-SD-NEXT: ret1424;1425; CHECK-GI-LABEL: combine_i32_sdiv_pow2:1426; CHECK-GI: // %bb.0:1427; CHECK-GI-NEXT: asr w8, w0, #311428; CHECK-GI-NEXT: add w8, w0, w8, lsr #281429; CHECK-GI-NEXT: asr w0, w8, #41430; CHECK-GI-NEXT: ret1431 %1 = sdiv i32 %x, 161432 ret i32 %11433}1434 1435define i32 @combine_i32_sdiv_negpow2(i32 %x) {1436; CHECK-SD-LABEL: combine_i32_sdiv_negpow2:1437; CHECK-SD: // %bb.0:1438; CHECK-SD-NEXT: add w8, w0, #2551439; CHECK-SD-NEXT: cmp w0, #01440; CHECK-SD-NEXT: csel w8, w8, w0, mi1441; CHECK-SD-NEXT: neg w0, w8, asr #81442; CHECK-SD-NEXT: ret1443;1444; CHECK-GI-LABEL: combine_i32_sdiv_negpow2:1445; CHECK-GI: // %bb.0:1446; CHECK-GI-NEXT: asr w8, w0, #311447; CHECK-GI-NEXT: add w8, w0, w8, lsr #241448; CHECK-GI-NEXT: neg w0, w8, asr #81449; CHECK-GI-NEXT: ret1450 %1 = sdiv i32 %x, -2561451 ret i32 %11452}1453 1454define i64 @combine_i64_sdiv_pow2(i64 %x) {1455; CHECK-SD-LABEL: combine_i64_sdiv_pow2:1456; CHECK-SD: // %bb.0:1457; CHECK-SD-NEXT: add x8, x0, #151458; CHECK-SD-NEXT: cmp x0, #01459; CHECK-SD-NEXT: csel x8, x8, x0, mi1460; CHECK-SD-NEXT: asr x0, x8, #41461; CHECK-SD-NEXT: ret1462;1463; CHECK-GI-LABEL: combine_i64_sdiv_pow2:1464; CHECK-GI: // %bb.0:1465; CHECK-GI-NEXT: asr x8, x0, #631466; CHECK-GI-NEXT: add x8, x0, x8, lsr #601467; CHECK-GI-NEXT: asr x0, x8, #41468; CHECK-GI-NEXT: ret1469 %1 = sdiv i64 %x, 161470 ret i64 %11471}1472 1473define i64 @combine_i64_sdiv_negpow2(i64 %x) {1474; CHECK-SD-LABEL: combine_i64_sdiv_negpow2:1475; CHECK-SD: // %bb.0:1476; CHECK-SD-NEXT: add x8, x0, #2551477; CHECK-SD-NEXT: cmp x0, #01478; CHECK-SD-NEXT: csel x8, x8, x0, mi1479; CHECK-SD-NEXT: neg x0, x8, asr #81480; CHECK-SD-NEXT: ret1481;1482; CHECK-GI-LABEL: combine_i64_sdiv_negpow2:1483; CHECK-GI: // %bb.0:1484; CHECK-GI-NEXT: asr x8, x0, #631485; CHECK-GI-NEXT: add x8, x0, x8, lsr #561486; CHECK-GI-NEXT: neg x0, x8, asr #81487; CHECK-GI-NEXT: ret1488 %1 = sdiv i64 %x, -2561489 ret i64 %11490}1491 1492define i5 @combine_i5_sdiv_const7(i5 %x) {1493; CHECK-SD-LABEL: combine_i5_sdiv_const7:1494; CHECK-SD: // %bb.0:1495; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x01496; CHECK-SD-NEXT: sbfx x8, x0, #0, #51497; CHECK-SD-NEXT: mov x9, #-56173 // =0xffffffffffff24931498; CHECK-SD-NEXT: movk x9, #37449, lsl #161499; CHECK-SD-NEXT: smull x8, w8, w91500; CHECK-SD-NEXT: sbfx w9, w0, #0, #51501; CHECK-SD-NEXT: add x8, x9, x8, lsr #321502; CHECK-SD-NEXT: asr w9, w8, #21503; CHECK-SD-NEXT: add w0, w9, w8, lsr #311504; CHECK-SD-NEXT: ret1505;1506; CHECK-GI-LABEL: combine_i5_sdiv_const7:1507; CHECK-GI: // %bb.0:1508; CHECK-GI-NEXT: mov w8, #19 // =0x131509; CHECK-GI-NEXT: sbfx w9, w0, #0, #51510; CHECK-GI-NEXT: sbfx w8, w8, #0, #51511; CHECK-GI-NEXT: mul w8, w9, w81512; CHECK-GI-NEXT: sbfx w8, w8, #0, #101513; CHECK-GI-NEXT: add w8, w0, w8, asr #51514; CHECK-GI-NEXT: sbfx w8, w8, #0, #51515; CHECK-GI-NEXT: asr w8, w8, #21516; CHECK-GI-NEXT: ubfx w9, w8, #4, #11517; CHECK-GI-NEXT: add w0, w8, w91518; CHECK-GI-NEXT: ret1519 %1 = sdiv i5 %x, 71520 ret i5 %11521}1522 1523define i5 @combine_i5_sdiv_const100(i5 %x) {1524; CHECK-SD-LABEL: combine_i5_sdiv_const100:1525; CHECK-SD: // %bb.0:1526; CHECK-SD-NEXT: sbfx w8, w0, #4, #11527; CHECK-SD-NEXT: and w8, w8, #0x31528; CHECK-SD-NEXT: add w8, w0, w81529; CHECK-SD-NEXT: sbfx w0, w8, #2, #31530; CHECK-SD-NEXT: ret1531;1532; CHECK-GI-LABEL: combine_i5_sdiv_const100:1533; CHECK-GI: // %bb.0:1534; CHECK-GI-NEXT: sbfx w8, w0, #0, #51535; CHECK-GI-NEXT: asr w8, w8, #41536; CHECK-GI-NEXT: ubfx w8, w8, #3, #21537; CHECK-GI-NEXT: add w8, w0, w81538; CHECK-GI-NEXT: sbfx w8, w8, #0, #51539; CHECK-GI-NEXT: asr w0, w8, #21540; CHECK-GI-NEXT: ret1541 %1 = sdiv i5 %x, 1001542 ret i5 %11543}1544 1545define i8 @combine_i8_sdiv_const7(i8 %x) {1546; CHECK-SD-LABEL: combine_i8_sdiv_const7:1547; CHECK-SD: // %bb.0:1548; CHECK-SD-NEXT: sxtb w8, w01549; CHECK-SD-NEXT: mov w9, #-109 // =0xffffff931550; CHECK-SD-NEXT: mul w8, w8, w91551; CHECK-SD-NEXT: add w8, w0, w8, lsr #81552; CHECK-SD-NEXT: sbfx w9, w8, #2, #61553; CHECK-SD-NEXT: and w8, w8, #0x801554; CHECK-SD-NEXT: add w0, w9, w8, lsr #71555; CHECK-SD-NEXT: ret1556;1557; CHECK-GI-LABEL: combine_i8_sdiv_const7:1558; CHECK-GI: // %bb.0:1559; CHECK-GI-NEXT: sxtb w8, w01560; CHECK-GI-NEXT: mov w9, #-109 // =0xffffff931561; CHECK-GI-NEXT: mul w8, w8, w91562; CHECK-GI-NEXT: sxth w8, w81563; CHECK-GI-NEXT: add w8, w0, w8, asr #81564; CHECK-GI-NEXT: sbfx w8, w8, #2, #61565; CHECK-GI-NEXT: ubfx w9, w8, #7, #11566; CHECK-GI-NEXT: add w0, w8, w91567; CHECK-GI-NEXT: ret1568 %1 = sdiv i8 %x, 71569 ret i8 %11570}1571 1572define i8 @combine_i8_sdiv_const100(i8 %x) {1573; CHECK-SD-LABEL: combine_i8_sdiv_const100:1574; CHECK-SD: // %bb.0:1575; CHECK-SD-NEXT: sxtb w8, w01576; CHECK-SD-NEXT: mov w9, #41 // =0x291577; CHECK-SD-NEXT: mul w8, w8, w91578; CHECK-SD-NEXT: asr w9, w8, #121579; CHECK-SD-NEXT: add w0, w9, w8, lsr #311580; CHECK-SD-NEXT: ret1581;1582; CHECK-GI-LABEL: combine_i8_sdiv_const100:1583; CHECK-GI: // %bb.0:1584; CHECK-GI-NEXT: sxtb w8, w01585; CHECK-GI-NEXT: mov w9, #41 // =0x291586; CHECK-GI-NEXT: mul w8, w8, w91587; CHECK-GI-NEXT: sbfx w8, w8, #8, #81588; CHECK-GI-NEXT: asr w8, w8, #41589; CHECK-GI-NEXT: ubfx w9, w8, #7, #11590; CHECK-GI-NEXT: add w0, w8, w91591; CHECK-GI-NEXT: ret1592 %1 = sdiv i8 %x, 1001593 ret i8 %11594}1595 1596define i16 @combine_i16_sdiv_const7(i16 %x) {1597; CHECK-SD-LABEL: combine_i16_sdiv_const7:1598; CHECK-SD: // %bb.0:1599; CHECK-SD-NEXT: sxth w8, w01600; CHECK-SD-NEXT: mov w9, #18725 // =0x49251601; CHECK-SD-NEXT: mul w8, w8, w91602; CHECK-SD-NEXT: asr w9, w8, #171603; CHECK-SD-NEXT: add w0, w9, w8, lsr #311604; CHECK-SD-NEXT: ret1605;1606; CHECK-GI-LABEL: combine_i16_sdiv_const7:1607; CHECK-GI: // %bb.0:1608; CHECK-GI-NEXT: sxth w8, w01609; CHECK-GI-NEXT: mov w9, #18725 // =0x49251610; CHECK-GI-NEXT: mul w8, w8, w91611; CHECK-GI-NEXT: asr w8, w8, #161612; CHECK-GI-NEXT: asr w8, w8, #11613; CHECK-GI-NEXT: ubfx w9, w8, #15, #11614; CHECK-GI-NEXT: add w0, w8, w91615; CHECK-GI-NEXT: ret1616 %1 = sdiv i16 %x, 71617 ret i16 %11618}1619 1620define i16 @combine_i16_sdiv_const100(i16 %x) {1621; CHECK-SD-LABEL: combine_i16_sdiv_const100:1622; CHECK-SD: // %bb.0:1623; CHECK-SD-NEXT: sxth w8, w01624; CHECK-SD-NEXT: mov w9, #5243 // =0x147b1625; CHECK-SD-NEXT: mul w8, w8, w91626; CHECK-SD-NEXT: asr w9, w8, #191627; CHECK-SD-NEXT: add w0, w9, w8, lsr #311628; CHECK-SD-NEXT: ret1629;1630; CHECK-GI-LABEL: combine_i16_sdiv_const100:1631; CHECK-GI: // %bb.0:1632; CHECK-GI-NEXT: sxth w8, w01633; CHECK-GI-NEXT: mov w9, #5243 // =0x147b1634; CHECK-GI-NEXT: mul w8, w8, w91635; CHECK-GI-NEXT: asr w8, w8, #161636; CHECK-GI-NEXT: asr w8, w8, #31637; CHECK-GI-NEXT: ubfx w9, w8, #15, #11638; CHECK-GI-NEXT: add w0, w8, w91639; CHECK-GI-NEXT: ret1640 %1 = sdiv i16 %x, 1001641 ret i16 %11642}1643 1644define i32 @combine_i32_sdiv_const7(i32 %x) {1645; CHECK-SD-LABEL: combine_i32_sdiv_const7:1646; CHECK-SD: // %bb.0:1647; CHECK-SD-NEXT: mov w8, #9363 // =0x24931648; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x01649; CHECK-SD-NEXT: movk w8, #37449, lsl #161650; CHECK-SD-NEXT: smull x8, w0, w81651; CHECK-SD-NEXT: add x8, x0, x8, lsr #321652; CHECK-SD-NEXT: asr w9, w8, #21653; CHECK-SD-NEXT: add w0, w9, w8, lsr #311654; CHECK-SD-NEXT: ret1655;1656; CHECK-GI-LABEL: combine_i32_sdiv_const7:1657; CHECK-GI: // %bb.0:1658; CHECK-GI-NEXT: mov w8, #9363 // =0x24931659; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x01660; CHECK-GI-NEXT: movk w8, #37449, lsl #161661; CHECK-GI-NEXT: smull x8, w0, w81662; CHECK-GI-NEXT: add x8, x0, x8, asr #321663; CHECK-GI-NEXT: asr w8, w8, #21664; CHECK-GI-NEXT: add w0, w8, w8, lsr #311665; CHECK-GI-NEXT: ret1666 %1 = sdiv i32 %x, 71667 ret i32 %11668}1669 1670define i32 @combine_i32_sdiv_const100(i32 %x) {1671; CHECK-SD-LABEL: combine_i32_sdiv_const100:1672; CHECK-SD: // %bb.0:1673; CHECK-SD-NEXT: mov w8, #34079 // =0x851f1674; CHECK-SD-NEXT: movk w8, #20971, lsl #161675; CHECK-SD-NEXT: smull x8, w0, w81676; CHECK-SD-NEXT: asr x8, x8, #371677; CHECK-SD-NEXT: add w0, w8, w8, lsr #311678; CHECK-SD-NEXT: ret1679;1680; CHECK-GI-LABEL: combine_i32_sdiv_const100:1681; CHECK-GI: // %bb.0:1682; CHECK-GI-NEXT: mov w8, #34079 // =0x851f1683; CHECK-GI-NEXT: movk w8, #20971, lsl #161684; CHECK-GI-NEXT: smull x8, w0, w81685; CHECK-GI-NEXT: asr x8, x8, #321686; CHECK-GI-NEXT: asr w8, w8, #51687; CHECK-GI-NEXT: add w0, w8, w8, lsr #311688; CHECK-GI-NEXT: ret1689 %1 = sdiv i32 %x, 1001690 ret i32 %11691}1692 1693define i64 @combine_i64_sdiv_const7(i64 %x) {1694; CHECK-SD-LABEL: combine_i64_sdiv_const7:1695; CHECK-SD: // %bb.0:1696; CHECK-SD-NEXT: mov x8, #18725 // =0x49251697; CHECK-SD-NEXT: movk x8, #9362, lsl #161698; CHECK-SD-NEXT: movk x8, #37449, lsl #321699; CHECK-SD-NEXT: movk x8, #18724, lsl #481700; CHECK-SD-NEXT: smulh x8, x0, x81701; CHECK-SD-NEXT: asr x9, x8, #11702; CHECK-SD-NEXT: add x0, x9, x8, lsr #631703; CHECK-SD-NEXT: ret1704;1705; CHECK-GI-LABEL: combine_i64_sdiv_const7:1706; CHECK-GI: // %bb.0:1707; CHECK-GI-NEXT: mov x8, #18725 // =0x49251708; CHECK-GI-NEXT: movk x8, #9362, lsl #161709; CHECK-GI-NEXT: movk x8, #37449, lsl #321710; CHECK-GI-NEXT: movk x8, #18724, lsl #481711; CHECK-GI-NEXT: smulh x8, x0, x81712; CHECK-GI-NEXT: asr x8, x8, #11713; CHECK-GI-NEXT: add x0, x8, x8, lsr #631714; CHECK-GI-NEXT: ret1715 %1 = sdiv i64 %x, 71716 ret i64 %11717}1718 1719define i64 @combine_i64_sdiv_const100(i64 %x) {1720; CHECK-SD-LABEL: combine_i64_sdiv_const100:1721; CHECK-SD: // %bb.0:1722; CHECK-SD-NEXT: mov x8, #55051 // =0xd70b1723; CHECK-SD-NEXT: movk x8, #28835, lsl #161724; CHECK-SD-NEXT: movk x8, #2621, lsl #321725; CHECK-SD-NEXT: movk x8, #41943, lsl #481726; CHECK-SD-NEXT: smulh x8, x0, x81727; CHECK-SD-NEXT: add x8, x8, x01728; CHECK-SD-NEXT: asr x9, x8, #61729; CHECK-SD-NEXT: add x0, x9, x8, lsr #631730; CHECK-SD-NEXT: ret1731;1732; CHECK-GI-LABEL: combine_i64_sdiv_const100:1733; CHECK-GI: // %bb.0:1734; CHECK-GI-NEXT: mov x8, #55051 // =0xd70b1735; CHECK-GI-NEXT: movk x8, #28835, lsl #161736; CHECK-GI-NEXT: movk x8, #2621, lsl #321737; CHECK-GI-NEXT: movk x8, #41943, lsl #481738; CHECK-GI-NEXT: smulh x8, x0, x81739; CHECK-GI-NEXT: add x8, x8, x01740; CHECK-GI-NEXT: asr x8, x8, #61741; CHECK-GI-NEXT: add x0, x8, x8, lsr #631742; CHECK-GI-NEXT: ret1743 %1 = sdiv i64 %x, 1001744 ret i64 %11745}1746 1747define i128 @combine_i128_sdiv_const7(i128 %x) {1748; CHECK-LABEL: combine_i128_sdiv_const7:1749; CHECK: // %bb.0:1750; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1751; CHECK-NEXT: .cfi_def_cfa_offset 161752; CHECK-NEXT: .cfi_offset w30, -161753; CHECK-NEXT: mov w2, #7 // =0x71754; CHECK-NEXT: mov x3, xzr1755; CHECK-NEXT: bl __divti31756; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1757; CHECK-NEXT: ret1758 %1 = sdiv i128 %x, 71759 ret i128 %11760}1761 1762define i128 @combine_i128_sdiv_const100(i128 %x) {1763; CHECK-LABEL: combine_i128_sdiv_const100:1764; CHECK: // %bb.0:1765; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1766; CHECK-NEXT: .cfi_def_cfa_offset 161767; CHECK-NEXT: .cfi_offset w30, -161768; CHECK-NEXT: mov w2, #100 // =0x641769; CHECK-NEXT: mov x3, xzr1770; CHECK-NEXT: bl __divti31771; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1772; CHECK-NEXT: ret1773 %1 = sdiv i128 %x, 1001774 ret i128 %11775}1776 1777; The following only becomes an sdiv_by_one after type legalisation, after which1778; the splatted scalar constant has a different type to the splat vector. This1779; test verifies DAGCombiner does not care about this type difference.1780define <16 x i16> @combine_vec_sdiv_by_one_obfuscated(<16 x i16> %x) "target-features"="+sve" {1781; CHECK-SD-LABEL: combine_vec_sdiv_by_one_obfuscated:1782; CHECK-SD: // %bb.0:1783; CHECK-SD-NEXT: ret1784;1785; CHECK-GI-LABEL: combine_vec_sdiv_by_one_obfuscated:1786; CHECK-GI: // %bb.0:1787; CHECK-GI-NEXT: movi v2.2d, #00000000000000001788; CHECK-GI-NEXT: movi v3.8h, #11789; CHECK-GI-NEXT: smov w8, v0.h[0]1790; CHECK-GI-NEXT: mov v3.h[0], v2.h[0]1791; CHECK-GI-NEXT: smov w9, v3.h[0]1792; CHECK-GI-NEXT: smov w16, v3.h[7]1793; CHECK-GI-NEXT: sdiv w14, w8, w91794; CHECK-GI-NEXT: smov w8, v0.h[1]1795; CHECK-GI-NEXT: smov w9, v3.h[1]1796; CHECK-GI-NEXT: sdiv w15, w8, w91797; CHECK-GI-NEXT: smov w8, v0.h[2]1798; CHECK-GI-NEXT: smov w9, v3.h[2]1799; CHECK-GI-NEXT: sdiv w13, w8, w91800; CHECK-GI-NEXT: smov w8, v0.h[3]1801; CHECK-GI-NEXT: smov w9, v3.h[3]1802; CHECK-GI-NEXT: sdiv w12, w8, w91803; CHECK-GI-NEXT: smov w8, v0.h[4]1804; CHECK-GI-NEXT: smov w9, v3.h[4]1805; CHECK-GI-NEXT: sdiv w11, w8, w91806; CHECK-GI-NEXT: smov w8, v0.h[5]1807; CHECK-GI-NEXT: smov w9, v3.h[5]1808; CHECK-GI-NEXT: sdiv w10, w8, w91809; CHECK-GI-NEXT: smov w8, v0.h[6]1810; CHECK-GI-NEXT: smov w9, v3.h[6]1811; CHECK-GI-NEXT: movi v3.8h, #11812; CHECK-GI-NEXT: smov w17, v3.h[0]1813; CHECK-GI-NEXT: smov w18, v3.h[1]1814; CHECK-GI-NEXT: smov w0, v3.h[2]1815; CHECK-GI-NEXT: smov w1, v3.h[3]1816; CHECK-GI-NEXT: smov w2, v3.h[4]1817; CHECK-GI-NEXT: smov w3, v3.h[5]1818; CHECK-GI-NEXT: sdiv w8, w8, w91819; CHECK-GI-NEXT: smov w9, v0.h[7]1820; CHECK-GI-NEXT: fmov s0, w141821; CHECK-GI-NEXT: mov v0.h[1], w151822; CHECK-GI-NEXT: smov w15, v1.h[6]1823; CHECK-GI-NEXT: mov v0.h[2], w131824; CHECK-GI-NEXT: sdiv w9, w9, w161825; CHECK-GI-NEXT: smov w16, v1.h[0]1826; CHECK-GI-NEXT: mov v0.h[3], w121827; CHECK-GI-NEXT: smov w12, v1.h[7]1828; CHECK-GI-NEXT: mov v0.h[4], w111829; CHECK-GI-NEXT: sdiv w16, w16, w171830; CHECK-GI-NEXT: smov w17, v1.h[1]1831; CHECK-GI-NEXT: mov v0.h[5], w101832; CHECK-GI-NEXT: mov v0.h[6], w81833; CHECK-GI-NEXT: sdiv w17, w17, w181834; CHECK-GI-NEXT: smov w18, v1.h[2]1835; CHECK-GI-NEXT: fmov s2, w161836; CHECK-GI-NEXT: smov w16, v3.h[6]1837; CHECK-GI-NEXT: mov v0.h[7], w91838; CHECK-GI-NEXT: sdiv w18, w18, w01839; CHECK-GI-NEXT: smov w0, v1.h[3]1840; CHECK-GI-NEXT: mov v2.h[1], w171841; CHECK-GI-NEXT: sdiv w0, w0, w11842; CHECK-GI-NEXT: smov w1, v1.h[4]1843; CHECK-GI-NEXT: mov v2.h[2], w181844; CHECK-GI-NEXT: sdiv w1, w1, w21845; CHECK-GI-NEXT: smov w2, v1.h[5]1846; CHECK-GI-NEXT: mov v2.h[3], w01847; CHECK-GI-NEXT: sdiv w14, w2, w31848; CHECK-GI-NEXT: mov v2.h[4], w11849; CHECK-GI-NEXT: sdiv w13, w15, w161850; CHECK-GI-NEXT: smov w15, v3.h[7]1851; CHECK-GI-NEXT: mov v2.h[5], w141852; CHECK-GI-NEXT: sdiv w10, w12, w151853; CHECK-GI-NEXT: mov v2.h[6], w131854; CHECK-GI-NEXT: mov v2.h[7], w101855; CHECK-GI-NEXT: mov v1.16b, v2.16b1856; CHECK-GI-NEXT: ret1857 %zero_and_ones = shufflevector <16 x i16> zeroinitializer, <16 x i16> splat (i16 1), <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1858 %div = sdiv <16 x i16> %x, %zero_and_ones1859 ret <16 x i16> %div1860}1861