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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s3 4target triple = "aarch64"5 6; Expected to transform7define <vscale x 4 x i32> @complex_mul_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {8; CHECK-LABEL: complex_mul_v4i32:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: movi v2.2d, #000000000000000011; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #012; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #9013; CHECK-NEXT: mov z0.d, z2.d14; CHECK-NEXT: ret15entry:16 %a.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %a)17 %a.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 018 %a.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 119 %b.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %b)20 %b.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 021 %b.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 122 %0 = mul <vscale x 2 x i32> %b.imag, %a.real23 %1 = mul <vscale x 2 x i32> %b.real, %a.imag24 %2 = add <vscale x 2 x i32> %1, %025 %3 = mul <vscale x 2 x i32> %b.real, %a.real26 %4 = mul <vscale x 2 x i32> %a.imag, %b.imag27 %5 = sub <vscale x 2 x i32> %3, %428 %interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %5, <vscale x 2 x i32> %2)29 ret <vscale x 4 x i32> %interleaved.vec30}31 32; Expected to transform33define <vscale x 8 x i32> @complex_mul_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {34; CHECK-LABEL: complex_mul_v8i32:35; CHECK: // %bb.0: // %entry36; CHECK-NEXT: movi v4.2d, #000000000000000037; CHECK-NEXT: movi v5.2d, #000000000000000038; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #039; CHECK-NEXT: cmla z4.s, z3.s, z1.s, #040; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #9041; CHECK-NEXT: cmla z4.s, z3.s, z1.s, #9042; CHECK-NEXT: mov z0.d, z5.d43; CHECK-NEXT: mov z1.d, z4.d44; CHECK-NEXT: ret45entry:46 %a.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %a)47 %a.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 048 %a.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 149 %b.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %b)50 %b.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 051 %b.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 152 %0 = mul <vscale x 4 x i32> %b.imag, %a.real53 %1 = mul <vscale x 4 x i32> %b.real, %a.imag54 %2 = add <vscale x 4 x i32> %1, %055 %3 = mul <vscale x 4 x i32> %b.real, %a.real56 %4 = mul <vscale x 4 x i32> %a.imag, %b.imag57 %5 = sub <vscale x 4 x i32> %3, %458 %interleaved.vec = tail call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %2)59 ret <vscale x 8 x i32> %interleaved.vec60}61 62; Expected to transform63define <vscale x 16 x i32> @complex_mul_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {64; CHECK-LABEL: complex_mul_v16i32:65; CHECK: // %bb.0: // %entry66; CHECK-NEXT: movi v24.2d, #000000000000000067; CHECK-NEXT: movi v25.2d, #000000000000000068; CHECK-NEXT: movi v26.2d, #000000000000000069; CHECK-NEXT: movi v27.2d, #000000000000000070; CHECK-NEXT: cmla z24.s, z4.s, z0.s, #071; CHECK-NEXT: cmla z25.s, z5.s, z1.s, #072; CHECK-NEXT: cmla z27.s, z6.s, z2.s, #073; CHECK-NEXT: cmla z26.s, z7.s, z3.s, #074; CHECK-NEXT: cmla z24.s, z4.s, z0.s, #9075; CHECK-NEXT: cmla z25.s, z5.s, z1.s, #9076; CHECK-NEXT: cmla z27.s, z6.s, z2.s, #9077; CHECK-NEXT: cmla z26.s, z7.s, z3.s, #9078; CHECK-NEXT: mov z0.d, z24.d79; CHECK-NEXT: mov z1.d, z25.d80; CHECK-NEXT: mov z2.d, z27.d81; CHECK-NEXT: mov z3.d, z26.d82; CHECK-NEXT: ret83entry:84 %a.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %a)85 %a.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 086 %a.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 187 %b.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %b)88 %b.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 089 %b.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 190 %0 = mul <vscale x 8 x i32> %b.imag, %a.real91 %1 = mul <vscale x 8 x i32> %b.real, %a.imag92 %2 = add <vscale x 8 x i32> %1, %093 %3 = mul <vscale x 8 x i32> %b.real, %a.real94 %4 = mul <vscale x 8 x i32> %a.imag, %b.imag95 %5 = sub <vscale x 8 x i32> %3, %496 %interleaved.vec = tail call <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32> %5, <vscale x 8 x i32> %2)97 ret <vscale x 16 x i32> %interleaved.vec98}99 100declare { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>)101declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)102 103declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)104declare <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)105 106declare { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32>)107declare <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>)108 109