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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s3 4target triple = "aarch64"5 6; Expected to transform7define <vscale x 2 x i64> @complex_add_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {8; CHECK-LABEL: complex_add_v2i64:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: cadd z1.d, z1.d, z0.d, #9011; CHECK-NEXT: mov z0.d, z1.d12; CHECK-NEXT: ret13entry:14 %a.deinterleaved = tail call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64> %a)15 %a.real = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %a.deinterleaved, 016 %a.imag = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %a.deinterleaved, 117 %b.deinterleaved = tail call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64> %b)18 %b.real = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %b.deinterleaved, 019 %b.imag = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %b.deinterleaved, 120 %0 = sub <vscale x 1 x i64> %b.real, %a.imag21 %1 = add <vscale x 1 x i64> %b.imag, %a.real22 %interleaved.vec = tail call <vscale x 2 x i64> @llvm.vector.interleave2.nxv2i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1)23 ret <vscale x 2 x i64> %interleaved.vec24}25 26; Expected to transform27define <vscale x 4 x i64> @complex_add_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {28; CHECK-LABEL: complex_add_v4i64:29; CHECK: // %bb.0: // %entry30; CHECK-NEXT: cadd z3.d, z3.d, z1.d, #9031; CHECK-NEXT: cadd z2.d, z2.d, z0.d, #9032; CHECK-NEXT: mov z0.d, z2.d33; CHECK-NEXT: mov z1.d, z3.d34; CHECK-NEXT: ret35entry:36 %a.deinterleaved = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %a)37 %a.real = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %a.deinterleaved, 038 %a.imag = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %a.deinterleaved, 139 %b.deinterleaved = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %b)40 %b.real = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %b.deinterleaved, 041 %b.imag = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %b.deinterleaved, 142 %0 = sub <vscale x 2 x i64> %b.real, %a.imag43 %1 = add <vscale x 2 x i64> %b.imag, %a.real44 %interleaved.vec = tail call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)45 ret <vscale x 4 x i64> %interleaved.vec46}47 48; Expected to transform49define <vscale x 8 x i64> @complex_add_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {50; CHECK-LABEL: complex_add_v8i64:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: cadd z6.d, z6.d, z2.d, #9053; CHECK-NEXT: cadd z4.d, z4.d, z0.d, #9054; CHECK-NEXT: cadd z5.d, z5.d, z1.d, #9055; CHECK-NEXT: cadd z7.d, z7.d, z3.d, #9056; CHECK-NEXT: mov z0.d, z4.d57; CHECK-NEXT: mov z1.d, z5.d58; CHECK-NEXT: mov z2.d, z6.d59; CHECK-NEXT: mov z3.d, z7.d60; CHECK-NEXT: ret61entry:62 %a.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %a)63 %a.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 064 %a.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 165 %b.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %b)66 %b.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 067 %b.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 168 %0 = sub <vscale x 4 x i64> %b.real, %a.imag69 %1 = add <vscale x 4 x i64> %b.imag, %a.real70 %interleaved.vec = tail call <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1)71 ret <vscale x 8 x i64> %interleaved.vec72}73 74declare { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64>)75declare <vscale x 2 x i64> @llvm.vector.interleave2.nxv2i64(<vscale x 1 x i64>, <vscale x 1 x i64>)76 77declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)78declare <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)79 80declare { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64>)81declare <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64>, <vscale x 4 x i64>)82