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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s3 4target triple = "aarch64"5 6; Expected to not transform as the type's minimum size is less than 128 bits.7define <vscale x 8 x i8> @complex_add_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {8; CHECK-LABEL: complex_add_v8i8:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: uunpkhi z2.s, z0.h11; CHECK-NEXT: uunpklo z0.s, z0.h12; CHECK-NEXT: uunpkhi z3.s, z1.h13; CHECK-NEXT: uunpklo z1.s, z1.h14; CHECK-NEXT: uzp1 z4.s, z0.s, z2.s15; CHECK-NEXT: uzp2 z0.s, z0.s, z2.s16; CHECK-NEXT: uzp2 z2.s, z1.s, z3.s17; CHECK-NEXT: uzp1 z1.s, z1.s, z3.s18; CHECK-NEXT: sub z0.s, z1.s, z0.s19; CHECK-NEXT: add z1.s, z2.s, z4.s20; CHECK-NEXT: zip2 z2.s, z0.s, z1.s21; CHECK-NEXT: zip1 z0.s, z0.s, z1.s22; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h23; CHECK-NEXT: ret24entry:25 %a.deinterleaved = tail call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> %a)26 %a.real = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %a.deinterleaved, 027 %a.imag = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %a.deinterleaved, 128 %b.deinterleaved = tail call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> %b)29 %b.real = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %b.deinterleaved, 030 %b.imag = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %b.deinterleaved, 131 %0 = sub <vscale x 4 x i8> %b.real, %a.imag32 %1 = add <vscale x 4 x i8> %b.imag, %a.real33 %interleaved.vec = tail call <vscale x 8 x i8> @llvm.vector.interleave2.nxv8i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1)34 ret <vscale x 8 x i8> %interleaved.vec35}36 37; Expected to transform38define <vscale x 16 x i8> @complex_add_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {39; CHECK-LABEL: complex_add_v16i8:40; CHECK: // %bb.0: // %entry41; CHECK-NEXT: cadd z1.b, z1.b, z0.b, #9042; CHECK-NEXT: mov z0.d, z1.d43; CHECK-NEXT: ret44entry:45 %a.deinterleaved = tail call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %a)46 %a.real = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %a.deinterleaved, 047 %a.imag = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %a.deinterleaved, 148 %b.deinterleaved = tail call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %b)49 %b.real = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %b.deinterleaved, 050 %b.imag = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %b.deinterleaved, 151 %0 = sub <vscale x 8 x i8> %b.real, %a.imag52 %1 = add <vscale x 8 x i8> %b.imag, %a.real53 %interleaved.vec = tail call <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1)54 ret <vscale x 16 x i8> %interleaved.vec55}56 57; Expected to transform58define <vscale x 32 x i8> @complex_add_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {59; CHECK-LABEL: complex_add_v32i8:60; CHECK: // %bb.0: // %entry61; CHECK-NEXT: cadd z3.b, z3.b, z1.b, #9062; CHECK-NEXT: cadd z2.b, z2.b, z0.b, #9063; CHECK-NEXT: mov z0.d, z2.d64; CHECK-NEXT: mov z1.d, z3.d65; CHECK-NEXT: ret66entry:67 %a.deinterleaved = tail call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %a)68 %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 069 %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 170 %b.deinterleaved = tail call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %b)71 %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 072 %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 173 %0 = sub <vscale x 16 x i8> %b.real, %a.imag74 %1 = add <vscale x 16 x i8> %b.imag, %a.real75 %interleaved.vec = tail call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)76 ret <vscale x 32 x i8> %interleaved.vec77}78 79declare { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8>)80declare <vscale x 8 x i8> @llvm.vector.interleave2.nxv8i8(<vscale x 4 x i8>, <vscale x 4 x i8>)81 82declare { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8>)83declare <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8>, <vscale x 8 x i8>)84 85declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)86declare <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8>, <vscale x 16 x i8>)87