316 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s3 4target triple = "aarch64"5 6; Expected to transform7define <4 x float> @simple_mul(<4 x float> %a, <4 x float> %b) {8; CHECK-LABEL: simple_mul:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: movi v2.2d, #000000000000000011; CHECK-NEXT: fcmla v2.4s, v1.4s, v0.4s, #012; CHECK-NEXT: fcmla v2.4s, v1.4s, v0.4s, #9013; CHECK-NEXT: mov v0.16b, v2.16b14; CHECK-NEXT: ret15entry:16 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>17 %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>18 %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>19 %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>20 %0 = fmul fast <2 x float> %strided.vec20, %strided.vec21 %1 = fmul fast <2 x float> %strided.vec19, %strided.vec1722 %2 = fadd fast <2 x float> %1, %023 %3 = fmul fast <2 x float> %strided.vec19, %strided.vec24 %4 = fmul fast <2 x float> %strided.vec17, %strided.vec2025 %5 = fsub fast <2 x float> %3, %426 %interleaved.vec = shufflevector <2 x float> %5, <2 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>27 ret <4 x float> %interleaved.vec28}29 30; Expected to not transform31define <4 x float> @simple_mul_no_contract(<4 x float> %a, <4 x float> %b) {32; CHECK-LABEL: simple_mul_no_contract:33; CHECK: // %bb.0: // %entry34; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #835; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #836; CHECK-NEXT: zip1 v4.2s, v0.2s, v2.2s37; CHECK-NEXT: zip2 v0.2s, v0.2s, v2.2s38; CHECK-NEXT: zip1 v2.2s, v1.2s, v3.2s39; CHECK-NEXT: zip2 v1.2s, v1.2s, v3.2s40; CHECK-NEXT: fmul v3.2s, v1.2s, v4.2s41; CHECK-NEXT: fmul v4.2s, v2.2s, v4.2s42; CHECK-NEXT: fmul v1.2s, v0.2s, v1.2s43; CHECK-NEXT: fmla v3.2s, v0.2s, v2.2s44; CHECK-NEXT: fsub v0.2s, v4.2s, v1.2s45; CHECK-NEXT: zip1 v0.4s, v0.4s, v3.4s46; CHECK-NEXT: ret47entry:48 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>49 %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>50 %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>51 %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>52 %0 = fmul fast <2 x float> %strided.vec20, %strided.vec53 %1 = fmul fast <2 x float> %strided.vec19, %strided.vec1754 %2 = fadd fast <2 x float> %1, %055 %3 = fmul fast <2 x float> %strided.vec19, %strided.vec56 %4 = fmul fast <2 x float> %strided.vec17, %strided.vec2057 %5 = fsub <2 x float> %3, %458 %interleaved.vec = shufflevector <2 x float> %5, <2 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>59 ret <4 x float> %interleaved.vec60}61 62; Expected to transform63define <4 x float> @three_way_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {64; CHECK-LABEL: three_way_mul:65; CHECK: // %bb.0: // %entry66; CHECK-NEXT: movi v4.2d, #000000000000000067; CHECK-NEXT: movi v3.2d, #000000000000000068; CHECK-NEXT: fcmla v4.4s, v0.4s, v1.4s, #069; CHECK-NEXT: fcmla v4.4s, v0.4s, v1.4s, #9070; CHECK-NEXT: fcmla v3.4s, v4.4s, v2.4s, #071; CHECK-NEXT: fcmla v3.4s, v4.4s, v2.4s, #9072; CHECK-NEXT: mov v0.16b, v3.16b73; CHECK-NEXT: ret74entry:75 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>76 %strided.vec39 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>77 %strided.vec41 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>78 %strided.vec42 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>79 %strided.vec44 = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 0, i32 2>80 %strided.vec45 = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 1, i32 3>81 %0 = fmul fast <2 x float> %strided.vec41, %strided.vec82 %1 = fmul fast <2 x float> %strided.vec42, %strided.vec3983 %2 = fsub fast <2 x float> %0, %184 %3 = fmul fast <2 x float> %2, %strided.vec4585 %4 = fmul fast <2 x float> %strided.vec42, %strided.vec86 %5 = fmul fast <2 x float> %strided.vec39, %strided.vec4187 %6 = fadd fast <2 x float> %4, %588 %7 = fmul fast <2 x float> %6, %strided.vec4489 %8 = fadd fast <2 x float> %3, %790 %9 = fmul fast <2 x float> %2, %strided.vec4491 %10 = fmul fast <2 x float> %6, %strided.vec4592 %11 = fsub fast <2 x float> %9, %1093 %interleaved.vec = shufflevector <2 x float> %11, <2 x float> %8, <4 x i32> <i32 0, i32 2, i32 1, i32 3>94 ret <4 x float> %interleaved.vec95}96 97; Expected to transform98define <4 x float> @simple_add_90(<4 x float> %a, <4 x float> %b) {99; CHECK-LABEL: simple_add_90:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: fcadd v0.4s, v1.4s, v0.4s, #90102; CHECK-NEXT: ret103entry:104 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>105 %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>106 %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>107 %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>108 %0 = fsub fast <2 x float> %strided.vec19, %strided.vec17109 %1 = fadd fast <2 x float> %strided.vec20, %strided.vec110 %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>111 ret <4 x float> %interleaved.vec112}113 114; Expected to not transform, fadd commutativity is not yet implemented115define <4 x float> @simple_add_270_false(<4 x float> %a, <4 x float> %b) {116; CHECK-LABEL: simple_add_270_false:117; CHECK: // %bb.0: // %entry118; CHECK-NEXT: fcadd v0.4s, v0.4s, v1.4s, #270119; CHECK-NEXT: ret120entry:121 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>122 %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>123 %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>124 %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>125 %0 = fadd fast <2 x float> %strided.vec20, %strided.vec126 %1 = fsub fast <2 x float> %strided.vec17, %strided.vec19127 %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>128 ret <4 x float> %interleaved.vec129}130 131; Expected to transform132define <4 x float> @simple_add_270_true(<4 x float> %a, <4 x float> %b) {133; CHECK-LABEL: simple_add_270_true:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: fcadd v0.4s, v0.4s, v1.4s, #270136; CHECK-NEXT: ret137entry:138 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>139 %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>140 %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>141 %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>142 %0 = fadd fast <2 x float> %strided.vec, %strided.vec20143 %1 = fsub fast <2 x float> %strided.vec17, %strided.vec19144 %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>145 ret <4 x float> %interleaved.vec146}147 148; Expected to not transform149define <4 x float> @add_external_use(<4 x float> %a, <4 x float> %b) {150; CHECK-LABEL: add_external_use:151; CHECK: // %bb.0: // %entry152; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8153; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8154; CHECK-NEXT: zip1 v4.2s, v0.2s, v2.2s155; CHECK-NEXT: zip2 v0.2s, v0.2s, v2.2s156; CHECK-NEXT: zip1 v2.2s, v1.2s, v3.2s157; CHECK-NEXT: zip2 v1.2s, v1.2s, v3.2s158; CHECK-NEXT: fadd v0.2s, v0.2s, v2.2s159; CHECK-NEXT: fsub v1.2s, v4.2s, v1.2s160; CHECK-NEXT: zip1 v0.4s, v1.4s, v0.4s161; CHECK-NEXT: ret162entry:163 %a.real = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>164 %a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>165 %b.real = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>166 %b.imag = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>167 %0 = fsub fast <2 x float> %a.real, %b.imag168 %1 = fadd fast <2 x float> %a.imag, %b.real169 %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>170 %dup = shufflevector <2 x float> %0, <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>171 %interleaved.vec2 = shufflevector <4 x float> %interleaved.vec, <4 x float> %dup, <4 x i32> <i32 0, i32 1, i32 2, i32 3>172 ret <4 x float> %interleaved.vec2173}174 175; Expected to transform176define <4 x float> @mul_mul_with_fneg(<4 x float> %a, <4 x float> %b) {177; CHECK-LABEL: mul_mul_with_fneg:178; CHECK: // %bb.0: // %entry179; CHECK-NEXT: movi v2.2d, #0000000000000000180; CHECK-NEXT: fcmla v2.4s, v0.4s, v1.4s, #270181; CHECK-NEXT: fcmla v2.4s, v0.4s, v1.4s, #180182; CHECK-NEXT: mov v0.16b, v2.16b183; CHECK-NEXT: ret184entry:185 %a.real = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>186 %a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>187 %b.real = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>188 %b.imag = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>189 %0 = fneg fast <2 x float> %a.imag190 %1 = fmul fast <2 x float> %b.real, %0191 %2 = fmul fast <2 x float> %a.real, %b.imag192 %3 = fsub fast <2 x float> %1, %2193 %4 = fmul fast <2 x float> %b.imag, %a.imag194 %5 = fmul fast <2 x float> %a.real, %b.real195 %6 = fsub fast <2 x float> %4, %5196 %interleaved.vec = shufflevector <2 x float> %6, <2 x float> %3, <4 x i32> <i32 0, i32 2, i32 1, i32 3>197 ret <4 x float> %interleaved.vec198}199 200; Expected to not transform201define <12 x float> @abp90c12(<12 x float> %a, <12 x float> %b, <12 x float> %c) {202; CHECK-LABEL: abp90c12:203; CHECK: // %bb.0: // %entry204; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1205; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3206; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0207; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2208; CHECK-NEXT: ldr s17, [sp, #32]209; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5210; CHECK-NEXT: add x9, sp, #48211; CHECK-NEXT: add x10, sp, #64212; CHECK-NEXT: mov v1.s[1], v3.s[0]213; CHECK-NEXT: mov v0.s[1], v2.s[0]214; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4215; CHECK-NEXT: add x11, sp, #72216; CHECK-NEXT: ld1 { v17.s }[1], [x9]217; CHECK-NEXT: ldr s18, [x10]218; CHECK-NEXT: add x9, sp, #80219; CHECK-NEXT: add x10, sp, #56220; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6221; CHECK-NEXT: // kill: def $s7 killed $s7 def $q7222; CHECK-NEXT: ldr s16, [sp, #8]223; CHECK-NEXT: ldr s3, [sp, #96]224; CHECK-NEXT: ld1 { v18.s }[1], [x9]225; CHECK-NEXT: add x9, sp, #88226; CHECK-NEXT: ldr s2, [sp]227; CHECK-NEXT: mov v1.s[2], v5.s[0]228; CHECK-NEXT: ldr s5, [sp, #40]229; CHECK-NEXT: mov v0.s[2], v4.s[0]230; CHECK-NEXT: ld1 { v5.s }[1], [x10]231; CHECK-NEXT: ldr s19, [x11]232; CHECK-NEXT: add x10, sp, #144233; CHECK-NEXT: zip1 v4.2d, v17.2d, v18.2d234; CHECK-NEXT: add x11, sp, #160235; CHECK-NEXT: ldr s18, [sp, #136]236; CHECK-NEXT: ld1 { v19.s }[1], [x9]237; CHECK-NEXT: mov v0.s[3], v6.s[0]238; CHECK-NEXT: ldr s6, [sp, #128]239; CHECK-NEXT: mov v1.s[3], v7.s[0]240; CHECK-NEXT: add x9, sp, #24241; CHECK-NEXT: ldr s7, [sp, #104]242; CHECK-NEXT: ld1 { v16.s }[1], [x9]243; CHECK-NEXT: add x9, sp, #112244; CHECK-NEXT: ld1 { v6.s }[1], [x10]245; CHECK-NEXT: zip1 v5.2d, v5.2d, v19.2d246; CHECK-NEXT: add x10, sp, #120247; CHECK-NEXT: ld1 { v3.s }[1], [x9]248; CHECK-NEXT: ld1 { v7.s }[1], [x10]249; CHECK-NEXT: ldr s17, [x11]250; CHECK-NEXT: add x9, sp, #176251; CHECK-NEXT: add x10, sp, #16252; CHECK-NEXT: add x11, sp, #168253; CHECK-NEXT: ld1 { v17.s }[1], [x9]254; CHECK-NEXT: ld1 { v2.s }[1], [x10]255; CHECK-NEXT: add x9, sp, #152256; CHECK-NEXT: fmul v19.4s, v5.4s, v1.4s257; CHECK-NEXT: fmul v20.4s, v7.4s, v16.4s258; CHECK-NEXT: fmul v16.4s, v3.4s, v16.4s259; CHECK-NEXT: fmul v1.4s, v4.4s, v1.4s260; CHECK-NEXT: ld1 { v18.s }[1], [x9]261; CHECK-NEXT: ldr s21, [x11]262; CHECK-NEXT: zip1 v6.2d, v6.2d, v17.2d263; CHECK-NEXT: ldr s17, [sp, #192]264; CHECK-NEXT: add x9, sp, #184265; CHECK-NEXT: add x10, sp, #208266; CHECK-NEXT: ld1 { v21.s }[1], [x9]267; CHECK-NEXT: add x9, sp, #216268; CHECK-NEXT: fneg v19.4s, v19.4s269; CHECK-NEXT: fneg v20.4s, v20.4s270; CHECK-NEXT: fmla v16.4s, v2.4s, v7.4s271; CHECK-NEXT: fmla v1.4s, v0.4s, v5.4s272; CHECK-NEXT: ld1 { v17.s }[1], [x10]273; CHECK-NEXT: ldr s5, [sp, #200]274; CHECK-NEXT: zip1 v7.2d, v18.2d, v21.2d275; CHECK-NEXT: ld1 { v5.s }[1], [x9]276; CHECK-NEXT: fmla v19.4s, v0.4s, v4.4s277; CHECK-NEXT: fmla v20.4s, v2.4s, v3.4s278; CHECK-NEXT: fsub v0.4s, v6.4s, v1.4s279; CHECK-NEXT: fsub v1.4s, v17.4s, v16.4s280; CHECK-NEXT: fadd v2.4s, v7.4s, v19.4s281; CHECK-NEXT: fadd v3.4s, v5.4s, v20.4s282; CHECK-NEXT: ext v4.16b, v0.16b, v1.16b, #12283; CHECK-NEXT: ext v5.16b, v2.16b, v3.16b, #12284; CHECK-NEXT: trn2 v1.4s, v1.4s, v3.4s285; CHECK-NEXT: ext v4.16b, v0.16b, v4.16b, #12286; CHECK-NEXT: ext v5.16b, v2.16b, v5.16b, #8287; CHECK-NEXT: rev64 v4.4s, v4.4s288; CHECK-NEXT: trn2 v3.4s, v4.4s, v5.4s289; CHECK-NEXT: zip2 v4.4s, v0.4s, v2.4s290; CHECK-NEXT: zip1 v0.4s, v0.4s, v2.4s291; CHECK-NEXT: ext v1.16b, v3.16b, v1.16b, #8292; CHECK-NEXT: mov v4.d[1], v3.d[0]293; CHECK-NEXT: str q0, [x8]294; CHECK-NEXT: stp q4, q1, [x8, #16]295; CHECK-NEXT: ret296entry:297 %ar = shufflevector <12 x float> %a, <12 x float> poison, <6 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10>298 %ai = shufflevector <12 x float> %a, <12 x float> poison, <6 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>299 %br = shufflevector <12 x float> %b, <12 x float> poison, <6 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10>300 %bi = shufflevector <12 x float> %b, <12 x float> poison, <6 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>301 %cr = shufflevector <12 x float> %c, <12 x float> poison, <6 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10>302 %ci = shufflevector <12 x float> %c, <12 x float> poison, <6 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>303 304 %i6 = fmul fast <6 x float> %br, %ar305 %i7 = fmul fast <6 x float> %bi, %ai306 %xr = fsub fast <6 x float> %i6, %i7307 %i9 = fmul fast <6 x float> %bi, %ar308 %i10 = fmul fast <6 x float> %br, %ai309 %xi = fadd fast <6 x float> %i9, %i10310 311 %zr = fsub fast <6 x float> %cr, %xi312 %zi = fadd fast <6 x float> %ci, %xr313 %interleaved.vec = shufflevector <6 x float> %zr, <6 x float> %zi, <12 x i32> <i32 0, i32 6, i32 1, i32 7, i32 2, i32 8, i32 3, i32 9, i32 4, i32 10, i32 5, i32 11>314 ret <12 x float> %interleaved.vec315}316