151 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 < %s | FileCheck %s3 4define i16 @combine_add_16xi16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) {5; CHECK-LABEL: combine_add_16xi16:6; CHECK: // %bb.0:7; CHECK-NEXT: fmov s0, w08; CHECK-NEXT: ldr h1, [sp]9; CHECK-NEXT: add x8, sp, #810; CHECK-NEXT: ld1 { v1.h }[1], [x8]11; CHECK-NEXT: add x8, sp, #1612; CHECK-NEXT: mov v0.h[1], w113; CHECK-NEXT: ld1 { v1.h }[2], [x8]14; CHECK-NEXT: add x8, sp, #2415; CHECK-NEXT: mov v0.h[2], w216; CHECK-NEXT: ld1 { v1.h }[3], [x8]17; CHECK-NEXT: add x8, sp, #3218; CHECK-NEXT: mov v0.h[3], w319; CHECK-NEXT: ld1 { v1.h }[4], [x8]20; CHECK-NEXT: add x8, sp, #4021; CHECK-NEXT: ld1 { v1.h }[5], [x8]22; CHECK-NEXT: add x8, sp, #4823; CHECK-NEXT: mov v0.h[4], w424; CHECK-NEXT: ld1 { v1.h }[6], [x8]25; CHECK-NEXT: add x8, sp, #5626; CHECK-NEXT: mov v0.h[5], w527; CHECK-NEXT: ld1 { v1.h }[7], [x8]28; CHECK-NEXT: mov v0.h[6], w629; CHECK-NEXT: mov v0.h[7], w730; CHECK-NEXT: uzp2 v2.16b, v0.16b, v1.16b31; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b32; CHECK-NEXT: uhadd v0.16b, v0.16b, v2.16b33; CHECK-NEXT: uaddlv h0, v0.16b34; CHECK-NEXT: umov w0, v0.h[0]35; CHECK-NEXT: ret36 %a1 = insertelement <16 x i16> poison, i16 %a, i16 037 %b1 = insertelement <16 x i16> %a1, i16 %b, i16 138 %c1 = insertelement <16 x i16> %b1, i16 %c, i16 239 %d1 = insertelement <16 x i16> %c1, i16 %d, i16 340 %e1 = insertelement <16 x i16> %d1, i16 %e, i16 441 %f1 = insertelement <16 x i16> %e1, i16 %f, i16 542 %g1 = insertelement <16 x i16> %f1, i16 %g, i16 643 %h1 = insertelement <16 x i16> %g1, i16 %h, i16 744 %i1 = insertelement <16 x i16> %h1, i16 %i, i16 845 %j1 = insertelement <16 x i16> %i1, i16 %j, i16 946 %k1 = insertelement <16 x i16> %j1, i16 %k, i16 1047 %l1 = insertelement <16 x i16> %k1, i16 %l, i16 1148 %m1 = insertelement <16 x i16> %l1, i16 %m, i16 1249 %n1 = insertelement <16 x i16> %m1, i16 %n, i16 1350 %o1 = insertelement <16 x i16> %n1, i16 %o, i16 1451 %p1 = insertelement <16 x i16> %o1, i16 %p, i16 1552 %x = and <16 x i16> %p1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>53 %sh1 = lshr <16 x i16> %p1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>54 %s = add nuw nsw <16 x i16> %x, %sh155 %sh2 = lshr <16 x i16> %s, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>56 %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sh2)57 ret i16 %res58}59 60define i32 @combine_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) local_unnamed_addr #0 {61; CHECK-LABEL: combine_add_8xi32:62; CHECK: // %bb.0:63; CHECK-NEXT: fmov s0, w464; CHECK-NEXT: fmov s1, w065; CHECK-NEXT: mov v0.s[1], w566; CHECK-NEXT: mov v1.s[1], w167; CHECK-NEXT: mov v0.s[2], w668; CHECK-NEXT: mov v1.s[2], w269; CHECK-NEXT: mov v0.s[3], w770; CHECK-NEXT: mov v1.s[3], w371; CHECK-NEXT: uzp2 v2.8h, v1.8h, v0.8h72; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h73; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h74; CHECK-NEXT: uaddlv s0, v0.8h75; CHECK-NEXT: fmov w0, s076; CHECK-NEXT: ret77 %a1 = insertelement <8 x i32> poison, i32 %a, i32 078 %b1 = insertelement <8 x i32> %a1, i32 %b, i32 179 %c1 = insertelement <8 x i32> %b1, i32 %c, i32 280 %d1 = insertelement <8 x i32> %c1, i32 %d, i32 381 %e1 = insertelement <8 x i32> %d1, i32 %e, i32 482 %f1 = insertelement <8 x i32> %e1, i32 %f, i32 583 %g1 = insertelement <8 x i32> %f1, i32 %g, i32 684 %h1 = insertelement <8 x i32> %g1, i32 %h, i32 785 %x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>86 %sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>87 %s = add nuw nsw <8 x i32> %x, %sh188 %sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>89 %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)90 ret i32 %res91}92 93define i32 @combine_undef_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {94; CHECK-LABEL: combine_undef_add_8xi32:95; CHECK: // %bb.0:96; CHECK-NEXT: fmov s1, w097; CHECK-NEXT: dup v0.4s, w898; CHECK-NEXT: mov v1.s[1], w199; CHECK-NEXT: mov v1.s[2], w2100; CHECK-NEXT: mov v1.s[3], w3101; CHECK-NEXT: uzp2 v2.8h, v1.8h, v0.8h102; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h103; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h104; CHECK-NEXT: uaddlv s0, v0.8h105; CHECK-NEXT: fmov w0, s0106; CHECK-NEXT: ret107 %a1 = insertelement <8 x i32> poison, i32 %a, i32 0108 %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1109 %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2110 %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3111 %e1 = insertelement <8 x i32> %d1, i32 undef, i32 4112 %f1 = insertelement <8 x i32> %e1, i32 undef, i32 5113 %g1 = insertelement <8 x i32> %f1, i32 undef, i32 6114 %h1 = insertelement <8 x i32> %g1, i32 undef, i32 7115 %x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>116 %sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>117 %s = add nuw nsw <8 x i32> %x, %sh1118 %sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>119 %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)120 ret i32 %res121}122 123define i64 @combine_add_4xi64(i64 %a, i64 %b, i64 %c, i64 %d) local_unnamed_addr #0 {124; CHECK-LABEL: combine_add_4xi64:125; CHECK: // %bb.0:126; CHECK-NEXT: fmov d0, x2127; CHECK-NEXT: fmov d1, x0128; CHECK-NEXT: mov v0.d[1], x3129; CHECK-NEXT: mov v1.d[1], x1130; CHECK-NEXT: uzp2 v2.4s, v1.4s, v0.4s131; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s132; CHECK-NEXT: uhadd v0.4s, v0.4s, v2.4s133; CHECK-NEXT: uaddlv d0, v0.4s134; CHECK-NEXT: fmov x0, d0135; CHECK-NEXT: ret136 %a1 = insertelement <4 x i64> poison, i64 %a, i64 0137 %b1 = insertelement <4 x i64> %a1, i64 %b, i64 1138 %c1 = insertelement <4 x i64> %b1, i64 %c, i64 2139 %d1 = insertelement <4 x i64> %c1, i64 %d, i64 3140 %x = and <4 x i64> %d1, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>141 %sh1 = lshr <4 x i64> %d1, <i64 32, i64 32, i64 32, i64 32>142 %s = add nuw nsw <4 x i64> %x, %sh1143 %sh2 = lshr <4 x i64> %s, <i64 1, i64 1, i64 1, i64 1>144 %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %sh2)145 ret i64 %res146}147 148declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)149declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)150declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)151