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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -O3 < %s -o - | FileCheck %s --check-prefixes=CHECK3 4; Tests consecutive stores of @llvm.aarch64.sve.faddv. Within SDAG faddv is5; lowered as a FADDV + EXTRACT_VECTOR_ELT (of lane 0). Stores of extracts can6; be matched by DAGCombiner::mergeConsecutiveStores(), which we want to avoid in7; some cases as it can lead to worse codegen.8 9; TODO: A single `stp s0, s1, [x0]` may be preferred here.10define void @consecutive_stores_pair(ptr %dest0, <vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1) {11; CHECK-LABEL: consecutive_stores_pair:12; CHECK: // %bb.0:13; CHECK-NEXT: ptrue p0.s14; CHECK-NEXT: faddv s0, p0, z0.s15; CHECK-NEXT: faddv s1, p0, z1.s16; CHECK-NEXT: mov v0.s[1], v1.s[0]17; CHECK-NEXT: str d0, [x0]18; CHECK-NEXT: ret19 %dest1 = getelementptr inbounds i8, ptr %dest0, i64 420 %reduce0 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec0)21 %reduce1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec1)22 store float %reduce0, ptr %dest0, align 423 store float %reduce1, ptr %dest1, align 424 ret void25}26 27define void @consecutive_stores_quadruple(ptr %dest0, <vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1, <vscale x 4 x float> %vec2, <vscale x 4 x float> %vec3) {28; CHECK-LABEL: consecutive_stores_quadruple:29; CHECK: // %bb.0:30; CHECK-NEXT: ptrue p0.s31; CHECK-NEXT: faddv s0, p0, z0.s32; CHECK-NEXT: faddv s1, p0, z1.s33; CHECK-NEXT: faddv s2, p0, z2.s34; CHECK-NEXT: mov v0.s[1], v1.s[0]35; CHECK-NEXT: faddv s3, p0, z3.s36; CHECK-NEXT: mov v2.s[1], v3.s[0]37; CHECK-NEXT: stp d0, d2, [x0]38; CHECK-NEXT: ret39 %dest1 = getelementptr inbounds i8, ptr %dest0, i64 440 %dest2 = getelementptr inbounds i8, ptr %dest1, i64 441 %dest3 = getelementptr inbounds i8, ptr %dest2, i64 442 %reduce0 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec0)43 %reduce1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec1)44 %reduce2 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec2)45 %reduce3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec3)46 store float %reduce0, ptr %dest0, align 447 store float %reduce1, ptr %dest1, align 448 store float %reduce2, ptr %dest2, align 449 store float %reduce3, ptr %dest3, align 450 ret void51}52 53define void @consecutive_stores_pair_streaming_function(ptr %dest0, <vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1) "aarch64_pstate_sm_enabled" {54; CHECK-LABEL: consecutive_stores_pair_streaming_function:55; CHECK: // %bb.0:56; CHECK-NEXT: ptrue p0.s57; CHECK-NEXT: faddv s0, p0, z0.s58; CHECK-NEXT: faddv s1, p0, z1.s59; CHECK-NEXT: stp s0, s1, [x0]60; CHECK-NEXT: ret61 %dest1 = getelementptr inbounds i8, ptr %dest0, i64 462 %reduce0 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec0)63 %reduce1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec1)64 store float %reduce0, ptr %dest0, align 465 store float %reduce1, ptr %dest1, align 466 ret void67}68 69define void @consecutive_stores_quadruple_streaming_function(ptr %dest0, <vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1, <vscale x 4 x float> %vec2, <vscale x 4 x float> %vec3) "aarch64_pstate_sm_enabled" {70; CHECK-LABEL: consecutive_stores_quadruple_streaming_function:71; CHECK: // %bb.0:72; CHECK-NEXT: ptrue p0.s73; CHECK-NEXT: faddv s0, p0, z0.s74; CHECK-NEXT: faddv s1, p0, z1.s75; CHECK-NEXT: faddv s2, p0, z2.s76; CHECK-NEXT: stp s0, s1, [x0]77; CHECK-NEXT: faddv s3, p0, z3.s78; CHECK-NEXT: stp s2, s3, [x0, #8]79; CHECK-NEXT: ret80 %dest1 = getelementptr inbounds i8, ptr %dest0, i64 481 %dest2 = getelementptr inbounds i8, ptr %dest1, i64 482 %dest3 = getelementptr inbounds i8, ptr %dest2, i64 483 %reduce0 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec0)84 %reduce1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec1)85 %reduce2 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec2)86 %reduce3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat(i1 true), <vscale x 4 x float> %vec3)87 store float %reduce0, ptr %dest0, align 488 store float %reduce1, ptr %dest1, align 489 store float %reduce2, ptr %dest2, align 490 store float %reduce3, ptr %dest3, align 491 ret void92}93