1098 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; The mask is all-ones, potentially shifted.5 6;------------------------------------------------------------------------------;7; 8-bit8;------------------------------------------------------------------------------;9 10; lshr11 12define i8 @test_i8_7_mask_lshr_1(i8 %a0) {13; CHECK-LABEL: test_i8_7_mask_lshr_1:14; CHECK: // %bb.0:15; CHECK-NEXT: ubfx w0, w0, #1, #216; CHECK-NEXT: ret17 %t0 = and i8 %a0, 718 %t1 = lshr i8 %t0, 119 ret i8 %t120}21 22define i8 @test_i8_28_mask_lshr_1(i8 %a0) {23; CHECK-LABEL: test_i8_28_mask_lshr_1:24; CHECK: // %bb.0:25; CHECK-NEXT: and w8, w0, #0x1c26; CHECK-NEXT: lsr w0, w8, #127; CHECK-NEXT: ret28 %t0 = and i8 %a0, 2829 %t1 = lshr i8 %t0, 130 ret i8 %t131}32define i8 @test_i8_28_mask_lshr_2(i8 %a0) {33; CHECK-LABEL: test_i8_28_mask_lshr_2:34; CHECK: // %bb.0:35; CHECK-NEXT: ubfx w0, w0, #2, #336; CHECK-NEXT: ret37 %t0 = and i8 %a0, 2838 %t1 = lshr i8 %t0, 239 ret i8 %t140}41define i8 @test_i8_28_mask_lshr_3(i8 %a0) {42; CHECK-LABEL: test_i8_28_mask_lshr_3:43; CHECK: // %bb.0:44; CHECK-NEXT: ubfx w0, w0, #3, #245; CHECK-NEXT: ret46 %t0 = and i8 %a0, 2847 %t1 = lshr i8 %t0, 348 ret i8 %t149}50define i8 @test_i8_28_mask_lshr_4(i8 %a0) {51; CHECK-LABEL: test_i8_28_mask_lshr_4:52; CHECK: // %bb.0:53; CHECK-NEXT: ubfx w0, w0, #4, #154; CHECK-NEXT: ret55 %t0 = and i8 %a0, 2856 %t1 = lshr i8 %t0, 457 ret i8 %t158}59 60define i8 @test_i8_224_mask_lshr_1(i8 %a0) {61; CHECK-LABEL: test_i8_224_mask_lshr_1:62; CHECK: // %bb.0:63; CHECK-NEXT: and w8, w0, #0xe064; CHECK-NEXT: lsr w0, w8, #165; CHECK-NEXT: ret66 %t0 = and i8 %a0, 22467 %t1 = lshr i8 %t0, 168 ret i8 %t169}70define i8 @test_i8_224_mask_lshr_4(i8 %a0) {71; CHECK-LABEL: test_i8_224_mask_lshr_4:72; CHECK: // %bb.0:73; CHECK-NEXT: and w8, w0, #0xe074; CHECK-NEXT: lsr w0, w8, #475; CHECK-NEXT: ret76 %t0 = and i8 %a0, 22477 %t1 = lshr i8 %t0, 478 ret i8 %t179}80define i8 @test_i8_224_mask_lshr_5(i8 %a0) {81; CHECK-LABEL: test_i8_224_mask_lshr_5:82; CHECK: // %bb.0:83; CHECK-NEXT: ubfx w0, w0, #5, #384; CHECK-NEXT: ret85 %t0 = and i8 %a0, 22486 %t1 = lshr i8 %t0, 587 ret i8 %t188}89define i8 @test_i8_224_mask_lshr_6(i8 %a0) {90; CHECK-LABEL: test_i8_224_mask_lshr_6:91; CHECK: // %bb.0:92; CHECK-NEXT: ubfx w0, w0, #6, #293; CHECK-NEXT: ret94 %t0 = and i8 %a0, 22495 %t1 = lshr i8 %t0, 696 ret i8 %t197}98 99; ashr100 101define i8 @test_i8_7_mask_ashr_1(i8 %a0) {102; CHECK-LABEL: test_i8_7_mask_ashr_1:103; CHECK: // %bb.0:104; CHECK-NEXT: ubfx w0, w0, #1, #2105; CHECK-NEXT: ret106 %t0 = and i8 %a0, 7107 %t1 = ashr i8 %t0, 1108 ret i8 %t1109}110 111define i8 @test_i8_28_mask_ashr_1(i8 %a0) {112; CHECK-LABEL: test_i8_28_mask_ashr_1:113; CHECK: // %bb.0:114; CHECK-NEXT: and w8, w0, #0x1c115; CHECK-NEXT: lsr w0, w8, #1116; CHECK-NEXT: ret117 %t0 = and i8 %a0, 28118 %t1 = ashr i8 %t0, 1119 ret i8 %t1120}121define i8 @test_i8_28_mask_ashr_2(i8 %a0) {122; CHECK-LABEL: test_i8_28_mask_ashr_2:123; CHECK: // %bb.0:124; CHECK-NEXT: ubfx w0, w0, #2, #3125; CHECK-NEXT: ret126 %t0 = and i8 %a0, 28127 %t1 = ashr i8 %t0, 2128 ret i8 %t1129}130define i8 @test_i8_28_mask_ashr_3(i8 %a0) {131; CHECK-LABEL: test_i8_28_mask_ashr_3:132; CHECK: // %bb.0:133; CHECK-NEXT: ubfx w0, w0, #3, #2134; CHECK-NEXT: ret135 %t0 = and i8 %a0, 28136 %t1 = ashr i8 %t0, 3137 ret i8 %t1138}139define i8 @test_i8_28_mask_ashr_4(i8 %a0) {140; CHECK-LABEL: test_i8_28_mask_ashr_4:141; CHECK: // %bb.0:142; CHECK-NEXT: ubfx w0, w0, #4, #1143; CHECK-NEXT: ret144 %t0 = and i8 %a0, 28145 %t1 = ashr i8 %t0, 4146 ret i8 %t1147}148 149define i8 @test_i8_224_mask_ashr_1(i8 %a0) {150; CHECK-LABEL: test_i8_224_mask_ashr_1:151; CHECK: // %bb.0:152; CHECK-NEXT: and w8, w0, #0xe0153; CHECK-NEXT: sbfx w0, w8, #1, #7154; CHECK-NEXT: ret155 %t0 = and i8 %a0, 224156 %t1 = ashr i8 %t0, 1157 ret i8 %t1158}159define i8 @test_i8_224_mask_ashr_4(i8 %a0) {160; CHECK-LABEL: test_i8_224_mask_ashr_4:161; CHECK: // %bb.0:162; CHECK-NEXT: and w8, w0, #0xe0163; CHECK-NEXT: sbfx w0, w8, #4, #4164; CHECK-NEXT: ret165 %t0 = and i8 %a0, 224166 %t1 = ashr i8 %t0, 4167 ret i8 %t1168}169define i8 @test_i8_224_mask_ashr_5(i8 %a0) {170; CHECK-LABEL: test_i8_224_mask_ashr_5:171; CHECK: // %bb.0:172; CHECK-NEXT: sbfx w0, w0, #5, #3173; CHECK-NEXT: ret174 %t0 = and i8 %a0, 224175 %t1 = ashr i8 %t0, 5176 ret i8 %t1177}178define i8 @test_i8_224_mask_ashr_6(i8 %a0) {179; CHECK-LABEL: test_i8_224_mask_ashr_6:180; CHECK: // %bb.0:181; CHECK-NEXT: sbfx w0, w0, #6, #2182; CHECK-NEXT: ret183 %t0 = and i8 %a0, 224184 %t1 = ashr i8 %t0, 6185 ret i8 %t1186}187 188; shl189 190define i8 @test_i8_7_mask_shl_1(i8 %a0) {191; CHECK-LABEL: test_i8_7_mask_shl_1:192; CHECK: // %bb.0:193; CHECK-NEXT: ubfiz w0, w0, #1, #3194; CHECK-NEXT: ret195 %t0 = and i8 %a0, 7196 %t1 = shl i8 %t0, 1197 ret i8 %t1198}199define i8 @test_i8_7_mask_shl_4(i8 %a0) {200; CHECK-LABEL: test_i8_7_mask_shl_4:201; CHECK: // %bb.0:202; CHECK-NEXT: ubfiz w0, w0, #4, #3203; CHECK-NEXT: ret204 %t0 = and i8 %a0, 7205 %t1 = shl i8 %t0, 4206 ret i8 %t1207}208define i8 @test_i8_7_mask_shl_5(i8 %a0) {209; CHECK-LABEL: test_i8_7_mask_shl_5:210; CHECK: // %bb.0:211; CHECK-NEXT: lsl w0, w0, #5212; CHECK-NEXT: ret213 %t0 = and i8 %a0, 7214 %t1 = shl i8 %t0, 5215 ret i8 %t1216}217define i8 @test_i8_7_mask_shl_6(i8 %a0) {218; CHECK-LABEL: test_i8_7_mask_shl_6:219; CHECK: // %bb.0:220; CHECK-NEXT: lsl w0, w0, #6221; CHECK-NEXT: ret222 %t0 = and i8 %a0, 7223 %t1 = shl i8 %t0, 6224 ret i8 %t1225}226 227define i8 @test_i8_28_mask_shl_1(i8 %a0) {228; CHECK-LABEL: test_i8_28_mask_shl_1:229; CHECK: // %bb.0:230; CHECK-NEXT: lsl w8, w0, #1231; CHECK-NEXT: and w0, w8, #0x38232; CHECK-NEXT: ret233 %t0 = and i8 %a0, 28234 %t1 = shl i8 %t0, 1235 ret i8 %t1236}237define i8 @test_i8_28_mask_shl_2(i8 %a0) {238; CHECK-LABEL: test_i8_28_mask_shl_2:239; CHECK: // %bb.0:240; CHECK-NEXT: lsl w8, w0, #2241; CHECK-NEXT: and w0, w8, #0x70242; CHECK-NEXT: ret243 %t0 = and i8 %a0, 28244 %t1 = shl i8 %t0, 2245 ret i8 %t1246}247define i8 @test_i8_28_mask_shl_3(i8 %a0) {248; CHECK-LABEL: test_i8_28_mask_shl_3:249; CHECK: // %bb.0:250; CHECK-NEXT: lsl w8, w0, #3251; CHECK-NEXT: and w0, w8, #0xe0252; CHECK-NEXT: ret253 %t0 = and i8 %a0, 28254 %t1 = shl i8 %t0, 3255 ret i8 %t1256}257define i8 @test_i8_28_mask_shl_4(i8 %a0) {258; CHECK-LABEL: test_i8_28_mask_shl_4:259; CHECK: // %bb.0:260; CHECK-NEXT: lsl w8, w0, #4261; CHECK-NEXT: and w0, w8, #0xc0262; CHECK-NEXT: ret263 %t0 = and i8 %a0, 28264 %t1 = shl i8 %t0, 4265 ret i8 %t1266}267 268define i8 @test_i8_224_mask_shl_1(i8 %a0) {269; CHECK-LABEL: test_i8_224_mask_shl_1:270; CHECK: // %bb.0:271; CHECK-NEXT: lsl w8, w0, #1272; CHECK-NEXT: and w0, w8, #0xc0273; CHECK-NEXT: ret274 %t0 = and i8 %a0, 224275 %t1 = shl i8 %t0, 1276 ret i8 %t1277}278 279;------------------------------------------------------------------------------;280; 16-bit281;------------------------------------------------------------------------------;282 283; lshr284 285define i16 @test_i16_127_mask_lshr_1(i16 %a0) {286; CHECK-LABEL: test_i16_127_mask_lshr_1:287; CHECK: // %bb.0:288; CHECK-NEXT: ubfx w0, w0, #1, #6289; CHECK-NEXT: ret290 %t0 = and i16 %a0, 127291 %t1 = lshr i16 %t0, 1292 ret i16 %t1293}294 295define i16 @test_i16_2032_mask_lshr_3(i16 %a0) {296; CHECK-LABEL: test_i16_2032_mask_lshr_3:297; CHECK: // %bb.0:298; CHECK-NEXT: and w8, w0, #0x7f0299; CHECK-NEXT: lsr w0, w8, #3300; CHECK-NEXT: ret301 %t0 = and i16 %a0, 2032302 %t1 = lshr i16 %t0, 3303 ret i16 %t1304}305define i16 @test_i16_2032_mask_lshr_4(i16 %a0) {306; CHECK-LABEL: test_i16_2032_mask_lshr_4:307; CHECK: // %bb.0:308; CHECK-NEXT: ubfx w0, w0, #4, #7309; CHECK-NEXT: ret310 %t0 = and i16 %a0, 2032311 %t1 = lshr i16 %t0, 4312 ret i16 %t1313}314define i16 @test_i16_2032_mask_lshr_5(i16 %a0) {315; CHECK-LABEL: test_i16_2032_mask_lshr_5:316; CHECK: // %bb.0:317; CHECK-NEXT: ubfx w0, w0, #5, #6318; CHECK-NEXT: ret319 %t0 = and i16 %a0, 2032320 %t1 = lshr i16 %t0, 5321 ret i16 %t1322}323define i16 @test_i16_2032_mask_lshr_6(i16 %a0) {324; CHECK-LABEL: test_i16_2032_mask_lshr_6:325; CHECK: // %bb.0:326; CHECK-NEXT: ubfx w0, w0, #6, #5327; CHECK-NEXT: ret328 %t0 = and i16 %a0, 2032329 %t1 = lshr i16 %t0, 6330 ret i16 %t1331}332 333define i16 @test_i16_65024_mask_lshr_1(i16 %a0) {334; CHECK-LABEL: test_i16_65024_mask_lshr_1:335; CHECK: // %bb.0:336; CHECK-NEXT: and w8, w0, #0xfe00337; CHECK-NEXT: lsr w0, w8, #1338; CHECK-NEXT: ret339 %t0 = and i16 %a0, 65024340 %t1 = lshr i16 %t0, 1341 ret i16 %t1342}343define i16 @test_i16_65024_mask_lshr_8(i16 %a0) {344; CHECK-LABEL: test_i16_65024_mask_lshr_8:345; CHECK: // %bb.0:346; CHECK-NEXT: and w8, w0, #0xfe00347; CHECK-NEXT: lsr w0, w8, #8348; CHECK-NEXT: ret349 %t0 = and i16 %a0, 65024350 %t1 = lshr i16 %t0, 8351 ret i16 %t1352}353define i16 @test_i16_65024_mask_lshr_9(i16 %a0) {354; CHECK-LABEL: test_i16_65024_mask_lshr_9:355; CHECK: // %bb.0:356; CHECK-NEXT: ubfx w0, w0, #9, #7357; CHECK-NEXT: ret358 %t0 = and i16 %a0, 65024359 %t1 = lshr i16 %t0, 9360 ret i16 %t1361}362define i16 @test_i16_65024_mask_lshr_10(i16 %a0) {363; CHECK-LABEL: test_i16_65024_mask_lshr_10:364; CHECK: // %bb.0:365; CHECK-NEXT: ubfx w0, w0, #10, #6366; CHECK-NEXT: ret367 %t0 = and i16 %a0, 65024368 %t1 = lshr i16 %t0, 10369 ret i16 %t1370}371 372; ashr373 374define i16 @test_i16_127_mask_ashr_1(i16 %a0) {375; CHECK-LABEL: test_i16_127_mask_ashr_1:376; CHECK: // %bb.0:377; CHECK-NEXT: ubfx w0, w0, #1, #6378; CHECK-NEXT: ret379 %t0 = and i16 %a0, 127380 %t1 = ashr i16 %t0, 1381 ret i16 %t1382}383 384define i16 @test_i16_2032_mask_ashr_3(i16 %a0) {385; CHECK-LABEL: test_i16_2032_mask_ashr_3:386; CHECK: // %bb.0:387; CHECK-NEXT: and w8, w0, #0x7f0388; CHECK-NEXT: lsr w0, w8, #3389; CHECK-NEXT: ret390 %t0 = and i16 %a0, 2032391 %t1 = ashr i16 %t0, 3392 ret i16 %t1393}394define i16 @test_i16_2032_mask_ashr_4(i16 %a0) {395; CHECK-LABEL: test_i16_2032_mask_ashr_4:396; CHECK: // %bb.0:397; CHECK-NEXT: ubfx w0, w0, #4, #7398; CHECK-NEXT: ret399 %t0 = and i16 %a0, 2032400 %t1 = ashr i16 %t0, 4401 ret i16 %t1402}403define i16 @test_i16_2032_mask_ashr_5(i16 %a0) {404; CHECK-LABEL: test_i16_2032_mask_ashr_5:405; CHECK: // %bb.0:406; CHECK-NEXT: ubfx w0, w0, #5, #6407; CHECK-NEXT: ret408 %t0 = and i16 %a0, 2032409 %t1 = ashr i16 %t0, 5410 ret i16 %t1411}412define i16 @test_i16_2032_mask_ashr_6(i16 %a0) {413; CHECK-LABEL: test_i16_2032_mask_ashr_6:414; CHECK: // %bb.0:415; CHECK-NEXT: ubfx w0, w0, #6, #5416; CHECK-NEXT: ret417 %t0 = and i16 %a0, 2032418 %t1 = ashr i16 %t0, 6419 ret i16 %t1420}421 422define i16 @test_i16_65024_mask_ashr_1(i16 %a0) {423; CHECK-LABEL: test_i16_65024_mask_ashr_1:424; CHECK: // %bb.0:425; CHECK-NEXT: and w8, w0, #0xfe00426; CHECK-NEXT: sbfx w0, w8, #1, #15427; CHECK-NEXT: ret428 %t0 = and i16 %a0, 65024429 %t1 = ashr i16 %t0, 1430 ret i16 %t1431}432define i16 @test_i16_65024_mask_ashr_8(i16 %a0) {433; CHECK-LABEL: test_i16_65024_mask_ashr_8:434; CHECK: // %bb.0:435; CHECK-NEXT: and w8, w0, #0xfe00436; CHECK-NEXT: sbfx w0, w8, #8, #8437; CHECK-NEXT: ret438 %t0 = and i16 %a0, 65024439 %t1 = ashr i16 %t0, 8440 ret i16 %t1441}442define i16 @test_i16_65024_mask_ashr_9(i16 %a0) {443; CHECK-LABEL: test_i16_65024_mask_ashr_9:444; CHECK: // %bb.0:445; CHECK-NEXT: sbfx w0, w0, #9, #7446; CHECK-NEXT: ret447 %t0 = and i16 %a0, 65024448 %t1 = ashr i16 %t0, 9449 ret i16 %t1450}451define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {452; CHECK-LABEL: test_i16_65024_mask_ashr_10:453; CHECK: // %bb.0:454; CHECK-NEXT: sbfx w0, w0, #10, #6455; CHECK-NEXT: ret456 %t0 = and i16 %a0, 65024457 %t1 = ashr i16 %t0, 10458 ret i16 %t1459}460 461; shl462 463define i16 @test_i16_127_mask_shl_1(i16 %a0) {464; CHECK-LABEL: test_i16_127_mask_shl_1:465; CHECK: // %bb.0:466; CHECK-NEXT: ubfiz w0, w0, #1, #7467; CHECK-NEXT: ret468 %t0 = and i16 %a0, 127469 %t1 = shl i16 %t0, 1470 ret i16 %t1471}472define i16 @test_i16_127_mask_shl_8(i16 %a0) {473; CHECK-LABEL: test_i16_127_mask_shl_8:474; CHECK: // %bb.0:475; CHECK-NEXT: ubfiz w0, w0, #8, #7476; CHECK-NEXT: ret477 %t0 = and i16 %a0, 127478 %t1 = shl i16 %t0, 8479 ret i16 %t1480}481define i16 @test_i16_127_mask_shl_9(i16 %a0) {482; CHECK-LABEL: test_i16_127_mask_shl_9:483; CHECK: // %bb.0:484; CHECK-NEXT: lsl w0, w0, #9485; CHECK-NEXT: ret486 %t0 = and i16 %a0, 127487 %t1 = shl i16 %t0, 9488 ret i16 %t1489}490define i16 @test_i16_127_mask_shl_10(i16 %a0) {491; CHECK-LABEL: test_i16_127_mask_shl_10:492; CHECK: // %bb.0:493; CHECK-NEXT: lsl w0, w0, #10494; CHECK-NEXT: ret495 %t0 = and i16 %a0, 127496 %t1 = shl i16 %t0, 10497 ret i16 %t1498}499 500define i16 @test_i16_2032_mask_shl_3(i16 %a0) {501; CHECK-LABEL: test_i16_2032_mask_shl_3:502; CHECK: // %bb.0:503; CHECK-NEXT: lsl w8, w0, #3504; CHECK-NEXT: and w0, w8, #0x3f80505; CHECK-NEXT: ret506 %t0 = and i16 %a0, 2032507 %t1 = shl i16 %t0, 3508 ret i16 %t1509}510define i16 @test_i16_2032_mask_shl_4(i16 %a0) {511; CHECK-LABEL: test_i16_2032_mask_shl_4:512; CHECK: // %bb.0:513; CHECK-NEXT: lsl w8, w0, #4514; CHECK-NEXT: and w0, w8, #0x7f00515; CHECK-NEXT: ret516 %t0 = and i16 %a0, 2032517 %t1 = shl i16 %t0, 4518 ret i16 %t1519}520define i16 @test_i16_2032_mask_shl_5(i16 %a0) {521; CHECK-LABEL: test_i16_2032_mask_shl_5:522; CHECK: // %bb.0:523; CHECK-NEXT: lsl w8, w0, #5524; CHECK-NEXT: and w0, w8, #0xfe00525; CHECK-NEXT: ret526 %t0 = and i16 %a0, 2032527 %t1 = shl i16 %t0, 5528 ret i16 %t1529}530define i16 @test_i16_2032_mask_shl_6(i16 %a0) {531; CHECK-LABEL: test_i16_2032_mask_shl_6:532; CHECK: // %bb.0:533; CHECK-NEXT: lsl w8, w0, #6534; CHECK-NEXT: and w0, w8, #0xfc00535; CHECK-NEXT: ret536 %t0 = and i16 %a0, 2032537 %t1 = shl i16 %t0, 6538 ret i16 %t1539}540 541define i16 @test_i16_65024_mask_shl_1(i16 %a0) {542; CHECK-LABEL: test_i16_65024_mask_shl_1:543; CHECK: // %bb.0:544; CHECK-NEXT: lsl w8, w0, #1545; CHECK-NEXT: and w0, w8, #0xfc00546; CHECK-NEXT: ret547 %t0 = and i16 %a0, 65024548 %t1 = shl i16 %t0, 1549 ret i16 %t1550}551 552;------------------------------------------------------------------------------;553; 32-bit554;------------------------------------------------------------------------------;555 556; lshr557 558define i32 @test_i32_32767_mask_lshr_1(i32 %a0) {559; CHECK-LABEL: test_i32_32767_mask_lshr_1:560; CHECK: // %bb.0:561; CHECK-NEXT: ubfx w0, w0, #1, #14562; CHECK-NEXT: ret563 %t0 = and i32 %a0, 32767564 %t1 = lshr i32 %t0, 1565 ret i32 %t1566}567 568define i32 @test_i32_8388352_mask_lshr_7(i32 %a0) {569; CHECK-LABEL: test_i32_8388352_mask_lshr_7:570; CHECK: // %bb.0:571; CHECK-NEXT: and w8, w0, #0x7fff00572; CHECK-NEXT: lsr w0, w8, #7573; CHECK-NEXT: ret574 %t0 = and i32 %a0, 8388352575 %t1 = lshr i32 %t0, 7576 ret i32 %t1577}578define i32 @test_i32_8388352_mask_lshr_8(i32 %a0) {579; CHECK-LABEL: test_i32_8388352_mask_lshr_8:580; CHECK: // %bb.0:581; CHECK-NEXT: ubfx w0, w0, #8, #15582; CHECK-NEXT: ret583 %t0 = and i32 %a0, 8388352584 %t1 = lshr i32 %t0, 8585 ret i32 %t1586}587define i32 @test_i32_8388352_mask_lshr_9(i32 %a0) {588; CHECK-LABEL: test_i32_8388352_mask_lshr_9:589; CHECK: // %bb.0:590; CHECK-NEXT: ubfx w0, w0, #9, #14591; CHECK-NEXT: ret592 %t0 = and i32 %a0, 8388352593 %t1 = lshr i32 %t0, 9594 ret i32 %t1595}596define i32 @test_i32_8388352_mask_lshr_10(i32 %a0) {597; CHECK-LABEL: test_i32_8388352_mask_lshr_10:598; CHECK: // %bb.0:599; CHECK-NEXT: ubfx w0, w0, #10, #13600; CHECK-NEXT: ret601 %t0 = and i32 %a0, 8388352602 %t1 = lshr i32 %t0, 10603 ret i32 %t1604}605 606define i32 @test_i32_4294836224_mask_lshr_1(i32 %a0) {607; CHECK-LABEL: test_i32_4294836224_mask_lshr_1:608; CHECK: // %bb.0:609; CHECK-NEXT: and w8, w0, #0xfffe0000610; CHECK-NEXT: lsr w0, w8, #1611; CHECK-NEXT: ret612 %t0 = and i32 %a0, 4294836224613 %t1 = lshr i32 %t0, 1614 ret i32 %t1615}616define i32 @test_i32_4294836224_mask_lshr_16(i32 %a0) {617; CHECK-LABEL: test_i32_4294836224_mask_lshr_16:618; CHECK: // %bb.0:619; CHECK-NEXT: and w8, w0, #0xfffe0000620; CHECK-NEXT: lsr w0, w8, #16621; CHECK-NEXT: ret622 %t0 = and i32 %a0, 4294836224623 %t1 = lshr i32 %t0, 16624 ret i32 %t1625}626define i32 @test_i32_4294836224_mask_lshr_17(i32 %a0) {627; CHECK-LABEL: test_i32_4294836224_mask_lshr_17:628; CHECK: // %bb.0:629; CHECK-NEXT: lsr w0, w0, #17630; CHECK-NEXT: ret631 %t0 = and i32 %a0, 4294836224632 %t1 = lshr i32 %t0, 17633 ret i32 %t1634}635define i32 @test_i32_4294836224_mask_lshr_18(i32 %a0) {636; CHECK-LABEL: test_i32_4294836224_mask_lshr_18:637; CHECK: // %bb.0:638; CHECK-NEXT: lsr w0, w0, #18639; CHECK-NEXT: ret640 %t0 = and i32 %a0, 4294836224641 %t1 = lshr i32 %t0, 18642 ret i32 %t1643}644 645; ashr646 647define i32 @test_i32_32767_mask_ashr_1(i32 %a0) {648; CHECK-LABEL: test_i32_32767_mask_ashr_1:649; CHECK: // %bb.0:650; CHECK-NEXT: ubfx w0, w0, #1, #14651; CHECK-NEXT: ret652 %t0 = and i32 %a0, 32767653 %t1 = ashr i32 %t0, 1654 ret i32 %t1655}656 657define i32 @test_i32_8388352_mask_ashr_7(i32 %a0) {658; CHECK-LABEL: test_i32_8388352_mask_ashr_7:659; CHECK: // %bb.0:660; CHECK-NEXT: and w8, w0, #0x7fff00661; CHECK-NEXT: lsr w0, w8, #7662; CHECK-NEXT: ret663 %t0 = and i32 %a0, 8388352664 %t1 = ashr i32 %t0, 7665 ret i32 %t1666}667define i32 @test_i32_8388352_mask_ashr_8(i32 %a0) {668; CHECK-LABEL: test_i32_8388352_mask_ashr_8:669; CHECK: // %bb.0:670; CHECK-NEXT: ubfx w0, w0, #8, #15671; CHECK-NEXT: ret672 %t0 = and i32 %a0, 8388352673 %t1 = ashr i32 %t0, 8674 ret i32 %t1675}676define i32 @test_i32_8388352_mask_ashr_9(i32 %a0) {677; CHECK-LABEL: test_i32_8388352_mask_ashr_9:678; CHECK: // %bb.0:679; CHECK-NEXT: ubfx w0, w0, #9, #14680; CHECK-NEXT: ret681 %t0 = and i32 %a0, 8388352682 %t1 = ashr i32 %t0, 9683 ret i32 %t1684}685define i32 @test_i32_8388352_mask_ashr_10(i32 %a0) {686; CHECK-LABEL: test_i32_8388352_mask_ashr_10:687; CHECK: // %bb.0:688; CHECK-NEXT: ubfx w0, w0, #10, #13689; CHECK-NEXT: ret690 %t0 = and i32 %a0, 8388352691 %t1 = ashr i32 %t0, 10692 ret i32 %t1693}694 695define i32 @test_i32_4294836224_mask_ashr_1(i32 %a0) {696; CHECK-LABEL: test_i32_4294836224_mask_ashr_1:697; CHECK: // %bb.0:698; CHECK-NEXT: and w8, w0, #0xfffe0000699; CHECK-NEXT: asr w0, w8, #1700; CHECK-NEXT: ret701 %t0 = and i32 %a0, 4294836224702 %t1 = ashr i32 %t0, 1703 ret i32 %t1704}705define i32 @test_i32_4294836224_mask_ashr_16(i32 %a0) {706; CHECK-LABEL: test_i32_4294836224_mask_ashr_16:707; CHECK: // %bb.0:708; CHECK-NEXT: and w8, w0, #0xfffe0000709; CHECK-NEXT: asr w0, w8, #16710; CHECK-NEXT: ret711 %t0 = and i32 %a0, 4294836224712 %t1 = ashr i32 %t0, 16713 ret i32 %t1714}715define i32 @test_i32_4294836224_mask_ashr_17(i32 %a0) {716; CHECK-LABEL: test_i32_4294836224_mask_ashr_17:717; CHECK: // %bb.0:718; CHECK-NEXT: asr w0, w0, #17719; CHECK-NEXT: ret720 %t0 = and i32 %a0, 4294836224721 %t1 = ashr i32 %t0, 17722 ret i32 %t1723}724define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {725; CHECK-LABEL: test_i32_4294836224_mask_ashr_18:726; CHECK: // %bb.0:727; CHECK-NEXT: asr w0, w0, #18728; CHECK-NEXT: ret729 %t0 = and i32 %a0, 4294836224730 %t1 = ashr i32 %t0, 18731 ret i32 %t1732}733 734; shl735 736define i32 @test_i32_32767_mask_shl_1(i32 %a0) {737; CHECK-LABEL: test_i32_32767_mask_shl_1:738; CHECK: // %bb.0:739; CHECK-NEXT: ubfiz w0, w0, #1, #15740; CHECK-NEXT: ret741 %t0 = and i32 %a0, 32767742 %t1 = shl i32 %t0, 1743 ret i32 %t1744}745define i32 @test_i32_32767_mask_shl_16(i32 %a0) {746; CHECK-LABEL: test_i32_32767_mask_shl_16:747; CHECK: // %bb.0:748; CHECK-NEXT: ubfiz w0, w0, #16, #15749; CHECK-NEXT: ret750 %t0 = and i32 %a0, 32767751 %t1 = shl i32 %t0, 16752 ret i32 %t1753}754define i32 @test_i32_32767_mask_shl_17(i32 %a0) {755; CHECK-LABEL: test_i32_32767_mask_shl_17:756; CHECK: // %bb.0:757; CHECK-NEXT: lsl w0, w0, #17758; CHECK-NEXT: ret759 %t0 = and i32 %a0, 32767760 %t1 = shl i32 %t0, 17761 ret i32 %t1762}763define i32 @test_i32_32767_mask_shl_18(i32 %a0) {764; CHECK-LABEL: test_i32_32767_mask_shl_18:765; CHECK: // %bb.0:766; CHECK-NEXT: lsl w0, w0, #18767; CHECK-NEXT: ret768 %t0 = and i32 %a0, 32767769 %t1 = shl i32 %t0, 18770 ret i32 %t1771}772 773define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {774; CHECK-LABEL: test_i32_8388352_mask_shl_7:775; CHECK: // %bb.0:776; CHECK-NEXT: lsl w8, w0, #7777; CHECK-NEXT: and w0, w8, #0x3fff8000778; CHECK-NEXT: ret779 %t0 = and i32 %a0, 8388352780 %t1 = shl i32 %t0, 7781 ret i32 %t1782}783define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {784; CHECK-LABEL: test_i32_8388352_mask_shl_8:785; CHECK: // %bb.0:786; CHECK-NEXT: lsl w8, w0, #8787; CHECK-NEXT: and w0, w8, #0x7fff0000788; CHECK-NEXT: ret789 %t0 = and i32 %a0, 8388352790 %t1 = shl i32 %t0, 8791 ret i32 %t1792}793define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {794; CHECK-LABEL: test_i32_8388352_mask_shl_9:795; CHECK: // %bb.0:796; CHECK-NEXT: lsl w8, w0, #9797; CHECK-NEXT: and w0, w8, #0xfffe0000798; CHECK-NEXT: ret799 %t0 = and i32 %a0, 8388352800 %t1 = shl i32 %t0, 9801 ret i32 %t1802}803define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {804; CHECK-LABEL: test_i32_8388352_mask_shl_10:805; CHECK: // %bb.0:806; CHECK-NEXT: lsl w8, w0, #10807; CHECK-NEXT: and w0, w8, #0xfffc0000808; CHECK-NEXT: ret809 %t0 = and i32 %a0, 8388352810 %t1 = shl i32 %t0, 10811 ret i32 %t1812}813 814define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {815; CHECK-LABEL: test_i32_4294836224_mask_shl_1:816; CHECK: // %bb.0:817; CHECK-NEXT: lsl w8, w0, #1818; CHECK-NEXT: and w0, w8, #0xfffc0000819; CHECK-NEXT: ret820 %t0 = and i32 %a0, 4294836224821 %t1 = shl i32 %t0, 1822 ret i32 %t1823}824 825;------------------------------------------------------------------------------;826; 64-bit827;------------------------------------------------------------------------------;828 829; lshr830 831define i64 @test_i64_2147483647_mask_lshr_1(i64 %a0) {832; CHECK-LABEL: test_i64_2147483647_mask_lshr_1:833; CHECK: // %bb.0:834; CHECK-NEXT: ubfx x0, x0, #1, #30835; CHECK-NEXT: ret836 %t0 = and i64 %a0, 2147483647837 %t1 = lshr i64 %t0, 1838 ret i64 %t1839}840 841define i64 @test_i64_140737488289792_mask_lshr_15(i64 %a0) {842; CHECK-LABEL: test_i64_140737488289792_mask_lshr_15:843; CHECK: // %bb.0:844; CHECK-NEXT: and x8, x0, #0x7fffffff0000845; CHECK-NEXT: lsr x0, x8, #15846; CHECK-NEXT: ret847 %t0 = and i64 %a0, 140737488289792848 %t1 = lshr i64 %t0, 15849 ret i64 %t1850}851define i64 @test_i64_140737488289792_mask_lshr_16(i64 %a0) {852; CHECK-LABEL: test_i64_140737488289792_mask_lshr_16:853; CHECK: // %bb.0:854; CHECK-NEXT: ubfx x0, x0, #16, #31855; CHECK-NEXT: ret856 %t0 = and i64 %a0, 140737488289792857 %t1 = lshr i64 %t0, 16858 ret i64 %t1859}860define i64 @test_i64_140737488289792_mask_lshr_17(i64 %a0) {861; CHECK-LABEL: test_i64_140737488289792_mask_lshr_17:862; CHECK: // %bb.0:863; CHECK-NEXT: ubfx x0, x0, #17, #30864; CHECK-NEXT: ret865 %t0 = and i64 %a0, 140737488289792866 %t1 = lshr i64 %t0, 17867 ret i64 %t1868}869define i64 @test_i64_140737488289792_mask_lshr_18(i64 %a0) {870; CHECK-LABEL: test_i64_140737488289792_mask_lshr_18:871; CHECK: // %bb.0:872; CHECK-NEXT: ubfx x0, x0, #18, #29873; CHECK-NEXT: ret874 %t0 = and i64 %a0, 140737488289792875 %t1 = lshr i64 %t0, 18876 ret i64 %t1877}878 879define i64 @test_i64_18446744065119617024_mask_lshr_1(i64 %a0) {880; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_1:881; CHECK: // %bb.0:882; CHECK-NEXT: and x8, x0, #0xfffffffe00000000883; CHECK-NEXT: lsr x0, x8, #1884; CHECK-NEXT: ret885 %t0 = and i64 %a0, 18446744065119617024886 %t1 = lshr i64 %t0, 1887 ret i64 %t1888}889define i64 @test_i64_18446744065119617024_mask_lshr_32(i64 %a0) {890; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_32:891; CHECK: // %bb.0:892; CHECK-NEXT: and x8, x0, #0xfffffffe00000000893; CHECK-NEXT: lsr x0, x8, #32894; CHECK-NEXT: ret895 %t0 = and i64 %a0, 18446744065119617024896 %t1 = lshr i64 %t0, 32897 ret i64 %t1898}899define i64 @test_i64_18446744065119617024_mask_lshr_33(i64 %a0) {900; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_33:901; CHECK: // %bb.0:902; CHECK-NEXT: lsr x0, x0, #33903; CHECK-NEXT: ret904 %t0 = and i64 %a0, 18446744065119617024905 %t1 = lshr i64 %t0, 33906 ret i64 %t1907}908define i64 @test_i64_18446744065119617024_mask_lshr_34(i64 %a0) {909; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_34:910; CHECK: // %bb.0:911; CHECK-NEXT: lsr x0, x0, #34912; CHECK-NEXT: ret913 %t0 = and i64 %a0, 18446744065119617024914 %t1 = lshr i64 %t0, 34915 ret i64 %t1916}917 918; ashr919 920define i64 @test_i64_2147483647_mask_ashr_1(i64 %a0) {921; CHECK-LABEL: test_i64_2147483647_mask_ashr_1:922; CHECK: // %bb.0:923; CHECK-NEXT: ubfx x0, x0, #1, #30924; CHECK-NEXT: ret925 %t0 = and i64 %a0, 2147483647926 %t1 = ashr i64 %t0, 1927 ret i64 %t1928}929 930define i64 @test_i64_140737488289792_mask_ashr_15(i64 %a0) {931; CHECK-LABEL: test_i64_140737488289792_mask_ashr_15:932; CHECK: // %bb.0:933; CHECK-NEXT: and x8, x0, #0x7fffffff0000934; CHECK-NEXT: lsr x0, x8, #15935; CHECK-NEXT: ret936 %t0 = and i64 %a0, 140737488289792937 %t1 = ashr i64 %t0, 15938 ret i64 %t1939}940define i64 @test_i64_140737488289792_mask_ashr_16(i64 %a0) {941; CHECK-LABEL: test_i64_140737488289792_mask_ashr_16:942; CHECK: // %bb.0:943; CHECK-NEXT: ubfx x0, x0, #16, #31944; CHECK-NEXT: ret945 %t0 = and i64 %a0, 140737488289792946 %t1 = ashr i64 %t0, 16947 ret i64 %t1948}949define i64 @test_i64_140737488289792_mask_ashr_17(i64 %a0) {950; CHECK-LABEL: test_i64_140737488289792_mask_ashr_17:951; CHECK: // %bb.0:952; CHECK-NEXT: ubfx x0, x0, #17, #30953; CHECK-NEXT: ret954 %t0 = and i64 %a0, 140737488289792955 %t1 = ashr i64 %t0, 17956 ret i64 %t1957}958define i64 @test_i64_140737488289792_mask_ashr_18(i64 %a0) {959; CHECK-LABEL: test_i64_140737488289792_mask_ashr_18:960; CHECK: // %bb.0:961; CHECK-NEXT: ubfx x0, x0, #18, #29962; CHECK-NEXT: ret963 %t0 = and i64 %a0, 140737488289792964 %t1 = ashr i64 %t0, 18965 ret i64 %t1966}967 968define i64 @test_i64_18446744065119617024_mask_ashr_1(i64 %a0) {969; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_1:970; CHECK: // %bb.0:971; CHECK-NEXT: and x8, x0, #0xfffffffe00000000972; CHECK-NEXT: asr x0, x8, #1973; CHECK-NEXT: ret974 %t0 = and i64 %a0, 18446744065119617024975 %t1 = ashr i64 %t0, 1976 ret i64 %t1977}978define i64 @test_i64_18446744065119617024_mask_ashr_32(i64 %a0) {979; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_32:980; CHECK: // %bb.0:981; CHECK-NEXT: and x8, x0, #0xfffffffe00000000982; CHECK-NEXT: asr x0, x8, #32983; CHECK-NEXT: ret984 %t0 = and i64 %a0, 18446744065119617024985 %t1 = ashr i64 %t0, 32986 ret i64 %t1987}988define i64 @test_i64_18446744065119617024_mask_ashr_33(i64 %a0) {989; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_33:990; CHECK: // %bb.0:991; CHECK-NEXT: asr x0, x0, #33992; CHECK-NEXT: ret993 %t0 = and i64 %a0, 18446744065119617024994 %t1 = ashr i64 %t0, 33995 ret i64 %t1996}997define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {998; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_34:999; CHECK: // %bb.0:1000; CHECK-NEXT: asr x0, x0, #341001; CHECK-NEXT: ret1002 %t0 = and i64 %a0, 184467440651196170241003 %t1 = ashr i64 %t0, 341004 ret i64 %t11005}1006 1007; shl1008 1009define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {1010; CHECK-LABEL: test_i64_2147483647_mask_shl_1:1011; CHECK: // %bb.0:1012; CHECK-NEXT: lsl w0, w0, #11013; CHECK-NEXT: ret1014 %t0 = and i64 %a0, 21474836471015 %t1 = shl i64 %t0, 11016 ret i64 %t11017}1018define i64 @test_i64_2147483647_mask_shl_32(i64 %a0) {1019; CHECK-LABEL: test_i64_2147483647_mask_shl_32:1020; CHECK: // %bb.0:1021; CHECK-NEXT: and w8, w0, #0x7fffffff1022; CHECK-NEXT: lsl x0, x8, #321023; CHECK-NEXT: ret1024 %t0 = and i64 %a0, 21474836471025 %t1 = shl i64 %t0, 321026 ret i64 %t11027}1028define i64 @test_i64_2147483647_mask_shl_33(i64 %a0) {1029; CHECK-LABEL: test_i64_2147483647_mask_shl_33:1030; CHECK: // %bb.0:1031; CHECK-NEXT: lsl x0, x0, #331032; CHECK-NEXT: ret1033 %t0 = and i64 %a0, 21474836471034 %t1 = shl i64 %t0, 331035 ret i64 %t11036}1037define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {1038; CHECK-LABEL: test_i64_2147483647_mask_shl_34:1039; CHECK: // %bb.0:1040; CHECK-NEXT: lsl x0, x0, #341041; CHECK-NEXT: ret1042 %t0 = and i64 %a0, 21474836471043 %t1 = shl i64 %t0, 341044 ret i64 %t11045}1046 1047define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {1048; CHECK-LABEL: test_i64_140737488289792_mask_shl_15:1049; CHECK: // %bb.0:1050; CHECK-NEXT: lsl x8, x0, #151051; CHECK-NEXT: and x0, x8, #0x3fffffff800000001052; CHECK-NEXT: ret1053 %t0 = and i64 %a0, 1407374882897921054 %t1 = shl i64 %t0, 151055 ret i64 %t11056}1057define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {1058; CHECK-LABEL: test_i64_140737488289792_mask_shl_16:1059; CHECK: // %bb.0:1060; CHECK-NEXT: lsl x8, x0, #161061; CHECK-NEXT: and x0, x8, #0x7fffffff000000001062; CHECK-NEXT: ret1063 %t0 = and i64 %a0, 1407374882897921064 %t1 = shl i64 %t0, 161065 ret i64 %t11066}1067define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {1068; CHECK-LABEL: test_i64_140737488289792_mask_shl_17:1069; CHECK: // %bb.0:1070; CHECK-NEXT: lsl x8, x0, #171071; CHECK-NEXT: and x0, x8, #0xfffffffe000000001072; CHECK-NEXT: ret1073 %t0 = and i64 %a0, 1407374882897921074 %t1 = shl i64 %t0, 171075 ret i64 %t11076}1077define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {1078; CHECK-LABEL: test_i64_140737488289792_mask_shl_18:1079; CHECK: // %bb.0:1080; CHECK-NEXT: lsl x8, x0, #181081; CHECK-NEXT: and x0, x8, #0xfffffffc000000001082; CHECK-NEXT: ret1083 %t0 = and i64 %a0, 1407374882897921084 %t1 = shl i64 %t0, 181085 ret i64 %t11086}1087 1088define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {1089; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1:1090; CHECK: // %bb.0:1091; CHECK-NEXT: lsl x8, x0, #11092; CHECK-NEXT: and x0, x8, #0xfffffffc000000001093; CHECK-NEXT: ret1094 %t0 = and i64 %a0, 184467440651196170241095 %t1 = shl i64 %t0, 11096 ret i64 %t11097}1098