1134 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s3 4declare void @use_i1(i1 %x)5declare void @use_i32(i32 %x)6 7; Based on the IR generated for the `last` method of the type `slice` in Rust8define ptr @test_last_elem_from_ptr(ptr noundef readnone %x0, i64 noundef %x1) {9; CHECK-LABEL: test_last_elem_from_ptr:10; CHECK: // %bb.0:11; CHECK-NEXT: subs x8, x1, #112; CHECK-NEXT: add x8, x8, x013; CHECK-NEXT: csel x0, xzr, x8, lo14; CHECK-NEXT: ret15 %cmp = icmp eq i64 %x1, 016 %add.ptr = getelementptr inbounds nuw i8, ptr %x0, i64 %x117 %add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 -118 %retval.0 = select i1 %cmp, ptr null, ptr %add.ptr119 ret ptr %retval.020}21 22define i32 @test_eq0_sub_add_i32(i32 %x0, i32 %x1) {23; CHECK-LABEL: test_eq0_sub_add_i32:24; CHECK: // %bb.0:25; CHECK-NEXT: subs w8, w1, #126; CHECK-NEXT: add w8, w8, w027; CHECK-NEXT: csel w0, wzr, w8, lo28; CHECK-NEXT: ret29 %cmp = icmp eq i32 %x1, 030 %add = add nuw i32 %x0, %x131 %sub = sub i32 %add, 132 %ret = select i1 %cmp, i32 0, i32 %sub33 ret i32 %ret34}35 36define i32 @test_eq7_sub_add_i32(i32 %x0, i32 %x1) {37; CHECK-LABEL: test_eq7_sub_add_i32:38; CHECK: // %bb.0:39; CHECK-NEXT: subs w8, w1, #740; CHECK-NEXT: add w8, w8, w041; CHECK-NEXT: csel w0, wzr, w8, eq42; CHECK-NEXT: ret43 %cmp = icmp eq i32 %x1, 744 %add = add nuw i32 %x0, %x145 %sub = sub i32 %add, 746 %ret = select i1 %cmp, i32 0, i32 %sub47 ret i32 %ret48}49 50define i32 @test_ule7_sub7_add_i32(i32 %x0, i32 %x1) {51; CHECK-LABEL: test_ule7_sub7_add_i32:52; CHECK: // %bb.0:53; CHECK-NEXT: subs w8, w1, #754; CHECK-NEXT: add w8, w8, w055; CHECK-NEXT: csel w0, wzr, w8, ls56; CHECK-NEXT: ret57 %cmp = icmp ule i32 %x1, 758 %add = add i32 %x0, %x159 %sub = sub i32 %add, 760 %ret = select i1 %cmp, i32 0, i32 %sub61 ret i32 %ret62}63 64define i32 @test_ule7_sub8_add_i32(i32 %x0, i32 %x1) {65; CHECK-LABEL: test_ule7_sub8_add_i32:66; CHECK: // %bb.0:67; CHECK-NEXT: subs w8, w1, #868; CHECK-NEXT: add w8, w8, w069; CHECK-NEXT: csel w0, wzr, w8, lo70; CHECK-NEXT: ret71 %cmp = icmp ule i32 %x1, 772 %add = add i32 %x0, %x173 %sub = sub i32 %add, 874 %ret = select i1 %cmp, i32 0, i32 %sub75 ret i32 %ret76}77 78define i32 @test_ule0_sub1_add_i32(i32 %x0, i32 %x1) {79; CHECK-LABEL: test_ule0_sub1_add_i32:80; CHECK: // %bb.0:81; CHECK-NEXT: subs w8, w1, #182; CHECK-NEXT: add w8, w8, w083; CHECK-NEXT: csel w0, wzr, w8, lo84; CHECK-NEXT: ret85 %cmp = icmp ule i32 %x1, 086 %add = add i32 %x0, %x187 %sub = sub i32 %add, 188 %ret = select i1 %cmp, i32 0, i32 %sub89 ret i32 %ret90}91 92define i32 @test_ultminus2_subminus2_add_i32(i32 %x0, i32 %x1) {93; CHECK-LABEL: test_ultminus2_subminus2_add_i32:94; CHECK: // %bb.0:95; CHECK-NEXT: adds w8, w1, #296; CHECK-NEXT: add w8, w8, w097; CHECK-NEXT: csel w0, wzr, w8, lo98; CHECK-NEXT: ret99 %cmp = icmp ult i32 %x1, -2100 %add = add i32 %x0, %x1101 %sub = sub i32 %add, -2102 %ret = select i1 %cmp, i32 0, i32 %sub103 ret i32 %ret104}105 106define i32 @test_ultminus2_subminus3_add_i32(i32 %x0, i32 %x1) {107; CHECK-LABEL: test_ultminus2_subminus3_add_i32:108; CHECK: // %bb.0:109; CHECK-NEXT: adds w8, w1, #3110; CHECK-NEXT: add w8, w8, w0111; CHECK-NEXT: csel w0, wzr, w8, ls112; CHECK-NEXT: ret113 %cmp = icmp ult i32 %x1, -2114 %add = add i32 %x0, %x1115 %sub = sub i32 %add, -3116 %ret = select i1 %cmp, i32 0, i32 %sub117 ret i32 %ret118}119 120define i32 @test_ne0_sub_add_i32(i32 %x0, i32 %x1) {121; CHECK-LABEL: test_ne0_sub_add_i32:122; CHECK: // %bb.0:123; CHECK-NEXT: subs w8, w1, #1124; CHECK-NEXT: add w8, w8, w0125; CHECK-NEXT: csel w0, w8, wzr, hs126; CHECK-NEXT: ret127 %cmp = icmp ne i32 %x1, 0128 %add = add i32 %x0, %x1129 %sub = sub i32 %add, 1130 %ret = select i1 %cmp, i32 %sub, i32 0131 ret i32 %ret132}133 134define i32 @test_ne7_sub_add_i32(i32 %x0, i32 %x1) {135; CHECK-LABEL: test_ne7_sub_add_i32:136; CHECK: // %bb.0:137; CHECK-NEXT: subs w8, w1, #7138; CHECK-NEXT: add w8, w8, w0139; CHECK-NEXT: csel w0, w8, wzr, ne140; CHECK-NEXT: ret141 %cmp = icmp ne i32 %x1, 7142 %add = add i32 %x0, %x1143 %sub = sub i32 %add, 7144 %ret = select i1 %cmp, i32 %sub, i32 0145 ret i32 %ret146}147 148define i32 @test_ultminus1_sub_add_i32(i32 %x0, i32 %x1) {149; CHECK-LABEL: test_ultminus1_sub_add_i32:150; CHECK: // %bb.0:151; CHECK-NEXT: adds w8, w1, #1152; CHECK-NEXT: add w8, w8, w0153; CHECK-NEXT: csel w0, wzr, w8, ne154; CHECK-NEXT: ret155 %cmp = icmp ult i32 %x1, -1156 %add = add i32 %x0, %x1157 %sub = sub i32 %add, -1158 %ret = select i1 %cmp, i32 0, i32 %sub159 ret i32 %ret160}161 162define i32 @test_ugt7_sub7_add_i32(i32 %x0, i32 %x1) {163; CHECK-LABEL: test_ugt7_sub7_add_i32:164; CHECK: // %bb.0:165; CHECK-NEXT: subs w8, w1, #7166; CHECK-NEXT: add w8, w8, w0167; CHECK-NEXT: csel w0, wzr, w8, hi168; CHECK-NEXT: ret169 %cmp = icmp ugt i32 %x1, 7170 %add = add i32 %x0, %x1171 %sub = sub i32 %add, 7172 %ret = select i1 %cmp, i32 0, i32 %sub173 ret i32 %ret174}175 176define i32 @test_ugt7_sub8_add_i32(i32 %x0, i32 %x1) {177; CHECK-LABEL: test_ugt7_sub8_add_i32:178; CHECK: // %bb.0:179; CHECK-NEXT: subs w8, w1, #8180; CHECK-NEXT: add w8, w8, w0181; CHECK-NEXT: csel w0, wzr, w8, hs182; CHECK-NEXT: ret183 %cmp = icmp ugt i32 %x1, 7184 %add = add i32 %x0, %x1185 %sub = sub i32 %add, 8186 %ret = select i1 %cmp, i32 0, i32 %sub187 ret i32 %ret188}189 190define i32 @test_sle7_sub7_add_i32(i32 %x0, i32 %x1) {191; CHECK-LABEL: test_sle7_sub7_add_i32:192; CHECK: // %bb.0:193; CHECK-NEXT: subs w8, w1, #7194; CHECK-NEXT: add w8, w8, w0195; CHECK-NEXT: csel w0, wzr, w8, le196; CHECK-NEXT: ret197 %cmp = icmp sle i32 %x1, 7198 %add = add i32 %x0, %x1199 %sub = sub i32 %add, 7200 %ret = select i1 %cmp, i32 0, i32 %sub201 ret i32 %ret202}203 204define i32 @test_sle7_sub8_add_i32(i32 %x0, i32 %x1) {205; CHECK-LABEL: test_sle7_sub8_add_i32:206; CHECK: // %bb.0:207; CHECK-NEXT: subs w8, w1, #8208; CHECK-NEXT: add w8, w8, w0209; CHECK-NEXT: csel w0, wzr, w8, lt210; CHECK-NEXT: ret211 %cmp = icmp sle i32 %x1, 7212 %add = add i32 %x0, %x1213 %sub = sub i32 %add, 8214 %ret = select i1 %cmp, i32 0, i32 %sub215 ret i32 %ret216}217 218define i32 @test_slt8_sub8_add_i32(i32 %x0, i32 %x1) {219; CHECK-LABEL: test_slt8_sub8_add_i32:220; CHECK: // %bb.0:221; CHECK-NEXT: subs w8, w1, #8222; CHECK-NEXT: add w8, w8, w0223; CHECK-NEXT: csel w0, wzr, w8, lt224; CHECK-NEXT: ret225 %cmp = icmp slt i32 %x1, 8226 %add = add i32 %x0, %x1227 %sub = sub i32 %add, 8228 %ret = select i1 %cmp, i32 0, i32 %sub229 ret i32 %ret230}231 232define i32 @test_slt8_sub7_add_i32(i32 %x0, i32 %x1) {233; CHECK-LABEL: test_slt8_sub7_add_i32:234; CHECK: // %bb.0:235; CHECK-NEXT: subs w8, w1, #7236; CHECK-NEXT: add w8, w8, w0237; CHECK-NEXT: csel w0, wzr, w8, le238; CHECK-NEXT: ret239 %cmp = icmp slt i32 %x1, 8240 %add = add i32 %x0, %x1241 %sub = sub i32 %add, 7242 %ret = select i1 %cmp, i32 0, i32 %sub243 ret i32 %ret244}245 246define i32 @test_sltminus8_subminus8_add_i32(i32 %x0, i32 %x1) {247; CHECK-LABEL: test_sltminus8_subminus8_add_i32:248; CHECK: // %bb.0:249; CHECK-NEXT: adds w8, w1, #8250; CHECK-NEXT: add w8, w8, w0251; CHECK-NEXT: csel w0, wzr, w8, lt252; CHECK-NEXT: ret253 %cmp = icmp slt i32 %x1, -8254 %add = add i32 %x0, %x1255 %sub = sub i32 %add, -8256 %ret = select i1 %cmp, i32 0, i32 %sub257 ret i32 %ret258}259 260define i32 @test_sgtminus8_subminus8_add_i32(i32 %x0, i32 %x1) {261; CHECK-LABEL: test_sgtminus8_subminus8_add_i32:262; CHECK: // %bb.0:263; CHECK-NEXT: adds w8, w1, #8264; CHECK-NEXT: add w8, w8, w0265; CHECK-NEXT: csel w0, wzr, w8, gt266; CHECK-NEXT: ret267 %cmp = icmp sgt i32 %x1, -8268 %add = add i32 %x0, %x1269 %sub = sub i32 %add, -8270 %ret = select i1 %cmp, i32 0, i32 %sub271 ret i32 %ret272}273 274define i32 @test_sgtminus8_subminus7_add_i32(i32 %x0, i32 %x1) {275; CHECK-LABEL: test_sgtminus8_subminus7_add_i32:276; CHECK: // %bb.0:277; CHECK-NEXT: adds w8, w1, #7278; CHECK-NEXT: add w8, w8, w0279; CHECK-NEXT: csel w0, wzr, w8, ge280; CHECK-NEXT: ret281 %cmp = icmp sgt i32 %x1, -8282 %add = add i32 %x0, %x1283 %sub = sub i32 %add, -7284 %ret = select i1 %cmp, i32 0, i32 %sub285 ret i32 %ret286}287 288define i32 @test_eq0_sub_addcomm_i32(i32 %x0, i32 %x1) {289; CHECK-LABEL: test_eq0_sub_addcomm_i32:290; CHECK: // %bb.0:291; CHECK-NEXT: subs w8, w1, #1292; CHECK-NEXT: add w8, w8, w0293; CHECK-NEXT: csel w0, wzr, w8, lo294; CHECK-NEXT: ret295 %cmp = icmp eq i32 %x1, 0296 %add = add i32 %x1, %x0297 %sub = sub i32 %add, 1298 %ret = select i1 %cmp, i32 0, i32 %sub299 ret i32 %ret300}301 302define i32 @test_eq0_subcomm_add_i32(i32 %x0, i32 %x1) {303; CHECK-LABEL: test_eq0_subcomm_add_i32:304; CHECK: // %bb.0:305; CHECK-NEXT: subs w8, w1, #1306; CHECK-NEXT: add w8, w8, w0307; CHECK-NEXT: csel w0, wzr, w8, lo308; CHECK-NEXT: ret309 %cmp = icmp eq i32 %x1, 0310 %add = add i32 %x0, %x1311 %sub = add i32 -1, %add312 %ret = select i1 %cmp, i32 0, i32 %sub313 ret i32 %ret314}315 316define i32 @test_eq0_multi_use_sub_i32(i32 %x0, i32 %x1) {317; CHECK-LABEL: test_eq0_multi_use_sub_i32:318; CHECK: // %bb.0:319; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill320; CHECK-NEXT: .cfi_def_cfa_offset 16321; CHECK-NEXT: .cfi_offset w19, -8322; CHECK-NEXT: .cfi_offset w30, -16323; CHECK-NEXT: subs w8, w1, #1324; CHECK-NEXT: add w0, w8, w0325; CHECK-NEXT: csel w19, wzr, w0, lo326; CHECK-NEXT: bl use_i32327; CHECK-NEXT: mov w0, w19328; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload329; CHECK-NEXT: ret330 %cmp = icmp eq i32 %x1, 0331 %add = add nuw i32 %x0, %x1332 %sub = sub i32 %add, 1333 tail call void @use_i32(i32 %sub)334 %ret = select i1 %cmp, i32 0, i32 %sub335 ret i32 %ret336}337 338define i32 @test_eq_nonconst_sub_add_i32(i32 %x0, i32 %x1, i32 %x2) {339; CHECK-LABEL: test_eq_nonconst_sub_add_i32:340; CHECK: // %bb.0:341; CHECK-NEXT: subs w8, w1, w2342; CHECK-NEXT: add w8, w8, w0343; CHECK-NEXT: csel w0, wzr, w8, eq344; CHECK-NEXT: ret345 %cmp = icmp eq i32 %x1, %x2346 %add = add nuw i32 %x0, %x1347 %sub = sub i32 %add, %x2348 %ret = select i1 %cmp, i32 0, i32 %sub349 ret i32 %ret350}351 352define i32 @test_ne_nonconst_sub_add_i32(i32 %x0, i32 %x1, i32 %x2) {353; CHECK-LABEL: test_ne_nonconst_sub_add_i32:354; CHECK: // %bb.0:355; CHECK-NEXT: subs w8, w1, w2356; CHECK-NEXT: add w8, w8, w0357; CHECK-NEXT: csel w0, wzr, w8, ne358; CHECK-NEXT: ret359 %cmp = icmp ne i32 %x1, %x2360 %add = add nuw i32 %x0, %x1361 %sub = sub i32 %add, %x2362 %ret = select i1 %cmp, i32 0, i32 %sub363 ret i32 %ret364}365 366define i32 @test_ult_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {367; CHECK-LABEL: test_ult_nonconst_i32:368; CHECK: // %bb.0:369; CHECK-NEXT: subs w8, w1, w2370; CHECK-NEXT: add w8, w8, w0371; CHECK-NEXT: csel w0, wzr, w8, lo372; CHECK-NEXT: ret373 %cmp = icmp ult i32 %x1, %x2374 %add = add i32 %x0, %x1375 %sub = sub i32 %add, %x2376 %ret = select i1 %cmp, i32 0, i32 %sub377 ret i32 %ret378}379 380define i32 @test_ule_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {381; CHECK-LABEL: test_ule_nonconst_i32:382; CHECK: // %bb.0:383; CHECK-NEXT: subs w8, w1, w2384; CHECK-NEXT: add w8, w8, w0385; CHECK-NEXT: csel w0, wzr, w8, ls386; CHECK-NEXT: ret387 %cmp = icmp ule i32 %x1, %x2388 %add = add i32 %x0, %x1389 %sub = sub i32 %add, %x2390 %ret = select i1 %cmp, i32 0, i32 %sub391 ret i32 %ret392}393 394define i32 @test_ugt_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {395; CHECK-LABEL: test_ugt_nonconst_i32:396; CHECK: // %bb.0:397; CHECK-NEXT: subs w8, w1, w2398; CHECK-NEXT: add w8, w8, w0399; CHECK-NEXT: csel w0, wzr, w8, hi400; CHECK-NEXT: ret401 %cmp = icmp ugt i32 %x1, %x2402 %add = add i32 %x0, %x1403 %sub = sub i32 %add, %x2404 %ret = select i1 %cmp, i32 0, i32 %sub405 ret i32 %ret406}407 408define i32 @test_uge_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {409; CHECK-LABEL: test_uge_nonconst_i32:410; CHECK: // %bb.0:411; CHECK-NEXT: subs w8, w1, w2412; CHECK-NEXT: add w8, w8, w0413; CHECK-NEXT: csel w0, wzr, w8, hs414; CHECK-NEXT: ret415 %cmp = icmp uge i32 %x1, %x2416 %add = add i32 %x0, %x1417 %sub = sub i32 %add, %x2418 %ret = select i1 %cmp, i32 0, i32 %sub419 ret i32 %ret420}421 422define i32 @test_slt_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {423; CHECK-LABEL: test_slt_nonconst_i32:424; CHECK: // %bb.0:425; CHECK-NEXT: subs w8, w1, w2426; CHECK-NEXT: add w8, w8, w0427; CHECK-NEXT: csel w0, wzr, w8, lt428; CHECK-NEXT: ret429 %cmp = icmp slt i32 %x1, %x2430 %add = add i32 %x0, %x1431 %sub = sub i32 %add, %x2432 %ret = select i1 %cmp, i32 0, i32 %sub433 ret i32 %ret434}435 436define i32 @test_sle_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {437; CHECK-LABEL: test_sle_nonconst_i32:438; CHECK: // %bb.0:439; CHECK-NEXT: subs w8, w1, w2440; CHECK-NEXT: add w8, w8, w0441; CHECK-NEXT: csel w0, wzr, w8, le442; CHECK-NEXT: ret443 %cmp = icmp sle i32 %x1, %x2444 %add = add i32 %x0, %x1445 %sub = sub i32 %add, %x2446 %ret = select i1 %cmp, i32 0, i32 %sub447 ret i32 %ret448}449 450define i32 @test_sgt_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {451; CHECK-LABEL: test_sgt_nonconst_i32:452; CHECK: // %bb.0:453; CHECK-NEXT: subs w8, w1, w2454; CHECK-NEXT: add w8, w8, w0455; CHECK-NEXT: csel w0, wzr, w8, gt456; CHECK-NEXT: ret457 %cmp = icmp sgt i32 %x1, %x2458 %add = add i32 %x0, %x1459 %sub = sub i32 %add, %x2460 %ret = select i1 %cmp, i32 0, i32 %sub461 ret i32 %ret462}463 464define i32 @test_sge_nonconst_i32(i32 %x0, i32 %x1, i32 %x2) {465; CHECK-LABEL: test_sge_nonconst_i32:466; CHECK: // %bb.0:467; CHECK-NEXT: subs w8, w1, w2468; CHECK-NEXT: add w8, w8, w0469; CHECK-NEXT: csel w0, wzr, w8, ge470; CHECK-NEXT: ret471 %cmp = icmp sge i32 %x1, %x2472 %add = add i32 %x0, %x1473 %sub = sub i32 %add, %x2474 %ret = select i1 %cmp, i32 0, i32 %sub475 ret i32 %ret476}477 478define i64 @test_ult_nonconst_i64(i64 %x0, i64 %x1, i64 %x2) {479; CHECK-LABEL: test_ult_nonconst_i64:480; CHECK: // %bb.0:481; CHECK-NEXT: subs x8, x1, x2482; CHECK-NEXT: add x8, x8, x0483; CHECK-NEXT: csel x0, xzr, x8, lo484; CHECK-NEXT: ret485 %cmp = icmp ult i64 %x1, %x2486 %add = add i64 %x0, %x1487 %sub = sub i64 %add, %x2488 %ret = select i1 %cmp, i64 0, i64 %sub489 ret i64 %ret490}491 492define i32 @test_eq_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {493; CHECK-LABEL: test_eq_nonconst_sub_add_comm_i32:494; CHECK: // %bb.0:495; CHECK-NEXT: subs w8, w1, w2496; CHECK-NEXT: add w8, w8, w0497; CHECK-NEXT: csel w0, wzr, w8, eq498; CHECK-NEXT: ret499 %cmp = icmp eq i32 %x2, %x1500 %add = add nuw i32 %x0, %x1501 %sub = sub i32 %add, %x2502 %ret = select i1 %cmp, i32 0, i32 %sub503 ret i32 %ret504}505 506define i32 @test_ne_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {507; CHECK-LABEL: test_ne_nonconst_sub_add_comm_i32:508; CHECK: // %bb.0:509; CHECK-NEXT: subs w8, w1, w2510; CHECK-NEXT: add w8, w8, w0511; CHECK-NEXT: csel w0, wzr, w8, ne512; CHECK-NEXT: ret513 %cmp = icmp ne i32 %x2, %x1514 %add = add nuw i32 %x0, %x1515 %sub = sub i32 %add, %x2516 %ret = select i1 %cmp, i32 0, i32 %sub517 ret i32 %ret518}519 520define i32 @test_ult_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {521; CHECK-LABEL: test_ult_nonconst_sub_add_comm_i32:522; CHECK: // %bb.0:523; CHECK-NEXT: subs w8, w1, w2524; CHECK-NEXT: add w8, w8, w0525; CHECK-NEXT: csel w0, wzr, w8, hi526; CHECK-NEXT: ret527 %cmp = icmp ult i32 %x2, %x1528 %add = add nuw i32 %x0, %x1529 %sub = sub i32 %add, %x2530 %ret = select i1 %cmp, i32 0, i32 %sub531 ret i32 %ret532}533 534define i32 @test_ule_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {535; CHECK-LABEL: test_ule_nonconst_sub_add_comm_i32:536; CHECK: // %bb.0:537; CHECK-NEXT: subs w8, w1, w2538; CHECK-NEXT: add w8, w8, w0539; CHECK-NEXT: csel w0, wzr, w8, hs540; CHECK-NEXT: ret541 %cmp = icmp ule i32 %x2, %x1542 %add = add nuw i32 %x0, %x1543 %sub = sub i32 %add, %x2544 %ret = select i1 %cmp, i32 0, i32 %sub545 ret i32 %ret546}547 548define i32 @test_ugt_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {549; CHECK-LABEL: test_ugt_nonconst_sub_add_comm_i32:550; CHECK: // %bb.0:551; CHECK-NEXT: subs w8, w1, w2552; CHECK-NEXT: add w8, w8, w0553; CHECK-NEXT: csel w0, wzr, w8, lo554; CHECK-NEXT: ret555 %cmp = icmp ugt i32 %x2, %x1556 %add = add nuw i32 %x0, %x1557 %sub = sub i32 %add, %x2558 %ret = select i1 %cmp, i32 0, i32 %sub559 ret i32 %ret560}561 562define i32 @test_uge_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {563; CHECK-LABEL: test_uge_nonconst_sub_add_comm_i32:564; CHECK: // %bb.0:565; CHECK-NEXT: subs w8, w1, w2566; CHECK-NEXT: add w8, w8, w0567; CHECK-NEXT: csel w0, wzr, w8, ls568; CHECK-NEXT: ret569 %cmp = icmp uge i32 %x2, %x1570 %add = add nuw i32 %x0, %x1571 %sub = sub i32 %add, %x2572 %ret = select i1 %cmp, i32 0, i32 %sub573 ret i32 %ret574}575 576define i32 @test_slt_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {577; CHECK-LABEL: test_slt_nonconst_sub_add_comm_i32:578; CHECK: // %bb.0:579; CHECK-NEXT: subs w8, w1, w2580; CHECK-NEXT: add w8, w8, w0581; CHECK-NEXT: csel w0, wzr, w8, gt582; CHECK-NEXT: ret583 %cmp = icmp slt i32 %x2, %x1584 %add = add nuw i32 %x0, %x1585 %sub = sub i32 %add, %x2586 %ret = select i1 %cmp, i32 0, i32 %sub587 ret i32 %ret588}589 590define i32 @test_sle_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {591; CHECK-LABEL: test_sle_nonconst_sub_add_comm_i32:592; CHECK: // %bb.0:593; CHECK-NEXT: subs w8, w1, w2594; CHECK-NEXT: add w8, w8, w0595; CHECK-NEXT: csel w0, wzr, w8, ge596; CHECK-NEXT: ret597 %cmp = icmp sle i32 %x2, %x1598 %add = add nuw i32 %x0, %x1599 %sub = sub i32 %add, %x2600 %ret = select i1 %cmp, i32 0, i32 %sub601 ret i32 %ret602}603 604define i32 @test_sgt_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {605; CHECK-LABEL: test_sgt_nonconst_sub_add_comm_i32:606; CHECK: // %bb.0:607; CHECK-NEXT: subs w8, w1, w2608; CHECK-NEXT: add w8, w8, w0609; CHECK-NEXT: csel w0, wzr, w8, lt610; CHECK-NEXT: ret611 %cmp = icmp sgt i32 %x2, %x1612 %add = add nuw i32 %x0, %x1613 %sub = sub i32 %add, %x2614 %ret = select i1 %cmp, i32 0, i32 %sub615 ret i32 %ret616}617 618define i32 @test_sge_nonconst_sub_add_comm_i32(i32 %x0, i32 %x1, i32 %x2) {619; CHECK-LABEL: test_sge_nonconst_sub_add_comm_i32:620; CHECK: // %bb.0:621; CHECK-NEXT: subs w8, w1, w2622; CHECK-NEXT: add w8, w8, w0623; CHECK-NEXT: csel w0, wzr, w8, le624; CHECK-NEXT: ret625 %cmp = icmp sge i32 %x2, %x1626 %add = add nuw i32 %x0, %x1627 %sub = sub i32 %add, %x2628 %ret = select i1 %cmp, i32 0, i32 %sub629 ret i32 %ret630}631 632; Negative test633define i32 @test_eq0_multi_use_cmp_i32(i32 %x0, i32 %x1) {634; CHECK-LABEL: test_eq0_multi_use_cmp_i32:635; CHECK: // %bb.0:636; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill637; CHECK-NEXT: .cfi_def_cfa_offset 16638; CHECK-NEXT: .cfi_offset w19, -8639; CHECK-NEXT: .cfi_offset w30, -16640; CHECK-NEXT: add w8, w0, w1641; CHECK-NEXT: cmp w1, #0642; CHECK-NEXT: sub w8, w8, #1643; CHECK-NEXT: cset w0, eq644; CHECK-NEXT: csel w19, wzr, w8, eq645; CHECK-NEXT: bl use_i1646; CHECK-NEXT: mov w0, w19647; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload648; CHECK-NEXT: ret649 %cmp = icmp eq i32 %x1, 0650 tail call void @use_i1(i1 %cmp)651 %add = add nuw i32 %x0, %x1652 %sub = sub i32 %add, 1653 %ret = select i1 %cmp, i32 0, i32 %sub654 ret i32 %ret655}656 657; Negative test658define i32 @test_eq0_multi_use_add_i32(i32 %x0, i32 %x1) {659; CHECK-LABEL: test_eq0_multi_use_add_i32:660; CHECK: // %bb.0:661; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill662; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill663; CHECK-NEXT: .cfi_def_cfa_offset 32664; CHECK-NEXT: .cfi_offset w19, -8665; CHECK-NEXT: .cfi_offset w20, -16666; CHECK-NEXT: .cfi_offset w30, -32667; CHECK-NEXT: add w20, w0, w1668; CHECK-NEXT: mov w19, w1669; CHECK-NEXT: mov w0, w20670; CHECK-NEXT: bl use_i32671; CHECK-NEXT: sub w8, w20, #1672; CHECK-NEXT: cmp w19, #0673; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload674; CHECK-NEXT: csel w0, wzr, w8, eq675; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload676; CHECK-NEXT: ret677 %cmp = icmp eq i32 %x1, 0678 %add = add nuw i32 %x0, %x1679 tail call void @use_i32(i32 %add)680 %sub = sub i32 %add, 1681 %ret = select i1 %cmp, i32 0, i32 %sub682 ret i32 %ret683}684 685; Negative test686define i32 @test_eq1_sub_add_i32(i32 %x0, i32 %x1) {687; CHECK-LABEL: test_eq1_sub_add_i32:688; CHECK: // %bb.0:689; CHECK-NEXT: add w8, w0, w1690; CHECK-NEXT: cmp w1, #1691; CHECK-NEXT: sub w8, w8, #2692; CHECK-NEXT: csel w0, wzr, w8, eq693; CHECK-NEXT: ret694 %cmp = icmp eq i32 %x1, 1695 %add = add i32 %x0, %x1696 %sub = sub i32 %add, 2697 %ret = select i1 %cmp, i32 0, i32 %sub698 ret i32 %ret699}700 701; Negative test702define i32 @test_ugtsmax_sub_add_i32(i32 %x0, i32 %x1) {703; CHECK-LABEL: test_ugtsmax_sub_add_i32:704; CHECK: // %bb.0:705; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000706; CHECK-NEXT: add w9, w0, w1707; CHECK-NEXT: cmp w1, #0708; CHECK-NEXT: add w8, w9, w8709; CHECK-NEXT: csel w0, wzr, w8, mi710; CHECK-NEXT: ret711 %cmp = icmp ugt i32 %x1, 2147483647712 %add = add i32 %x0, %x1713 %sub = sub i32 %add, 2147483648714 %ret = select i1 %cmp, i32 0, i32 %sub715 ret i32 %ret716}717 718; Negative test719define i32 @test_eq_const_mismatch_i32(i32 %x0, i32 %x1) {720; CHECK-LABEL: test_eq_const_mismatch_i32:721; CHECK: // %bb.0:722; CHECK-NEXT: add w8, w0, w1723; CHECK-NEXT: cmp w1, #0724; CHECK-NEXT: sub w8, w8, #2725; CHECK-NEXT: csel w0, wzr, w8, eq726; CHECK-NEXT: ret727 %cmp = icmp eq i32 %x1, 0728 %add = add i32 %x0, %x1729 %sub = sub i32 %add, 2730 %ret = select i1 %cmp, i32 0, i32 %sub731 ret i32 %ret732}733 734; Negative test735define i32 @test_ne_const_mismatch_i32(i32 %x0, i32 %x1) {736; CHECK-LABEL: test_ne_const_mismatch_i32:737; CHECK: // %bb.0:738; CHECK-NEXT: add w8, w0, w1739; CHECK-NEXT: cmp w1, #0740; CHECK-NEXT: sub w8, w8, #2741; CHECK-NEXT: csel w0, w8, wzr, ne742; CHECK-NEXT: ret743 %cmp = icmp ne i32 %x1, 0744 %add = add i32 %x0, %x1745 %sub = sub i32 %add, 2746 %ret = select i1 %cmp, i32 %sub, i32 0747 ret i32 %ret748}749 750; Negative test751define i32 @test_ult7_const_mismatch_i32(i32 %x0, i32 %x1) {752; CHECK-LABEL: test_ult7_const_mismatch_i32:753; CHECK: // %bb.0:754; CHECK-NEXT: add w8, w0, w1755; CHECK-NEXT: cmp w1, #7756; CHECK-NEXT: sub w8, w8, #8757; CHECK-NEXT: csel w0, wzr, w8, lo758; CHECK-NEXT: ret759 %cmp = icmp ult i32 %x1, 7760 %add = add i32 %x0, %x1761 %sub = sub i32 %add, 8762 %ret = select i1 %cmp, i32 0, i32 %sub763 ret i32 %ret764}765 766; Negative test767define i32 @test_ule7_const_mismatch_i32(i32 %x0, i32 %x1) {768; CHECK-LABEL: test_ule7_const_mismatch_i32:769; CHECK: // %bb.0:770; CHECK-NEXT: add w8, w0, w1771; CHECK-NEXT: cmp w1, #8772; CHECK-NEXT: sub w8, w8, #6773; CHECK-NEXT: csel w0, wzr, w8, lo774; CHECK-NEXT: ret775 %cmp = icmp ule i32 %x1, 7776 %add = add i32 %x0, %x1777 %sub = sub i32 %add, 6778 %ret = select i1 %cmp, i32 0, i32 %sub779 ret i32 %ret780}781 782; Negative test783define i32 @test_ugt7_const_mismatch_i32(i32 %x0, i32 %x1) {784; CHECK-LABEL: test_ugt7_const_mismatch_i32:785; CHECK: // %bb.0:786; CHECK-NEXT: add w8, w0, w1787; CHECK-NEXT: cmp w1, #7788; CHECK-NEXT: sub w8, w8, #6789; CHECK-NEXT: csel w0, wzr, w8, hi790; CHECK-NEXT: ret791 %cmp = icmp ugt i32 %x1, 7792 %add = add i32 %x0, %x1793 %sub = sub i32 %add, 6794 %ret = select i1 %cmp, i32 0, i32 %sub795 ret i32 %ret796}797 798; Negative test799define i32 @test_uge7_const_mismatch_i32(i32 %x0, i32 %x1) {800; CHECK-LABEL: test_uge7_const_mismatch_i32:801; CHECK: // %bb.0:802; CHECK-NEXT: add w8, w0, w1803; CHECK-NEXT: cmp w1, #6804; CHECK-NEXT: sub w8, w8, #8805; CHECK-NEXT: csel w0, wzr, w8, hi806; CHECK-NEXT: ret807 %cmp = icmp uge i32 %x1, 7808 %add = add i32 %x0, %x1809 %sub = sub i32 %add, 8810 %ret = select i1 %cmp, i32 0, i32 %sub811 ret i32 %ret812}813 814; Negative test815define i32 @test_slt7_const_mismatch_i32(i32 %x0, i32 %x1) {816; CHECK-LABEL: test_slt7_const_mismatch_i32:817; CHECK: // %bb.0:818; CHECK-NEXT: add w8, w0, w1819; CHECK-NEXT: cmp w1, #7820; CHECK-NEXT: sub w8, w8, #8821; CHECK-NEXT: csel w0, wzr, w8, lt822; CHECK-NEXT: ret823 %cmp = icmp slt i32 %x1, 7824 %add = add i32 %x0, %x1825 %sub = sub i32 %add, 8826 %ret = select i1 %cmp, i32 0, i32 %sub827 ret i32 %ret828}829 830; Negative test831define i32 @test_sle7_const_mismatch_i32(i32 %x0, i32 %x1) {832; CHECK-LABEL: test_sle7_const_mismatch_i32:833; CHECK: // %bb.0:834; CHECK-NEXT: add w8, w0, w1835; CHECK-NEXT: cmp w1, #8836; CHECK-NEXT: sub w8, w8, #6837; CHECK-NEXT: csel w0, wzr, w8, lt838; CHECK-NEXT: ret839 %cmp = icmp sle i32 %x1, 7840 %add = add i32 %x0, %x1841 %sub = sub i32 %add, 6842 %ret = select i1 %cmp, i32 0, i32 %sub843 ret i32 %ret844}845 846; Negative test847define i32 @test_sgt7_const_mismatch_i32(i32 %x0, i32 %x1) {848; CHECK-LABEL: test_sgt7_const_mismatch_i32:849; CHECK: // %bb.0:850; CHECK-NEXT: add w8, w0, w1851; CHECK-NEXT: cmp w1, #7852; CHECK-NEXT: sub w8, w8, #6853; CHECK-NEXT: csel w0, wzr, w8, gt854; CHECK-NEXT: ret855 %cmp = icmp sgt i32 %x1, 7856 %add = add i32 %x0, %x1857 %sub = sub i32 %add, 6858 %ret = select i1 %cmp, i32 0, i32 %sub859 ret i32 %ret860}861 862; Negative test863define i32 @test_sge7_const_mismatch_i32(i32 %x0, i32 %x1) {864; CHECK-LABEL: test_sge7_const_mismatch_i32:865; CHECK: // %bb.0:866; CHECK-NEXT: add w8, w0, w1867; CHECK-NEXT: cmp w1, #6868; CHECK-NEXT: sub w8, w8, #8869; CHECK-NEXT: csel w0, wzr, w8, gt870; CHECK-NEXT: ret871 %cmp = icmp sge i32 %x1, 7872 %add = add i32 %x0, %x1873 %sub = sub i32 %add, 8874 %ret = select i1 %cmp, i32 0, i32 %sub875 ret i32 %ret876}877 878; Negative test879define i32 @test_unrelated_add_i32(i32 %x0, i32 %x1, i32 %x2) {880; CHECK-LABEL: test_unrelated_add_i32:881; CHECK: // %bb.0:882; CHECK-NEXT: add w8, w0, w2883; CHECK-NEXT: cmp w1, #0884; CHECK-NEXT: sub w8, w8, #1885; CHECK-NEXT: csel w0, wzr, w8, eq886; CHECK-NEXT: ret887 %cmp = icmp eq i32 %x1, 0888 %add = add nuw i32 %x0, %x2889 %sub = sub i32 %add, 1890 %ret = select i1 %cmp, i32 0, i32 %sub891 ret i32 %ret892}893 894; Negative test895define i16 @test_eq0_sub_add_i16(i16 %x0, i16 %x1) {896; CHECK-LABEL: test_eq0_sub_add_i16:897; CHECK: // %bb.0:898; CHECK-NEXT: add w8, w0, w1899; CHECK-NEXT: tst w1, #0xffff900; CHECK-NEXT: sub w8, w8, #1901; CHECK-NEXT: csel w0, wzr, w8, eq902; CHECK-NEXT: ret903 %cmp = icmp eq i16 %x1, 0904 %add = add nuw i16 %x0, %x1905 %sub = sub i16 %add, 1906 %ret = select i1 %cmp, i16 0, i16 %sub907 ret i16 %ret908}909 910; Negative test911define i8 @test_eq_nonconst_sub_add_i8(i8 %x0, i8 %x1, i8 %x2) {912; CHECK-LABEL: test_eq_nonconst_sub_add_i8:913; CHECK: // %bb.0:914; CHECK-NEXT: and w8, w1, #0xff915; CHECK-NEXT: add w9, w0, w1916; CHECK-NEXT: sub w9, w9, w2917; CHECK-NEXT: cmp w8, w2, uxtb918; CHECK-NEXT: csel w0, wzr, w9, eq919; CHECK-NEXT: ret920 %cmp = icmp eq i8 %x1, %x2921 %add = add nuw i8 %x0, %x1922 %sub = sub i8 %add, %x2923 %ret = select i1 %cmp, i8 0, i8 %sub924 ret i8 %ret925}926 927; Negative test928define i16 @test_eq_nonconst_sub_add_i16(i16 %x0, i16 %x1, i16 %x2) {929; CHECK-LABEL: test_eq_nonconst_sub_add_i16:930; CHECK: // %bb.0:931; CHECK-NEXT: and w8, w1, #0xffff932; CHECK-NEXT: add w9, w0, w1933; CHECK-NEXT: sub w9, w9, w2934; CHECK-NEXT: cmp w8, w2, uxth935; CHECK-NEXT: csel w0, wzr, w9, eq936; CHECK-NEXT: ret937 %cmp = icmp eq i16 %x1, %x2938 %add = add nuw i16 %x0, %x1939 %sub = sub i16 %add, %x2940 %ret = select i1 %cmp, i16 0, i16 %sub941 ret i16 %ret942}943 944; Negative test945define i32 @test_ule_unsigned_overflow(i32 %x0, i32 %x1) {946; CHECK-LABEL: test_ule_unsigned_overflow:947; CHECK: // %bb.0:948; CHECK-NEXT: mov w0, wzr949; CHECK-NEXT: ret950 %cmp = icmp ule i32 %x1, -1951 %add = add i32 %x0, %x1952 %sub = sub i32 %add, 0953 %ret = select i1 %cmp, i32 0, i32 %sub954 ret i32 %ret955}956 957; Negative test958define i32 @test_ugt_unsigned_overflow(i32 %x0, i32 %x1) {959; CHECK-LABEL: test_ugt_unsigned_overflow:960; CHECK: // %bb.0:961; CHECK-NEXT: add w0, w0, w1962; CHECK-NEXT: ret963 %cmp = icmp ugt i32 %x1, -1964 %add = add i32 %x0, %x1965 %sub = sub i32 %add, 0966 %ret = select i1 %cmp, i32 0, i32 %sub967 ret i32 %ret968}969 970; Negative test971define i32 @test_ult_unsigned_overflow(i32 %x0, i32 %x1) {972; CHECK-LABEL: test_ult_unsigned_overflow:973; CHECK: // %bb.0:974; CHECK-NEXT: add w8, w0, w1975; CHECK-NEXT: add w0, w8, #1976; CHECK-NEXT: ret977 %cmp = icmp ult i32 %x1, 0978 %add = add i32 %x0, %x1979 %sub = sub i32 %add, -1980 %ret = select i1 %cmp, i32 0, i32 %sub981 ret i32 %ret982}983 984; Negative test985define i32 @test_uge_unsigned_overflow(i32 %x0, i32 %x1) {986; CHECK-LABEL: test_uge_unsigned_overflow:987; CHECK: // %bb.0:988; CHECK-NEXT: mov w0, wzr989; CHECK-NEXT: ret990 %cmp = icmp uge i32 %x1, 0991 %add = add i32 %x0, %x1992 %sub = sub i32 %add, -1993 %ret = select i1 %cmp, i32 0, i32 %sub994 ret i32 %ret995}996 997; Negative test998define i32 @test_slt_signed_overflow(i32 %x0, i32 %x1) {999; CHECK-LABEL: test_slt_signed_overflow:1000; CHECK: // %bb.0:1001; CHECK-NEXT: mov w8, #-2147483647 // =0x800000011002; CHECK-NEXT: add w9, w0, w11003; CHECK-NEXT: add w0, w9, w81004; CHECK-NEXT: ret1005 %cmp = icmp slt i32 %x1, 21474836481006 %add = add i32 %x0, %x11007 %sub = sub i32 %add, 21474836471008 %ret = select i1 %cmp, i32 0, i32 %sub1009 ret i32 %ret1010}1011 1012; Negative test1013define i32 @test_sle_signed_overflow(i32 %x0, i32 %x1) {1014; CHECK-LABEL: test_sle_signed_overflow:1015; CHECK: // %bb.0:1016; CHECK-NEXT: mov w0, wzr1017; CHECK-NEXT: ret1018 %cmp = icmp sle i32 %x1, 21474836471019 %add = add i32 %x0, %x11020 %sub = sub i32 %add, 21474836481021 %ret = select i1 %cmp, i32 0, i32 %sub1022 ret i32 %ret1023}1024 1025; Negative test1026define i32 @test_sgt_signed_overflow(i32 %x0, i32 %x1) {1027; CHECK-LABEL: test_sgt_signed_overflow:1028; CHECK: // %bb.0:1029; CHECK-NEXT: mov w8, #-2147483648 // =0x800000001030; CHECK-NEXT: add w9, w0, w11031; CHECK-NEXT: add w0, w9, w81032; CHECK-NEXT: ret1033 %cmp = icmp sgt i32 %x1, 21474836471034 %add = add i32 %x0, %x11035 %sub = sub i32 %add, 21474836481036 %ret = select i1 %cmp, i32 0, i32 %sub1037 ret i32 %ret1038}1039 1040; Negative test1041define i32 @test_sge_signed_overflow(i32 %x0, i32 %x1) {1042; CHECK-LABEL: test_sge_signed_overflow:1043; CHECK: // %bb.0:1044; CHECK-NEXT: mov w0, wzr1045; CHECK-NEXT: ret1046 %cmp = icmp sge i32 %x1, 21474836481047 %add = add i32 %x0, %x11048 %sub = sub i32 %add, 21474836471049 %ret = select i1 %cmp, i32 0, i32 %sub1050 ret i32 %ret1051}1052 1053; Negative test1054define i32 @test_eq0_bitwidth_mismatch(i32 %x0, i32 %x1) {1055; CHECK-LABEL: test_eq0_bitwidth_mismatch:1056; CHECK: // %bb.0:1057; CHECK-NEXT: add w8, w0, w11058; CHECK-NEXT: tst w1, #0xffff1059; CHECK-NEXT: sub w8, w8, #11060; CHECK-NEXT: csel w0, wzr, w8, eq1061; CHECK-NEXT: ret1062 %x1t = trunc i32 %x1 to i161063 %cmp = icmp eq i16 %x1t, 01064 %add = add i32 %x0, %x11065 %sub = sub i32 %add, 11066 %ret = select i1 %cmp, i32 0, i32 %sub1067 ret i32 %ret1068}1069 1070; Negative test1071define i32 @test_eq0_bitwidth_mismatch_2(i32 %x0, i64 %x1) {1072; CHECK-LABEL: test_eq0_bitwidth_mismatch_2:1073; CHECK: // %bb.0:1074; CHECK-NEXT: add w8, w0, w11075; CHECK-NEXT: cmp x1, #01076; CHECK-NEXT: sub w8, w8, #11077; CHECK-NEXT: csel w0, wzr, w8, eq1078; CHECK-NEXT: ret1079 %x1t = trunc i64 %x1 to i321080 %cmp = icmp eq i64 %x1, 01081 %add = add i32 %x0, %x1t1082 %sub = sub i32 %add, 11083 %ret = select i1 %cmp, i32 0, i32 %sub1084 ret i32 %ret1085}1086 1087; Negative test1088define i32 @test_ult_nonconst_op_mismatch_i32(i32 %x0, i32 %x1, i32 %x2) {1089; CHECK-LABEL: test_ult_nonconst_op_mismatch_i32:1090; CHECK: // %bb.0:1091; CHECK-NEXT: add w8, w0, w11092; CHECK-NEXT: cmp w1, w21093; CHECK-NEXT: add w8, w8, w21094; CHECK-NEXT: csel w0, wzr, w8, lo1095; CHECK-NEXT: ret1096 %cmp = icmp ult i32 %x1, %x21097 %add = add i32 %x0, %x11098 %sub = add i32 %add, %x21099 %ret = select i1 %cmp, i32 0, i32 %sub1100 ret i32 %ret1101}1102 1103; Negative test1104define i32 @test_ult_nonconst_unrelated_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {1105; CHECK-LABEL: test_ult_nonconst_unrelated_i32:1106; CHECK: // %bb.0:1107; CHECK-NEXT: add w8, w0, w11108; CHECK-NEXT: cmp w1, w21109; CHECK-NEXT: sub w8, w8, w31110; CHECK-NEXT: csel w0, wzr, w8, lo1111; CHECK-NEXT: ret1112 %cmp = icmp ult i32 %x1, %x21113 %add = add i32 %x0, %x11114 %sub = sub i32 %add, %x31115 %ret = select i1 %cmp, i32 0, i32 %sub1116 ret i32 %ret1117}1118 1119; Negative test1120define i32 @test_ult_nonconst_unrelated_2_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {1121; CHECK-LABEL: test_ult_nonconst_unrelated_2_i32:1122; CHECK: // %bb.0:1123; CHECK-NEXT: add w8, w0, w11124; CHECK-NEXT: cmp w2, w11125; CHECK-NEXT: sub w8, w8, w31126; CHECK-NEXT: csel w0, wzr, w8, lo1127; CHECK-NEXT: ret1128 %cmp = icmp ult i32 %x2, %x11129 %add = add i32 %x0, %x11130 %sub = sub i32 %add, %x31131 %ret = select i1 %cmp, i32 0, i32 %sub1132 ret i32 %ret1133}1134