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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s3 4define i32 @eq_i32(i32 %x) {5; CHECK-LABEL: eq_i32:6; CHECK: // %bb.0:7; CHECK-NEXT: mov w8, #-2097152 // =0xffe000008; CHECK-NEXT: subs w8, w8, w09; CHECK-NEXT: csel w0, w0, w8, eq10; CHECK-NEXT: ret11 %cmp = icmp eq i32 %x, -209715212 %sub = sub i32 -2097152, %x13 %retval.0 = select i1 %cmp, i32 %x, i32 %sub14 ret i32 %retval.015}16 17define i32 @ne_i32(i32 %x) {18; CHECK-LABEL: ne_i32:19; CHECK: // %bb.0:20; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000021; CHECK-NEXT: subs w8, w8, w022; CHECK-NEXT: csel w0, w0, w8, ne23; CHECK-NEXT: ret24 %cmp = icmp ne i32 %x, -209715225 %sub = sub i32 -2097152, %x26 %retval.0 = select i1 %cmp, i32 %x, i32 %sub27 ret i32 %retval.028}29 30define i32 @sgt_i32(i32 %x) {31; CHECK-LABEL: sgt_i32:32; CHECK: // %bb.0:33; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000034; CHECK-NEXT: subs w8, w8, w035; CHECK-NEXT: csel w0, w0, w8, lt36; CHECK-NEXT: ret37 %cmp = icmp sgt i32 %x, -209715238 %sub = sub i32 -2097152, %x39 %retval.0 = select i1 %cmp, i32 %x, i32 %sub40 ret i32 %retval.041}42 43define i32 @sge_i32(i32 %x) {44; CHECK-LABEL: sge_i32:45; CHECK: // %bb.0:46; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000047; CHECK-NEXT: subs w8, w8, w048; CHECK-NEXT: csel w0, w0, w8, le49; CHECK-NEXT: ret50 %cmp = icmp sge i32 %x, -209715251 %sub = sub i32 -2097152, %x52 %retval.0 = select i1 %cmp, i32 %x, i32 %sub53 ret i32 %retval.054}55 56define i32 @slt_i32(i32 %x) {57; CHECK-LABEL: slt_i32:58; CHECK: // %bb.0:59; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000060; CHECK-NEXT: subs w8, w8, w061; CHECK-NEXT: csel w0, w0, w8, gt62; CHECK-NEXT: ret63 %cmp = icmp slt i32 %x, -209715264 %sub = sub i32 -2097152, %x65 %retval.0 = select i1 %cmp, i32 %x, i32 %sub66 ret i32 %retval.067}68 69define i32 @sle_i32(i32 %x) {70; CHECK-LABEL: sle_i32:71; CHECK: // %bb.0:72; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000073; CHECK-NEXT: subs w8, w8, w074; CHECK-NEXT: csel w0, w0, w8, ge75; CHECK-NEXT: ret76 %cmp = icmp sle i32 %x, -209715277 %sub = sub i32 -2097152, %x78 %retval.0 = select i1 %cmp, i32 %x, i32 %sub79 ret i32 %retval.080}81 82define i32 @ugt_i32(i32 %x) {83; CHECK-LABEL: ugt_i32:84; CHECK: // %bb.0:85; CHECK-NEXT: mov w8, #-2097152 // =0xffe0000086; CHECK-NEXT: subs w8, w8, w087; CHECK-NEXT: csel w0, w0, w8, lo88; CHECK-NEXT: ret89 %cmp = icmp ugt i32 %x, -209715290 %sub = sub i32 -2097152, %x91 %retval.0 = select i1 %cmp, i32 %x, i32 %sub92 ret i32 %retval.093}94 95define i32 @uge_i32(i32 %x) {96; CHECK-LABEL: uge_i32:97; CHECK: // %bb.0:98; CHECK-NEXT: lsr w9, w0, #2199; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000100; CHECK-NEXT: sub w8, w8, w0101; CHECK-NEXT: cmp w9, #2046102; CHECK-NEXT: csel w0, w0, w8, hi103; CHECK-NEXT: ret104 %cmp = icmp uge i32 %x, -2097152105 %sub = sub i32 -2097152, %x106 %retval.0 = select i1 %cmp, i32 %x, i32 %sub107 ret i32 %retval.0108}109 110define i32 @ult_i32(i32 %x) {111; CHECK-LABEL: ult_i32:112; CHECK: // %bb.0:113; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000114; CHECK-NEXT: subs w8, w8, w0115; CHECK-NEXT: csel w0, w0, w8, hi116; CHECK-NEXT: ret117 %cmp = icmp ult i32 %x, -2097152118 %sub = sub i32 -2097152, %x119 %retval.0 = select i1 %cmp, i32 %x, i32 %sub120 ret i32 %retval.0121}122 123define i32 @ule_i32(i32 %x) {124; CHECK-LABEL: ule_i32:125; CHECK: // %bb.0:126; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000127; CHECK-NEXT: subs w8, w8, w0128; CHECK-NEXT: csel w0, w0, w8, hs129; CHECK-NEXT: ret130 %cmp = icmp ule i32 %x, -2097152131 %sub = sub i32 -2097152, %x132 %retval.0 = select i1 %cmp, i32 %x, i32 %sub133 ret i32 %retval.0134}135 136 137define i64 @eq_i64(i64 %x) {138; CHECK-LABEL: eq_i64:139; CHECK: // %bb.0:140; CHECK-NEXT: mov w8, #100 // =0x64141; CHECK-NEXT: subs x8, x8, x0142; CHECK-NEXT: csel x0, x0, x8, eq143; CHECK-NEXT: ret144 %cmp = icmp eq i64 %x, 100145 %sub = sub i64 100, %x146 %retval.0 = select i1 %cmp, i64 %x, i64 %sub147 ret i64 %retval.0148}149 150define i64 @ne_i64(i64 %x) {151; CHECK-LABEL: ne_i64:152; CHECK: // %bb.0:153; CHECK-NEXT: mov w8, #100 // =0x64154; CHECK-NEXT: subs x8, x8, x0155; CHECK-NEXT: csel x0, x0, x8, ne156; CHECK-NEXT: ret157 %cmp = icmp ne i64 %x, 100158 %sub = sub i64 100, %x159 %retval.0 = select i1 %cmp, i64 %x, i64 %sub160 ret i64 %retval.0161}162 163define i64 @sgt_i64(i64 %x) {164; CHECK-LABEL: sgt_i64:165; CHECK: // %bb.0:166; CHECK-NEXT: mov w8, #100 // =0x64167; CHECK-NEXT: subs x8, x8, x0168; CHECK-NEXT: csel x0, x0, x8, lt169; CHECK-NEXT: ret170 %cmp = icmp sgt i64 %x, 100171 %sub = sub i64 100, %x172 %retval.0 = select i1 %cmp, i64 %x, i64 %sub173 ret i64 %retval.0174}175 176define i64 @sge_i64(i64 %x) {177; CHECK-LABEL: sge_i64:178; CHECK: // %bb.0:179; CHECK-NEXT: mov w8, #100 // =0x64180; CHECK-NEXT: cmp x0, #99181; CHECK-NEXT: sub x8, x8, x0182; CHECK-NEXT: csel x0, x0, x8, gt183; CHECK-NEXT: ret184 %cmp = icmp sge i64 %x, 100185 %sub = sub i64 100, %x186 %retval.0 = select i1 %cmp, i64 %x, i64 %sub187 ret i64 %retval.0188}189 190define i64 @slt_i64(i64 %x) {191; CHECK-LABEL: slt_i64:192; CHECK: // %bb.0:193; CHECK-NEXT: mov w8, #100 // =0x64194; CHECK-NEXT: subs x8, x8, x0195; CHECK-NEXT: csel x0, x0, x8, gt196; CHECK-NEXT: ret197 %cmp = icmp slt i64 %x, 100198 %sub = sub i64 100, %x199 %retval.0 = select i1 %cmp, i64 %x, i64 %sub200 ret i64 %retval.0201}202 203define i64 @sle_i64(i64 %x) {204; CHECK-LABEL: sle_i64:205; CHECK: // %bb.0:206; CHECK-NEXT: mov w8, #100 // =0x64207; CHECK-NEXT: cmp x0, #101208; CHECK-NEXT: sub x8, x8, x0209; CHECK-NEXT: csel x0, x0, x8, lt210; CHECK-NEXT: ret211 %cmp = icmp sle i64 %x, 100212 %sub = sub i64 100, %x213 %retval.0 = select i1 %cmp, i64 %x, i64 %sub214 ret i64 %retval.0215}216 217define i64 @ugt_i64(i64 %x) {218; CHECK-LABEL: ugt_i64:219; CHECK: // %bb.0:220; CHECK-NEXT: mov w8, #100 // =0x64221; CHECK-NEXT: subs x8, x8, x0222; CHECK-NEXT: csel x0, x0, x8, lo223; CHECK-NEXT: ret224 %cmp = icmp ugt i64 %x, 100225 %sub = sub i64 100, %x226 %retval.0 = select i1 %cmp, i64 %x, i64 %sub227 ret i64 %retval.0228}229 230define i64 @uge_i64(i64 %x) {231; CHECK-LABEL: uge_i64:232; CHECK: // %bb.0:233; CHECK-NEXT: mov w8, #100 // =0x64234; CHECK-NEXT: cmp x0, #99235; CHECK-NEXT: sub x8, x8, x0236; CHECK-NEXT: csel x0, x0, x8, hi237; CHECK-NEXT: ret238 %cmp = icmp uge i64 %x, 100239 %sub = sub i64 100, %x240 %retval.0 = select i1 %cmp, i64 %x, i64 %sub241 ret i64 %retval.0242}243 244define i64 @ult_i64(i64 %x) {245; CHECK-LABEL: ult_i64:246; CHECK: // %bb.0:247; CHECK-NEXT: mov w8, #100 // =0x64248; CHECK-NEXT: subs x8, x8, x0249; CHECK-NEXT: csel x0, x0, x8, hi250; CHECK-NEXT: ret251 %cmp = icmp ult i64 %x, 100252 %sub = sub i64 100, %x253 %retval.0 = select i1 %cmp, i64 %x, i64 %sub254 ret i64 %retval.0255}256 257define i64 @ule_i64(i64 %x) {258; CHECK-LABEL: ule_i64:259; CHECK: // %bb.0:260; CHECK-NEXT: mov w8, #100 // =0x64261; CHECK-NEXT: cmp x0, #101262; CHECK-NEXT: sub x8, x8, x0263; CHECK-NEXT: csel x0, x0, x8, lo264; CHECK-NEXT: ret265 %cmp = icmp ule i64 %x, 100266 %sub = sub i64 100, %x267 %retval.0 = select i1 %cmp, i64 %x, i64 %sub268 ret i64 %retval.0269}270 271 272define i64 @both(i64 %x) {273; CHECK-LABEL: both:274; CHECK: // %bb.0:275; CHECK-NEXT: mov w8, #100 // =0x64276; CHECK-NEXT: sub x9, x0, #100277; CHECK-NEXT: cmp x0, #101278; CHECK-NEXT: sub x8, x8, x0279; CHECK-NEXT: csel x0, x8, x9, lo280; CHECK-NEXT: ret281 %cmp = icmp ule i64 %x, 100282 %sub1 = sub i64 100, %x283 %sub2 = sub i64 %x, 100284 %retval.0 = select i1 %cmp, i64 %sub1, i64 %sub2285 ret i64 %retval.0286}287 288define i32 @qabs(i32 %0) {289; CHECK-LABEL: qabs:290; CHECK: // %bb.0:291; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000292; CHECK-NEXT: cmp w0, w8293; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff294; CHECK-NEXT: csneg w8, w8, w0, eq295; CHECK-NEXT: cmp w0, #0296; CHECK-NEXT: csel w0, w0, w8, gt297; CHECK-NEXT: ret298 %cmp1 = icmp sgt i32 %0, 0299 %cmp2 = icmp eq i32 %0, -2147483648300 %sub = sub nsw i32 0, %0301 %cond = select i1 %cmp2, i32 2147483647, i32 %sub302 %cond6 = select i1 %cmp1, i32 %0, i32 %cond303 ret i32 %cond6304}305