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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mtriple=aarch64 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s --mtriple=aarch64 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i8 @llvm.ctlz.i8(i8, i1)6declare i16 @llvm.ctlz.i16(i16, i1)7declare i32 @llvm.ctlz.i32(i32, i1)8declare i64 @llvm.ctlz.i64(i64, i1)9 10define i8 @ctlo_i8(i8 %x) {11; CHECK-SD-LABEL: ctlo_i8:12; CHECK-SD: // %bb.0:13; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff14; CHECK-SD-NEXT: eor w8, w8, w0, lsl #2415; CHECK-SD-NEXT: clz w0, w816; CHECK-SD-NEXT: ret17;18; CHECK-GI-LABEL: ctlo_i8:19; CHECK-GI: // %bb.0:20; CHECK-GI-NEXT: mov w8, #255 // =0xff21; CHECK-GI-NEXT: bic w8, w8, w022; CHECK-GI-NEXT: clz w8, w823; CHECK-GI-NEXT: sub w0, w8, #2424; CHECK-GI-NEXT: ret25 %tmp1 = xor i8 %x, -126 %tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 false )27 ret i8 %tmp228}29 30define i8 @ctlo_i8_undef(i8 %x) {31; CHECK-SD-LABEL: ctlo_i8_undef:32; CHECK-SD: // %bb.0:33; CHECK-SD-NEXT: mvn w8, w034; CHECK-SD-NEXT: lsl w8, w8, #2435; CHECK-SD-NEXT: clz w0, w836; CHECK-SD-NEXT: ret37;38; CHECK-GI-LABEL: ctlo_i8_undef:39; CHECK-GI: // %bb.0:40; CHECK-GI-NEXT: mov w8, #255 // =0xff41; CHECK-GI-NEXT: bic w8, w8, w042; CHECK-GI-NEXT: clz w8, w843; CHECK-GI-NEXT: sub w0, w8, #2444; CHECK-GI-NEXT: ret45 %tmp1 = xor i8 %x, -146 %tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 true )47 ret i8 %tmp248}49 50define i16 @ctlo_i16(i16 %x) {51; CHECK-SD-LABEL: ctlo_i16:52; CHECK-SD: // %bb.0:53; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff54; CHECK-SD-NEXT: eor w8, w8, w0, lsl #1655; CHECK-SD-NEXT: clz w0, w856; CHECK-SD-NEXT: ret57;58; CHECK-GI-LABEL: ctlo_i16:59; CHECK-GI: // %bb.0:60; CHECK-GI-NEXT: mov w8, #65535 // =0xffff61; CHECK-GI-NEXT: bic w8, w8, w062; CHECK-GI-NEXT: clz w8, w863; CHECK-GI-NEXT: sub w0, w8, #1664; CHECK-GI-NEXT: ret65 %tmp1 = xor i16 %x, -166 %tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 false )67 ret i16 %tmp268}69 70define i16 @ctlo_i16_undef(i16 %x) {71; CHECK-SD-LABEL: ctlo_i16_undef:72; CHECK-SD: // %bb.0:73; CHECK-SD-NEXT: mvn w8, w074; CHECK-SD-NEXT: lsl w8, w8, #1675; CHECK-SD-NEXT: clz w0, w876; CHECK-SD-NEXT: ret77;78; CHECK-GI-LABEL: ctlo_i16_undef:79; CHECK-GI: // %bb.0:80; CHECK-GI-NEXT: mov w8, #65535 // =0xffff81; CHECK-GI-NEXT: bic w8, w8, w082; CHECK-GI-NEXT: clz w8, w883; CHECK-GI-NEXT: sub w0, w8, #1684; CHECK-GI-NEXT: ret85 %tmp1 = xor i16 %x, -186 %tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true )87 ret i16 %tmp288}89 90define i32 @ctlo_i32(i32 %x) {91; CHECK-LABEL: ctlo_i32:92; CHECK: // %bb.0:93; CHECK-NEXT: mvn w8, w094; CHECK-NEXT: clz w0, w895; CHECK-NEXT: ret96 %tmp1 = xor i32 %x, -197 %tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 false )98 ret i32 %tmp299}100 101define i32 @ctlo_i32_undef(i32 %x) {102; CHECK-LABEL: ctlo_i32_undef:103; CHECK: // %bb.0:104; CHECK-NEXT: mvn w8, w0105; CHECK-NEXT: clz w0, w8106; CHECK-NEXT: ret107 %tmp1 = xor i32 %x, -1108 %tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 true )109 ret i32 %tmp2110}111 112define i64 @ctlo_i64(i64 %x) {113; CHECK-LABEL: ctlo_i64:114; CHECK: // %bb.0:115; CHECK-NEXT: mvn x8, x0116; CHECK-NEXT: clz x0, x8117; CHECK-NEXT: ret118 %tmp1 = xor i64 %x, -1119 %tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 false )120 ret i64 %tmp2121}122 123define i64 @ctlo_i64_undef(i64 %x) {124; CHECK-LABEL: ctlo_i64_undef:125; CHECK: // %bb.0:126; CHECK-NEXT: mvn x8, x0127; CHECK-NEXT: clz x0, x8128; CHECK-NEXT: ret129 %tmp1 = xor i64 %x, -1130 %tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 true )131 ret i64 %tmp2132}133