597 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5 6define void @v2i8(ptr %p1) {7; CHECK-SD-LABEL: v2i8:8; CHECK-SD: // %bb.0: // %entry9; CHECK-SD-NEXT: ldr h1, [x0]10; CHECK-SD-NEXT: movi v0.2s, #2411; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #012; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #013; CHECK-SD-NEXT: clz v1.2s, v1.2s14; CHECK-SD-NEXT: sub v0.2s, v1.2s, v0.2s15; CHECK-SD-NEXT: mov s1, v0.s[1]16; CHECK-SD-NEXT: str b0, [x0]17; CHECK-SD-NEXT: stur b1, [x0, #1]18; CHECK-SD-NEXT: ret19;20; CHECK-GI-LABEL: v2i8:21; CHECK-GI: // %bb.0: // %entry22; CHECK-GI-NEXT: ldr b0, [x0]23; CHECK-GI-NEXT: add x8, x0, #124; CHECK-GI-NEXT: ld1 { v0.b }[1], [x8]25; CHECK-GI-NEXT: clz v0.8b, v0.8b26; CHECK-GI-NEXT: st1 { v0.b }[0], [x0]27; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]28; CHECK-GI-NEXT: ret29entry:30 %d = load <2 x i8>, ptr %p131 %s = call <2 x i8> @llvm.ctlz(<2 x i8> %d, i1 false)32 store <2 x i8> %s, ptr %p133 ret void34}35 36define void @v3i8(ptr %p1) {37; CHECK-SD-LABEL: v3i8:38; CHECK-SD: // %bb.0: // %entry39; CHECK-SD-NEXT: sub sp, sp, #1640; CHECK-SD-NEXT: .cfi_def_cfa_offset 1641; CHECK-SD-NEXT: movi v0.4h, #842; CHECK-SD-NEXT: ldr s1, [x0]43; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b44; CHECK-SD-NEXT: bic v1.4h, #255, lsl #845; CHECK-SD-NEXT: clz v1.4h, v1.4h46; CHECK-SD-NEXT: sub v0.4h, v1.4h, v0.4h47; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b48; CHECK-SD-NEXT: mov h0, v0.h[2]49; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #050; CHECK-SD-NEXT: stur b0, [x0, #2]51; CHECK-SD-NEXT: str h1, [x0]52; CHECK-SD-NEXT: add sp, sp, #1653; CHECK-SD-NEXT: ret54;55; CHECK-GI-LABEL: v3i8:56; CHECK-GI: // %bb.0: // %entry57; CHECK-GI-NEXT: ldr w8, [x0]58; CHECK-GI-NEXT: add x9, x0, #259; CHECK-GI-NEXT: fmov s0, w860; CHECK-GI-NEXT: add x8, x0, #161; CHECK-GI-NEXT: mov b1, v0.b[1]62; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]63; CHECK-GI-NEXT: mov b0, v0.b[2]64; CHECK-GI-NEXT: mov v2.b[1], v1.b[0]65; CHECK-GI-NEXT: mov v2.b[2], v0.b[0]66; CHECK-GI-NEXT: clz v0.8b, v2.8b67; CHECK-GI-NEXT: st1 { v0.b }[0], [x0]68; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]69; CHECK-GI-NEXT: st1 { v0.b }[2], [x9]70; CHECK-GI-NEXT: ret71entry:72 %d = load <3 x i8>, ptr %p173 %s = call <3 x i8> @llvm.ctlz(<3 x i8> %d, i1 false)74 store <3 x i8> %s, ptr %p175 ret void76}77 78define void @v4i8(ptr %p1) {79; CHECK-SD-LABEL: v4i8:80; CHECK-SD: // %bb.0: // %entry81; CHECK-SD-NEXT: ldr s1, [x0]82; CHECK-SD-NEXT: movi v0.4h, #883; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #084; CHECK-SD-NEXT: clz v1.4h, v1.4h85; CHECK-SD-NEXT: sub v0.4h, v1.4h, v0.4h86; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b87; CHECK-SD-NEXT: str s0, [x0]88; CHECK-SD-NEXT: ret89;90; CHECK-GI-LABEL: v4i8:91; CHECK-GI: // %bb.0: // %entry92; CHECK-GI-NEXT: ldr w8, [x0]93; CHECK-GI-NEXT: fmov s0, w894; CHECK-GI-NEXT: mov b1, v0.b[1]95; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]96; CHECK-GI-NEXT: mov b3, v0.b[2]97; CHECK-GI-NEXT: mov b0, v0.b[3]98; CHECK-GI-NEXT: mov v2.b[1], v1.b[0]99; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]100; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]101; CHECK-GI-NEXT: clz v0.8b, v2.8b102; CHECK-GI-NEXT: fmov w8, s0103; CHECK-GI-NEXT: str w8, [x0]104; CHECK-GI-NEXT: ret105entry:106 %d = load <4 x i8>, ptr %p1107 %s = call <4 x i8> @llvm.ctlz(<4 x i8> %d, i1 false)108 store <4 x i8> %s, ptr %p1109 ret void110}111 112define <8 x i8> @v8i8(<8 x i8> %d) {113; CHECK-LABEL: v8i8:114; CHECK: // %bb.0: // %entry115; CHECK-NEXT: clz v0.8b, v0.8b116; CHECK-NEXT: ret117entry:118 %s = call <8 x i8> @llvm.ctlz(<8 x i8> %d, i1 false)119 ret <8 x i8> %s120}121 122define <16 x i8> @v16i8(<16 x i8> %d) {123; CHECK-LABEL: v16i8:124; CHECK: // %bb.0: // %entry125; CHECK-NEXT: clz v0.16b, v0.16b126; CHECK-NEXT: ret127entry:128 %s = call <16 x i8> @llvm.ctlz(<16 x i8> %d, i1 false)129 ret <16 x i8> %s130}131 132define <32 x i8> @v32i8(<32 x i8> %d) {133; CHECK-LABEL: v32i8:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: clz v0.16b, v0.16b136; CHECK-NEXT: clz v1.16b, v1.16b137; CHECK-NEXT: ret138entry:139 %s = call <32 x i8> @llvm.ctlz(<32 x i8> %d, i1 false)140 ret <32 x i8> %s141}142 143define void @v2i16(ptr %p1) {144; CHECK-SD-LABEL: v2i16:145; CHECK-SD: // %bb.0: // %entry146; CHECK-SD-NEXT: ldr s1, [x0]147; CHECK-SD-NEXT: movi v0.2s, #16148; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0149; CHECK-SD-NEXT: clz v1.2s, v1.2s150; CHECK-SD-NEXT: sub v0.2s, v1.2s, v0.2s151; CHECK-SD-NEXT: mov s1, v0.s[1]152; CHECK-SD-NEXT: str h0, [x0]153; CHECK-SD-NEXT: str h1, [x0, #2]154; CHECK-SD-NEXT: ret155;156; CHECK-GI-LABEL: v2i16:157; CHECK-GI: // %bb.0: // %entry158; CHECK-GI-NEXT: ldr h0, [x0]159; CHECK-GI-NEXT: add x8, x0, #2160; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8]161; CHECK-GI-NEXT: clz v0.4h, v0.4h162; CHECK-GI-NEXT: str h0, [x0]163; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]164; CHECK-GI-NEXT: ret165entry:166 %d = load <2 x i16>, ptr %p1167 %s = call <2 x i16> @llvm.ctlz(<2 x i16> %d, i1 false)168 store <2 x i16> %s, ptr %p1169 ret void170}171 172define void @v3i16(ptr %p1) {173; CHECK-SD-LABEL: v3i16:174; CHECK-SD: // %bb.0: // %entry175; CHECK-SD-NEXT: ldr d0, [x0]176; CHECK-SD-NEXT: clz v0.4h, v0.4h177; CHECK-SD-NEXT: mov h1, v0.h[2]178; CHECK-SD-NEXT: str s0, [x0]179; CHECK-SD-NEXT: str h1, [x0, #4]180; CHECK-SD-NEXT: ret181;182; CHECK-GI-LABEL: v3i16:183; CHECK-GI: // %bb.0: // %entry184; CHECK-GI-NEXT: ldr d0, [x0]185; CHECK-GI-NEXT: add x8, x0, #2186; CHECK-GI-NEXT: add x9, x0, #4187; CHECK-GI-NEXT: clz v0.4h, v0.4h188; CHECK-GI-NEXT: str h0, [x0]189; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]190; CHECK-GI-NEXT: st1 { v0.h }[2], [x9]191; CHECK-GI-NEXT: ret192entry:193 %d = load <3 x i16>, ptr %p1194 %s = call <3 x i16> @llvm.ctlz(<3 x i16> %d, i1 false)195 store <3 x i16> %s, ptr %p1196 ret void197}198 199define <4 x i16> @v4i16(<4 x i16> %d) {200; CHECK-LABEL: v4i16:201; CHECK: // %bb.0: // %entry202; CHECK-NEXT: clz v0.4h, v0.4h203; CHECK-NEXT: ret204entry:205 %s = call <4 x i16> @llvm.ctlz(<4 x i16> %d, i1 false)206 ret <4 x i16> %s207}208 209define <8 x i16> @v8i16(<8 x i16> %d) {210; CHECK-LABEL: v8i16:211; CHECK: // %bb.0: // %entry212; CHECK-NEXT: clz v0.8h, v0.8h213; CHECK-NEXT: ret214entry:215 %s = call <8 x i16> @llvm.ctlz(<8 x i16> %d, i1 false)216 ret <8 x i16> %s217}218 219define <16 x i16> @v16i16(<16 x i16> %d) {220; CHECK-LABEL: v16i16:221; CHECK: // %bb.0: // %entry222; CHECK-NEXT: clz v0.8h, v0.8h223; CHECK-NEXT: clz v1.8h, v1.8h224; CHECK-NEXT: ret225entry:226 %s = call <16 x i16> @llvm.ctlz(<16 x i16> %d, i1 false)227 ret <16 x i16> %s228}229 230define <2 x i32> @v2i32(<2 x i32> %d) {231; CHECK-LABEL: v2i32:232; CHECK: // %bb.0: // %entry233; CHECK-NEXT: clz v0.2s, v0.2s234; CHECK-NEXT: ret235entry:236 %s = call <2 x i32> @llvm.ctlz(<2 x i32> %d, i1 false)237 ret <2 x i32> %s238}239 240define <3 x i32> @v3i32(<3 x i32> %d) {241; CHECK-LABEL: v3i32:242; CHECK: // %bb.0: // %entry243; CHECK-NEXT: clz v0.4s, v0.4s244; CHECK-NEXT: ret245entry:246 %s = call <3 x i32> @llvm.ctlz(<3 x i32> %d, i1 false)247 ret <3 x i32> %s248}249 250define <4 x i32> @v4i32(<4 x i32> %d) {251; CHECK-LABEL: v4i32:252; CHECK: // %bb.0: // %entry253; CHECK-NEXT: clz v0.4s, v0.4s254; CHECK-NEXT: ret255entry:256 %s = call <4 x i32> @llvm.ctlz(<4 x i32> %d, i1 false)257 ret <4 x i32> %s258}259 260define <8 x i32> @v8i32(<8 x i32> %d) {261; CHECK-LABEL: v8i32:262; CHECK: // %bb.0: // %entry263; CHECK-NEXT: clz v0.4s, v0.4s264; CHECK-NEXT: clz v1.4s, v1.4s265; CHECK-NEXT: ret266entry:267 %s = call <8 x i32> @llvm.ctlz(<8 x i32> %d, i1 false)268 ret <8 x i32> %s269}270 271define <2 x i64> @v2i64(<2 x i64> %d) {272; CHECK-SD-LABEL: v2i64:273; CHECK-SD: // %bb.0: // %entry274; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #1275; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b276; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #2277; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b278; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #4279; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b280; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #8281; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b282; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #16283; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b284; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #32285; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b286; CHECK-SD-NEXT: mvn v0.16b, v0.16b287; CHECK-SD-NEXT: cnt v0.16b, v0.16b288; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b289; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h290; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s291; CHECK-SD-NEXT: ret292;293; CHECK-GI-LABEL: v2i64:294; CHECK-GI: // %bb.0: // %entry295; CHECK-GI-NEXT: fmov x9, d0296; CHECK-GI-NEXT: mov x8, v0.d[1]297; CHECK-GI-NEXT: clz x9, x9298; CHECK-GI-NEXT: fmov d0, x9299; CHECK-GI-NEXT: clz x8, x8300; CHECK-GI-NEXT: mov v0.d[1], x8301; CHECK-GI-NEXT: ret302entry:303 %s = call <2 x i64> @llvm.ctlz(<2 x i64> %d, i1 false)304 ret <2 x i64> %s305}306 307define <3 x i64> @v3i64(<3 x i64> %d) {308; CHECK-SD-LABEL: v3i64:309; CHECK-SD: // %bb.0: // %entry310; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0311; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1312; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2313; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]314; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #1315; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b316; CHECK-SD-NEXT: ushr v1.2d, v2.2d, #1317; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #2318; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b319; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b320; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #2321; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #4322; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b323; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b324; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #4325; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #8326; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b327; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b328; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #8329; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #16330; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b331; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b332; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #16333; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #32334; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b335; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b336; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #32337; CHECK-SD-NEXT: mvn v0.16b, v0.16b338; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b339; CHECK-SD-NEXT: cnt v0.16b, v0.16b340; CHECK-SD-NEXT: mvn v1.16b, v1.16b341; CHECK-SD-NEXT: cnt v1.16b, v1.16b342; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b343; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h344; CHECK-SD-NEXT: uaddlp v1.8h, v1.16b345; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s346; CHECK-SD-NEXT: uaddlp v2.4s, v1.8h347; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8348; CHECK-SD-NEXT: uaddlp v2.2d, v2.4s349; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0350; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1351; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2352; CHECK-SD-NEXT: ret353;354; CHECK-GI-LABEL: v3i64:355; CHECK-GI: // %bb.0: // %entry356; CHECK-GI-NEXT: fmov x8, d0357; CHECK-GI-NEXT: fmov x9, d1358; CHECK-GI-NEXT: fmov x10, d2359; CHECK-GI-NEXT: clz x8, x8360; CHECK-GI-NEXT: clz x9, x9361; CHECK-GI-NEXT: clz x10, x10362; CHECK-GI-NEXT: fmov d0, x8363; CHECK-GI-NEXT: fmov d1, x9364; CHECK-GI-NEXT: fmov d2, x10365; CHECK-GI-NEXT: ret366entry:367 %s = call <3 x i64> @llvm.ctlz(<3 x i64> %d, i1 false)368 ret <3 x i64> %s369}370 371define <4 x i64> @v4i64(<4 x i64> %d) {372; CHECK-SD-LABEL: v4i64:373; CHECK-SD: // %bb.0: // %entry374; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #1375; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #1376; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b377; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b378; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #2379; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #2380; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b381; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b382; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #4383; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #4384; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b385; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b386; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #8387; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #8388; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b389; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b390; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #16391; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #16392; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b393; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b394; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #32395; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #32396; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b397; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b398; CHECK-SD-NEXT: mvn v0.16b, v0.16b399; CHECK-SD-NEXT: mvn v1.16b, v1.16b400; CHECK-SD-NEXT: cnt v0.16b, v0.16b401; CHECK-SD-NEXT: cnt v1.16b, v1.16b402; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b403; CHECK-SD-NEXT: uaddlp v1.8h, v1.16b404; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h405; CHECK-SD-NEXT: uaddlp v1.4s, v1.8h406; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s407; CHECK-SD-NEXT: uaddlp v1.2d, v1.4s408; CHECK-SD-NEXT: ret409;410; CHECK-GI-LABEL: v4i64:411; CHECK-GI: // %bb.0: // %entry412; CHECK-GI-NEXT: fmov x10, d0413; CHECK-GI-NEXT: fmov x11, d1414; CHECK-GI-NEXT: mov x8, v0.d[1]415; CHECK-GI-NEXT: mov x9, v1.d[1]416; CHECK-GI-NEXT: clz x10, x10417; CHECK-GI-NEXT: clz x11, x11418; CHECK-GI-NEXT: fmov d0, x10419; CHECK-GI-NEXT: fmov d1, x11420; CHECK-GI-NEXT: clz x8, x8421; CHECK-GI-NEXT: clz x9, x9422; CHECK-GI-NEXT: mov v0.d[1], x8423; CHECK-GI-NEXT: mov v1.d[1], x9424; CHECK-GI-NEXT: ret425entry:426 %s = call <4 x i64> @llvm.ctlz(<4 x i64> %d, i1 false)427 ret <4 x i64> %s428}429 430define <2 x i128> @v2i128(<2 x i128> %d) {431; CHECK-SD-LABEL: v2i128:432; CHECK-SD: // %bb.0: // %entry433; CHECK-SD-NEXT: clz x8, x0434; CHECK-SD-NEXT: clz x9, x1435; CHECK-SD-NEXT: cmp x1, #0436; CHECK-SD-NEXT: add x8, x8, #64437; CHECK-SD-NEXT: clz x10, x2438; CHECK-SD-NEXT: mov x1, xzr439; CHECK-SD-NEXT: csel x0, x9, x8, ne440; CHECK-SD-NEXT: clz x8, x3441; CHECK-SD-NEXT: add x9, x10, #64442; CHECK-SD-NEXT: cmp x3, #0443; CHECK-SD-NEXT: mov x3, xzr444; CHECK-SD-NEXT: csel x2, x8, x9, ne445; CHECK-SD-NEXT: ret446;447; CHECK-GI-LABEL: v2i128:448; CHECK-GI: // %bb.0: // %entry449; CHECK-GI-NEXT: mov w8, wzr450; CHECK-GI-NEXT: clz x9, x0451; CHECK-GI-NEXT: clz x11, x1452; CHECK-GI-NEXT: cmp w8, #1453; CHECK-GI-NEXT: add x9, x9, #64454; CHECK-GI-NEXT: adc x10, xzr, xzr455; CHECK-GI-NEXT: cmp x1, #0456; CHECK-GI-NEXT: csel x0, x9, x11, eq457; CHECK-GI-NEXT: clz x9, x2458; CHECK-GI-NEXT: csel x1, x10, xzr, eq459; CHECK-GI-NEXT: cmp w8, #1460; CHECK-GI-NEXT: add x9, x9, #64461; CHECK-GI-NEXT: clz x10, x3462; CHECK-GI-NEXT: adc x8, xzr, xzr463; CHECK-GI-NEXT: cmp x3, #0464; CHECK-GI-NEXT: csel x2, x9, x10, eq465; CHECK-GI-NEXT: csel x3, x8, xzr, eq466; CHECK-GI-NEXT: ret467entry:468 %s = call <2 x i128> @llvm.ctlz(<2 x i128> %d, i1 false)469 ret <2 x i128> %s470}471 472define <3 x i128> @v3i128(<3 x i128> %d) {473; CHECK-SD-LABEL: v3i128:474; CHECK-SD: // %bb.0: // %entry475; CHECK-SD-NEXT: clz x8, x0476; CHECK-SD-NEXT: clz x9, x1477; CHECK-SD-NEXT: cmp x1, #0478; CHECK-SD-NEXT: add x8, x8, #64479; CHECK-SD-NEXT: clz x10, x2480; CHECK-SD-NEXT: mov x1, xzr481; CHECK-SD-NEXT: csel x0, x9, x8, ne482; CHECK-SD-NEXT: clz x8, x3483; CHECK-SD-NEXT: add x9, x10, #64484; CHECK-SD-NEXT: cmp x3, #0485; CHECK-SD-NEXT: mov x3, xzr486; CHECK-SD-NEXT: csel x2, x8, x9, ne487; CHECK-SD-NEXT: clz x8, x4488; CHECK-SD-NEXT: clz x9, x5489; CHECK-SD-NEXT: add x8, x8, #64490; CHECK-SD-NEXT: cmp x5, #0491; CHECK-SD-NEXT: mov x5, xzr492; CHECK-SD-NEXT: csel x4, x9, x8, ne493; CHECK-SD-NEXT: ret494;495; CHECK-GI-LABEL: v3i128:496; CHECK-GI: // %bb.0: // %entry497; CHECK-GI-NEXT: mov w8, wzr498; CHECK-GI-NEXT: clz x9, x0499; CHECK-GI-NEXT: clz x11, x1500; CHECK-GI-NEXT: cmp w8, #1501; CHECK-GI-NEXT: add x9, x9, #64502; CHECK-GI-NEXT: adc x10, xzr, xzr503; CHECK-GI-NEXT: cmp x1, #0504; CHECK-GI-NEXT: csel x0, x9, x11, eq505; CHECK-GI-NEXT: clz x9, x2506; CHECK-GI-NEXT: csel x1, x10, xzr, eq507; CHECK-GI-NEXT: cmp w8, #1508; CHECK-GI-NEXT: add x9, x9, #64509; CHECK-GI-NEXT: clz x11, x3510; CHECK-GI-NEXT: adc x10, xzr, xzr511; CHECK-GI-NEXT: cmp x3, #0512; CHECK-GI-NEXT: csel x2, x9, x11, eq513; CHECK-GI-NEXT: clz x9, x4514; CHECK-GI-NEXT: csel x3, x10, xzr, eq515; CHECK-GI-NEXT: cmp w8, #1516; CHECK-GI-NEXT: add x9, x9, #64517; CHECK-GI-NEXT: clz x10, x5518; CHECK-GI-NEXT: adc x8, xzr, xzr519; CHECK-GI-NEXT: cmp x5, #0520; CHECK-GI-NEXT: csel x4, x9, x10, eq521; CHECK-GI-NEXT: csel x5, x8, xzr, eq522; CHECK-GI-NEXT: ret523entry:524 %s = call <3 x i128> @llvm.ctlz(<3 x i128> %d, i1 false)525 ret <3 x i128> %s526}527 528define <4 x i128> @v4i128(<4 x i128> %d) {529; CHECK-SD-LABEL: v4i128:530; CHECK-SD: // %bb.0: // %entry531; CHECK-SD-NEXT: clz x9, x0532; CHECK-SD-NEXT: clz x8, x2533; CHECK-SD-NEXT: clz x10, x1534; CHECK-SD-NEXT: add x9, x9, #64535; CHECK-SD-NEXT: cmp x1, #0536; CHECK-SD-NEXT: add x8, x8, #64537; CHECK-SD-NEXT: csel x0, x10, x9, ne538; CHECK-SD-NEXT: clz x9, x3539; CHECK-SD-NEXT: cmp x3, #0540; CHECK-SD-NEXT: csel x2, x9, x8, ne541; CHECK-SD-NEXT: clz x8, x4542; CHECK-SD-NEXT: clz x9, x5543; CHECK-SD-NEXT: add x8, x8, #64544; CHECK-SD-NEXT: cmp x5, #0545; CHECK-SD-NEXT: mov x1, xzr546; CHECK-SD-NEXT: csel x4, x9, x8, ne547; CHECK-SD-NEXT: clz x8, x6548; CHECK-SD-NEXT: clz x9, x7549; CHECK-SD-NEXT: add x8, x8, #64550; CHECK-SD-NEXT: cmp x7, #0551; CHECK-SD-NEXT: mov x3, xzr552; CHECK-SD-NEXT: csel x6, x9, x8, ne553; CHECK-SD-NEXT: mov x5, xzr554; CHECK-SD-NEXT: mov x7, xzr555; CHECK-SD-NEXT: ret556;557; CHECK-GI-LABEL: v4i128:558; CHECK-GI: // %bb.0: // %entry559; CHECK-GI-NEXT: mov w8, wzr560; CHECK-GI-NEXT: clz x9, x0561; CHECK-GI-NEXT: clz x11, x1562; CHECK-GI-NEXT: cmp w8, #1563; CHECK-GI-NEXT: add x9, x9, #64564; CHECK-GI-NEXT: adc x10, xzr, xzr565; CHECK-GI-NEXT: cmp x1, #0566; CHECK-GI-NEXT: csel x0, x9, x11, eq567; CHECK-GI-NEXT: clz x9, x2568; CHECK-GI-NEXT: csel x1, x10, xzr, eq569; CHECK-GI-NEXT: cmp w8, #1570; CHECK-GI-NEXT: add x9, x9, #64571; CHECK-GI-NEXT: clz x11, x3572; CHECK-GI-NEXT: adc x10, xzr, xzr573; CHECK-GI-NEXT: cmp x3, #0574; CHECK-GI-NEXT: csel x2, x9, x11, eq575; CHECK-GI-NEXT: clz x9, x4576; CHECK-GI-NEXT: csel x3, x10, xzr, eq577; CHECK-GI-NEXT: cmp w8, #1578; CHECK-GI-NEXT: add x9, x9, #64579; CHECK-GI-NEXT: clz x11, x5580; CHECK-GI-NEXT: adc x10, xzr, xzr581; CHECK-GI-NEXT: cmp x5, #0582; CHECK-GI-NEXT: csel x4, x9, x11, eq583; CHECK-GI-NEXT: clz x9, x6584; CHECK-GI-NEXT: csel x5, x10, xzr, eq585; CHECK-GI-NEXT: cmp w8, #1586; CHECK-GI-NEXT: add x9, x9, #64587; CHECK-GI-NEXT: clz x10, x7588; CHECK-GI-NEXT: adc x8, xzr, xzr589; CHECK-GI-NEXT: cmp x7, #0590; CHECK-GI-NEXT: csel x6, x9, x10, eq591; CHECK-GI-NEXT: csel x7, x8, xzr, eq592; CHECK-GI-NEXT: ret593entry:594 %s = call <4 x i128> @llvm.ctlz(<4 x i128> %d, i1 false)595 ret <4 x i128> %s596}597