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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s --mtriple=aarch64 | FileCheck %s3 4declare i8 @llvm.ctlz.i8(i8, i1 immarg)5declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1 immarg)6declare i11 @llvm.ctlz.i11(i11, i1 immarg)7 8define i32 @clz_nzu8(i8 %self) {9; CHECK-LABEL: clz_nzu8:10; CHECK: // %bb.0: // %start11; CHECK-NEXT: lsl w8, w0, #2412; CHECK-NEXT: clz w0, w813; CHECK-NEXT: ret14start:15 %ctlz_res = call i8 @llvm.ctlz.i8(i8 %self, i1 true)16 %ret = zext i8 %ctlz_res to i3217 ret i32 %ret18}19 20; non standard bit size argument to ctlz21define i32 @clz_nzu11(i11 %self) {22; CHECK-LABEL: clz_nzu11:23; CHECK: // %bb.0:24; CHECK-NEXT: lsl w8, w0, #2125; CHECK-NEXT: clz w0, w826; CHECK-NEXT: ret27 %ctlz_res = call i11 @llvm.ctlz.i11(i11 %self, i1 true)28 %ret = zext i11 %ctlz_res to i3229 ret i32 %ret30}31 32; vector type argument to ctlz intrinsic33define <8 x i32> @clz_vec_nzu8(<8 x i8> %self) {34; CHECK-LABEL: clz_vec_nzu8:35; CHECK: // %bb.0:36; CHECK-NEXT: clz v0.8b, v0.8b37; CHECK-NEXT: ushll v0.8h, v0.8b, #038; CHECK-NEXT: ushll2 v1.4s, v0.8h, #039; CHECK-NEXT: ushll v0.4s, v0.4h, #040; CHECK-NEXT: ret41 %ctlz_res = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %self, i1 true)42 %ret = zext <8 x i8> %ctlz_res to <8 x i32>43 ret <8 x i32> %ret44}45