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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {6; CHECK-LABEL: test_madd32:7; CHECK: ; %bb.0:8; CHECK-NEXT: madd w0, w1, w2, w09; CHECK-NEXT: ret10 %mid = mul i32 %val1, %val211 %res = add i32 %val0, %mid12 ret i32 %res13}14 15define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {16; CHECK-LABEL: test_madd64:17; CHECK: ; %bb.0:18; CHECK-NEXT: madd x0, x1, x2, x019; CHECK-NEXT: ret20 %mid = mul i64 %val1, %val221 %res = add i64 %val0, %mid22 ret i64 %res23}24 25define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {26; CHECK-LABEL: test_msub32:27; CHECK: ; %bb.0:28; CHECK-NEXT: msub w0, w1, w2, w029; CHECK-NEXT: ret30 %mid = mul i32 %val1, %val231 %res = sub i32 %val0, %mid32 ret i32 %res33}34 35define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {36; CHECK-LABEL: test_msub64:37; CHECK: ; %bb.0:38; CHECK-NEXT: msub x0, x1, x2, x039; CHECK-NEXT: ret40 %mid = mul i64 %val1, %val241 %res = sub i64 %val0, %mid42 ret i64 %res43}44 45define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {46; CHECK-LABEL: test_smaddl:47; CHECK: ; %bb.0:48; CHECK-NEXT: smaddl x0, w1, w2, x049; CHECK-NEXT: ret50 %ext1 = sext i32 %val1 to i6451 %ext2 = sext i32 %val2 to i6452 %prod = mul i64 %ext1, %ext253 %res = add i64 %acc, %prod54 ret i64 %res55}56 57define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {58; CHECK-LABEL: test_smsubl:59; CHECK: ; %bb.0:60; CHECK-NEXT: smsubl x0, w1, w2, x061; CHECK-NEXT: ret62 %ext1 = sext i32 %val1 to i6463 %ext2 = sext i32 %val2 to i6464 %prod = mul i64 %ext1, %ext265 %res = sub i64 %acc, %prod66 ret i64 %res67}68 69define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {70; CHECK-LABEL: test_umaddl:71; CHECK: ; %bb.0:72; CHECK-NEXT: umaddl x0, w1, w2, x073; CHECK-NEXT: ret74 %ext1 = zext i32 %val1 to i6475 %ext2 = zext i32 %val2 to i6476 %prod = mul i64 %ext1, %ext277 %res = add i64 %acc, %prod78 ret i64 %res79}80 81define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {82; CHECK-LABEL: test_umsubl:83; CHECK: ; %bb.0:84; CHECK-NEXT: umsubl x0, w1, w2, x085; CHECK-NEXT: ret86 %ext1 = zext i32 %val1 to i6487 %ext2 = zext i32 %val2 to i6488 %prod = mul i64 %ext1, %ext289 %res = sub i64 %acc, %prod90 ret i64 %res91}92 93define i64 @test_smulh(i64 %lhs, i64 %rhs) {94; CHECK-SD-LABEL: test_smulh:95; CHECK-SD: ; %bb.0:96; CHECK-SD-NEXT: smulh x0, x0, x197; CHECK-SD-NEXT: ret98;99; CHECK-GI-LABEL: test_smulh:100; CHECK-GI: ; %bb.0:101; CHECK-GI-NEXT: asr x8, x1, #63102; CHECK-GI-NEXT: asr x9, x0, #63103; CHECK-GI-NEXT: umulh x10, x0, x1104; CHECK-GI-NEXT: mul x8, x0, x8105; CHECK-GI-NEXT: madd x8, x9, x1, x8106; CHECK-GI-NEXT: add x0, x8, x10107; CHECK-GI-NEXT: ret108 %ext1 = sext i64 %lhs to i128109 %ext2 = sext i64 %rhs to i128110 %res = mul i128 %ext1, %ext2111 %high = lshr i128 %res, 64112 %val = trunc i128 %high to i64113 ret i64 %val114}115 116define i64 @test_umulh(i64 %lhs, i64 %rhs) {117; CHECK-LABEL: test_umulh:118; CHECK: ; %bb.0:119; CHECK-NEXT: umulh x0, x0, x1120; CHECK-NEXT: ret121 %ext1 = zext i64 %lhs to i128122 %ext2 = zext i64 %rhs to i128123 %res = mul i128 %ext1, %ext2124 %high = lshr i128 %res, 64125 %val = trunc i128 %high to i64126 ret i64 %val127}128 129define i32 @test_mul32(i32 %lhs, i32 %rhs) {130; CHECK-LABEL: test_mul32:131; CHECK: ; %bb.0:132; CHECK-NEXT: mul w0, w0, w1133; CHECK-NEXT: ret134 %res = mul i32 %lhs, %rhs135 ret i32 %res136}137 138define i64 @test_mul64(i64 %lhs, i64 %rhs) {139; CHECK-LABEL: test_mul64:140; CHECK: ; %bb.0:141; CHECK-NEXT: mul x0, x0, x1142; CHECK-NEXT: ret143 %res = mul i64 %lhs, %rhs144 ret i64 %res145}146 147define i32 @test_mneg32(i32 %lhs, i32 %rhs) {148; CHECK-LABEL: test_mneg32:149; CHECK: ; %bb.0:150; CHECK-NEXT: mneg w0, w0, w1151; CHECK-NEXT: ret152 %prod = mul i32 %lhs, %rhs153 %res = sub i32 0, %prod154 ret i32 %res155}156 157define i64 @test_mneg64(i64 %lhs, i64 %rhs) {158; CHECK-LABEL: test_mneg64:159; CHECK: ; %bb.0:160; CHECK-NEXT: mneg x0, x0, x1161; CHECK-NEXT: ret162 %prod = mul i64 %lhs, %rhs163 %res = sub i64 0, %prod164 ret i64 %res165}166 167define i64 @test_smull(i32 %lhs, i32 %rhs) {168; CHECK-LABEL: test_smull:169; CHECK: ; %bb.0:170; CHECK-NEXT: smull x0, w0, w1171; CHECK-NEXT: ret172 %ext1 = sext i32 %lhs to i64173 %ext2 = sext i32 %rhs to i64174 %res = mul i64 %ext1, %ext2175 ret i64 %res176}177 178define i64 @test_umull(i32 %lhs, i32 %rhs) {179; CHECK-LABEL: test_umull:180; CHECK: ; %bb.0:181; CHECK-NEXT: umull x0, w0, w1182; CHECK-NEXT: ret183 %ext1 = zext i32 %lhs to i64184 %ext2 = zext i32 %rhs to i64185 %res = mul i64 %ext1, %ext2186 ret i64 %res187}188 189define i64 @test_smnegl(i32 %lhs, i32 %rhs) {190; CHECK-LABEL: test_smnegl:191; CHECK: ; %bb.0:192; CHECK-NEXT: smnegl x0, w0, w1193; CHECK-NEXT: ret194 %ext1 = sext i32 %lhs to i64195 %ext2 = sext i32 %rhs to i64196 %prod = mul i64 %ext1, %ext2197 %res = sub i64 0, %prod198 ret i64 %res199}200 201define i64 @test_umnegl(i32 %lhs, i32 %rhs) {202; CHECK-LABEL: test_umnegl:203; CHECK: ; %bb.0:204; CHECK-NEXT: umnegl x0, w0, w1205; CHECK-NEXT: ret206 %ext1 = zext i32 %lhs to i64207 %ext2 = zext i32 %rhs to i64208 %prod = mul i64 %ext1, %ext2209 %res = sub i64 0, %prod210 ret i64 %res211}212 213@a = common global i32 0, align 4214@b = common global i32 0, align 4215@c = common global i32 0, align 4216 217define void @test_mneg(){218; CHECK-LABEL: test_mneg:219; CHECK: ; %bb.0:220; CHECK-NEXT: Lloh0:221; CHECK-NEXT: adrp x8, _a@GOTPAGE222; CHECK-NEXT: Lloh1:223; CHECK-NEXT: adrp x9, _b@GOTPAGE224; CHECK-NEXT: Lloh2:225; CHECK-NEXT: ldr x8, [x8, _a@GOTPAGEOFF]226; CHECK-NEXT: Lloh3:227; CHECK-NEXT: ldr x9, [x9, _b@GOTPAGEOFF]228; CHECK-NEXT: Lloh4:229; CHECK-NEXT: ldr w8, [x8]230; CHECK-NEXT: Lloh5:231; CHECK-NEXT: ldr w9, [x9]232; CHECK-NEXT: mneg w8, w8, w9233; CHECK-NEXT: Lloh6:234; CHECK-NEXT: adrp x9, _c@GOTPAGE235; CHECK-NEXT: Lloh7:236; CHECK-NEXT: ldr x9, [x9, _c@GOTPAGEOFF]237; CHECK-NEXT: Lloh8:238; CHECK-NEXT: str w8, [x9]239; CHECK-NEXT: ret240; CHECK-NEXT: .loh AdrpLdrGotStr Lloh6, Lloh7, Lloh8241; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh1, Lloh3, Lloh5242; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh0, Lloh2, Lloh4243 %1 = load i32, ptr @a, align 4244 %2 = load i32, ptr @b, align 4245 %3 = sub i32 0, %1246 %4 = mul i32 %2, %3247 store i32 %4, ptr @c, align 4248 ret void249}250