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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG3; RUN: llc -global-isel -global-isel-abort=1 -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL4 5@var32 = global i32 06@var64 = global i64 07 8define void @rev_i32() {9; CHECK-LABEL: rev_i32:10; CHECK: // %bb.0:11; CHECK-NEXT: adrp x8, :got:var3212; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]13; CHECK-NEXT: ldr w9, [x8]14; CHECK-NEXT: rev w9, w915; CHECK-NEXT: str w9, [x8]16; CHECK-NEXT: ret17 %val0_tmp = load i32, ptr @var3218 %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)19 store volatile i32 %val1_tmp, ptr @var3220 ret void21}22 23define void @rev_i64() {24; CHECK-LABEL: rev_i64:25; CHECK: // %bb.0:26; CHECK-NEXT: adrp x8, :got:var6427; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]28; CHECK-NEXT: ldr x9, [x8]29; CHECK-NEXT: rev x9, x930; CHECK-NEXT: str x9, [x8]31; CHECK-NEXT: ret32 %val0_tmp = load i64, ptr @var6433 %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)34 store volatile i64 %val1_tmp, ptr @var6435 ret void36}37 38define void @rev32_i64() {39; CHECK-LABEL: rev32_i64:40; CHECK: // %bb.0:41; CHECK-NEXT: adrp x8, :got:var6442; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]43; CHECK-NEXT: ldr x9, [x8]44; CHECK-NEXT: rev32 x9, x945; CHECK-NEXT: str x9, [x8]46; CHECK-NEXT: ret47 %val0_tmp = load i64, ptr @var6448 %val1_tmp = shl i64 %val0_tmp, 3249 %val5_tmp = sub i64 64, 3250 %val2_tmp = lshr i64 %val0_tmp, %val5_tmp51 %val3_tmp = or i64 %val1_tmp, %val2_tmp52 %val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)53 store volatile i64 %val4_tmp, ptr @var6454 ret void55}56 57define void @rev16_i32() {58; CHECK-LABEL: rev16_i32:59; CHECK: // %bb.0:60; CHECK-NEXT: adrp x8, :got:var3261; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]62; CHECK-NEXT: ldr w9, [x8]63; CHECK-NEXT: rev16 w9, w964; CHECK-NEXT: str w9, [x8]65; CHECK-NEXT: ret66 %val0_tmp = load i32, ptr @var3267 %val1_tmp = shl i32 %val0_tmp, 1668 %val2_tmp = lshr i32 %val0_tmp, 1669 %val3_tmp = or i32 %val1_tmp, %val2_tmp70 %val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)71 store volatile i32 %val4_tmp, ptr @var3272 ret void73}74 75define void @clz_zerodef_i32() {76; CHECK-LABEL: clz_zerodef_i32:77; CHECK: // %bb.0:78; CHECK-NEXT: adrp x8, :got:var3279; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]80; CHECK-NEXT: ldr w9, [x8]81; CHECK-NEXT: clz w9, w982; CHECK-NEXT: str w9, [x8]83; CHECK-NEXT: ret84 %val0_tmp = load i32, ptr @var3285 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)86 store volatile i32 %val4_tmp, ptr @var3287 ret void88}89 90define void @clz_zerodef_i64() {91; CHECK-LABEL: clz_zerodef_i64:92; CHECK: // %bb.0:93; CHECK-NEXT: adrp x8, :got:var6494; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]95; CHECK-NEXT: ldr x9, [x8]96; CHECK-NEXT: clz x9, x997; CHECK-NEXT: str x9, [x8]98; CHECK-NEXT: ret99 %val0_tmp = load i64, ptr @var64100 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)101 store volatile i64 %val4_tmp, ptr @var64102 ret void103}104 105define void @clz_zeroundef_i32() {106; CHECK-LABEL: clz_zeroundef_i32:107; CHECK: // %bb.0:108; CHECK-NEXT: adrp x8, :got:var32109; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]110; CHECK-NEXT: ldr w9, [x8]111; CHECK-NEXT: clz w9, w9112; CHECK-NEXT: str w9, [x8]113; CHECK-NEXT: ret114 %val0_tmp = load i32, ptr @var32115 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)116 store volatile i32 %val4_tmp, ptr @var32117 ret void118}119 120define void @clz_zeroundef_i64() {121; CHECK-LABEL: clz_zeroundef_i64:122; CHECK: // %bb.0:123; CHECK-NEXT: adrp x8, :got:var64124; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]125; CHECK-NEXT: ldr x9, [x8]126; CHECK-NEXT: clz x9, x9127; CHECK-NEXT: str x9, [x8]128; CHECK-NEXT: ret129 %val0_tmp = load i64, ptr @var64130 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)131 store volatile i64 %val4_tmp, ptr @var64132 ret void133}134 135define void @cttz_zerodef_i32() {136; CHECK-LABEL: cttz_zerodef_i32:137; CHECK: // %bb.0:138; CHECK-NEXT: adrp x8, :got:var32139; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]140; CHECK-NEXT: ldr w9, [x8]141; CHECK-NEXT: rbit w9, w9142; CHECK-NEXT: clz w9, w9143; CHECK-NEXT: str w9, [x8]144; CHECK-NEXT: ret145 %val0_tmp = load i32, ptr @var32146 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)147 store volatile i32 %val4_tmp, ptr @var32148 ret void149}150 151define void @cttz_zerodef_i64() {152; CHECK-LABEL: cttz_zerodef_i64:153; CHECK: // %bb.0:154; CHECK-NEXT: adrp x8, :got:var64155; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]156; CHECK-NEXT: ldr x9, [x8]157; CHECK-NEXT: rbit x9, x9158; CHECK-NEXT: clz x9, x9159; CHECK-NEXT: str x9, [x8]160; CHECK-NEXT: ret161 %val0_tmp = load i64, ptr @var64162 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)163 store volatile i64 %val4_tmp, ptr @var64164 ret void165}166 167define void @cttz_zeroundef_i32() {168; CHECK-LABEL: cttz_zeroundef_i32:169; CHECK: // %bb.0:170; CHECK-NEXT: adrp x8, :got:var32171; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]172; CHECK-NEXT: ldr w9, [x8]173; CHECK-NEXT: rbit w9, w9174; CHECK-NEXT: clz w9, w9175; CHECK-NEXT: str w9, [x8]176; CHECK-NEXT: ret177 %val0_tmp = load i32, ptr @var32178 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)179 store volatile i32 %val4_tmp, ptr @var32180 ret void181}182 183define void @cttz_zeroundef_i64() {184; CHECK-LABEL: cttz_zeroundef_i64:185; CHECK: // %bb.0:186; CHECK-NEXT: adrp x8, :got:var64187; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]188; CHECK-NEXT: ldr x9, [x8]189; CHECK-NEXT: rbit x9, x9190; CHECK-NEXT: clz x9, x9191; CHECK-NEXT: str x9, [x8]192; CHECK-NEXT: ret193 %val0_tmp = load i64, ptr @var64194 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)195 store volatile i64 %val4_tmp, ptr @var64196 ret void197}198 199define void @ctpop_i32() {200; CHECK-SDAG-LABEL: ctpop_i32:201; CHECK-SDAG: // %bb.0:202; CHECK-SDAG-NEXT: adrp x8, :got:var32203; CHECK-SDAG-NEXT: ldr x8, [x8, :got_lo12:var32]204; CHECK-SDAG-NEXT: ldr w9, [x8]205; CHECK-SDAG-NEXT: fmov d0, x9206; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b207; CHECK-SDAG-NEXT: addv b0, v0.8b208; CHECK-SDAG-NEXT: str s0, [x8]209; CHECK-SDAG-NEXT: ret210;211; CHECK-GISEL-LABEL: ctpop_i32:212; CHECK-GISEL: // %bb.0:213; CHECK-GISEL-NEXT: adrp x8, :got:var32214; CHECK-GISEL-NEXT: ldr x8, [x8, :got_lo12:var32]215; CHECK-GISEL-NEXT: ldr w9, [x8]216; CHECK-GISEL-NEXT: fmov d0, x9217; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b218; CHECK-GISEL-NEXT: uaddlv h0, v0.8b219; CHECK-GISEL-NEXT: str s0, [x8]220; CHECK-GISEL-NEXT: ret221 %val0_tmp = load i32, ptr @var32222 %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)223 store volatile i32 %val4_tmp, ptr @var32224 ret void225}226 227define i64 @popcnt(i64 %a, ptr %p) {228; CHECK-SDAG-LABEL: popcnt:229; CHECK-SDAG: // %bb.0:230; CHECK-SDAG-NEXT: fmov d0, x0231; CHECK-SDAG-NEXT: mov x0, xzr232; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b233; CHECK-SDAG-NEXT: addv b0, v0.8b234; CHECK-SDAG-NEXT: str d0, [x1]235; CHECK-SDAG-NEXT: ret236;237; CHECK-GISEL-LABEL: popcnt:238; CHECK-GISEL: // %bb.0:239; CHECK-GISEL-NEXT: fmov d0, x0240; CHECK-GISEL-NEXT: mov x0, xzr241; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b242; CHECK-GISEL-NEXT: uaddlv h0, v0.8b243; CHECK-GISEL-NEXT: mov w8, v0.s[0]244; CHECK-GISEL-NEXT: str x8, [x1]245; CHECK-GISEL-NEXT: ret246 %2 = call i64 @llvm.ctpop(i64 %a)247 store i64 %2, ptr %p248 ret i64 0249}250 251declare i32 @llvm.bswap.i32(i32)252declare i64 @llvm.bswap.i64(i64)253declare i32 @llvm.ctlz.i32 (i32, i1)254declare i64 @llvm.ctlz.i64 (i64, i1)255declare i32 @llvm.cttz.i32 (i32, i1)256declare i64 @llvm.cttz.i64 (i64, i1)257declare i32 @llvm.ctpop.i32 (i32)258declare i64 @llvm.ctpop.i64 (i64)259