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1; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s2 3@var32_0 = global i32 04@var32_1 = global i32 05@var64_0 = global i64 06@var64_1 = global i64 07 8define void @rorv_i64() {9; CHECK-LABEL: rorv_i64:10 %val0_tmp = load i64, ptr @var64_011 %val1_tmp = load i64, ptr @var64_112 %val2_tmp = sub i64 64, %val1_tmp13 %val3_tmp = shl i64 %val0_tmp, %val2_tmp14 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp15 %val5_tmp = or i64 %val3_tmp, %val4_tmp16; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}17 store volatile i64 %val5_tmp, ptr @var64_018 ret void19}20 21define void @asrv_i64() {22; CHECK-LABEL: asrv_i64:23 %val0_tmp = load i64, ptr @var64_024 %val1_tmp = load i64, ptr @var64_125 %val4_tmp = ashr i64 %val0_tmp, %val1_tmp26; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}27 store volatile i64 %val4_tmp, ptr @var64_128 ret void29}30 31define void @lsrv_i64() {32; CHECK-LABEL: lsrv_i64:33 %val0_tmp = load i64, ptr @var64_034 %val1_tmp = load i64, ptr @var64_135 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp36; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}37 store volatile i64 %val4_tmp, ptr @var64_038 ret void39}40 41define void @lslv_i64() {42; CHECK-LABEL: lslv_i64:43 %val0_tmp = load i64, ptr @var64_044 %val1_tmp = load i64, ptr @var64_145 %val4_tmp = shl i64 %val0_tmp, %val1_tmp46; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}47 store volatile i64 %val4_tmp, ptr @var64_148 ret void49}50 51define void @udiv_i64() {52; CHECK-LABEL: udiv_i64:53 %val0_tmp = load i64, ptr @var64_054 %val1_tmp = load i64, ptr @var64_155 %val4_tmp = udiv i64 %val0_tmp, %val1_tmp56; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}57 store volatile i64 %val4_tmp, ptr @var64_058 ret void59}60 61define void @sdiv_i64() {62; CHECK-LABEL: sdiv_i64:63 %val0_tmp = load i64, ptr @var64_064 %val1_tmp = load i64, ptr @var64_165 %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp66; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}67 store volatile i64 %val4_tmp, ptr @var64_168 ret void69}70 71 72define void @lsrv_i32() {73; CHECK-LABEL: lsrv_i32:74 %val0_tmp = load i32, ptr @var32_075 %val1_tmp = load i32, ptr @var32_176 %val2_tmp = add i32 1, %val1_tmp77 %val4_tmp = lshr i32 %val0_tmp, %val2_tmp78; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}79 store volatile i32 %val4_tmp, ptr @var32_080 ret void81}82 83define void @lslv_i32() {84; CHECK-LABEL: lslv_i32:85 %val0_tmp = load i32, ptr @var32_086 %val1_tmp = load i32, ptr @var32_187 %val2_tmp = add i32 1, %val1_tmp88 %val4_tmp = shl i32 %val0_tmp, %val2_tmp89; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}90 store volatile i32 %val4_tmp, ptr @var32_191 ret void92}93 94define void @rorv_i32() {95; CHECK-LABEL: rorv_i32:96 %val0_tmp = load i32, ptr @var32_097 %val6_tmp = load i32, ptr @var32_198 %val1_tmp = add i32 1, %val6_tmp99 %val2_tmp = sub i32 32, %val1_tmp100 %val3_tmp = shl i32 %val0_tmp, %val2_tmp101 %val4_tmp = lshr i32 %val0_tmp, %val1_tmp102 %val5_tmp = or i32 %val3_tmp, %val4_tmp103; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}104 store volatile i32 %val5_tmp, ptr @var32_0105 ret void106}107 108define void @asrv_i32() {109; CHECK-LABEL: asrv_i32:110 %val0_tmp = load i32, ptr @var32_0111 %val1_tmp = load i32, ptr @var32_1112 %val2_tmp = add i32 1, %val1_tmp113 %val4_tmp = ashr i32 %val0_tmp, %val2_tmp114; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}115 store volatile i32 %val4_tmp, ptr @var32_1116 ret void117}118 119define void @sdiv_i32() {120; CHECK-LABEL: sdiv_i32:121 %val0_tmp = load i32, ptr @var32_0122 %val1_tmp = load i32, ptr @var32_1123 %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp124; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}125 store volatile i32 %val4_tmp, ptr @var32_1126 ret void127}128 129define void @udiv_i32() {130; CHECK-LABEL: udiv_i32:131 %val0_tmp = load i32, ptr @var32_0132 %val1_tmp = load i32, ptr @var32_1133 %val4_tmp = udiv i32 %val0_tmp, %val1_tmp134; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}135 store volatile i32 %val4_tmp, ptr @var32_0136 ret void137}138 139; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))140; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.141define i32 @test_lsl32() {142; CHECK-LABEL: test_lsl32:143 144 %val = load i32, ptr @var32_0145 %ret = shl i32 1, %val146; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}147 148 ret i32 %ret149}150 151define i32 @test_lsr32() {152; CHECK-LABEL: test_lsr32:153 154 %val = load i32, ptr @var32_0155 %ret = lshr i32 1, %val156; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}157 158 ret i32 %ret159}160 161define i32 @test_asr32(i32 %in) {162; CHECK-LABEL: test_asr32:163 164 %val = load i32, ptr @var32_0165 %ret = ashr i32 %in, %val166; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}167 168 ret i32 %ret169}170