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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=early-ifcvt -stress-early-ifcvt -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=aarch64-- -passes=early-ifcvt -stress-early-ifcvt %s -o - | FileCheck %s4 5---6name: fmov07tracksRegLiveness: true8registers:9 - { id: 0, class: fpr32, preferred-register: '' }10 - { id: 1, class: fpr32, preferred-register: '' }11 - { id: 2, class: fpr32, preferred-register: '' }12 - { id: 3, class: fpr32, preferred-register: '' }13 - { id: 4, class: fpr32, preferred-register: '' }14 - { id: 5, class: gpr32common, preferred-register: '' }15 - { id: 6, class: gpr32, preferred-register: '' }16 - { id: 7, class: fpr32, preferred-register: '' }17 - { id: 8, class: fpr32, preferred-register: '' }18liveins:19 - { reg: '$s1', virtual-reg: '%4' }20 - { reg: '$w0', virtual-reg: '%5' }21body: |22 ; CHECK-LABEL: name: fmov023 ; CHECK: bb.0.entry:24 ; CHECK: liveins: $s1, $w025 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w026 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s127 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv28 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS029 ; CHECK: [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS030 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[FMOVS0_]]31 ; CHECK: $s0 = COPY [[COPY2]]32 ; CHECK: RET_ReallyLR implicit $s033 bb.0.entry:34 successors: %bb.1, %bb.235 liveins: $s1, $w036 37 %5:gpr32common = COPY $w038 %4:fpr32 = COPY $s139 %6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv40 Bcc 1, %bb.2, implicit $nzcv41 B %bb.142 43 bb.1:44 successors: %bb.345 46 %0:fpr32 = FMOVS047 B %bb.348 49 bb.2:50 successors: %bb.351 52 %1:fpr32 = FMOVS053 54 bb.3:55 %2:fpr32 = PHI %1, %bb.2, %0, %bb.156 $s0 = COPY %257 RET_ReallyLR implicit $s058 59...60---61name: fmov0_extrapred62tracksRegLiveness: true63registers:64 - { id: 0, class: fpr32, preferred-register: '' }65 - { id: 1, class: fpr32, preferred-register: '' }66 - { id: 2, class: fpr32, preferred-register: '' }67 - { id: 3, class: fpr32, preferred-register: '' }68 - { id: 4, class: fpr32, preferred-register: '' }69 - { id: 5, class: gpr32common, preferred-register: '' }70 - { id: 6, class: gpr32, preferred-register: '' }71 - { id: 7, class: fpr32, preferred-register: '' }72 - { id: 8, class: fpr32, preferred-register: '' }73liveins:74 - { reg: '$s1', virtual-reg: '%4' }75 - { reg: '$w0', virtual-reg: '%5' }76body: |77 ; CHECK-LABEL: name: fmov0_extrapred78 ; CHECK: bb.0.entry:79 ; CHECK: successors: %bb.4(0x80000000)80 ; CHECK: liveins: $s1, $w081 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w082 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s183 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv84 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS085 ; CHECK: [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS086 ; CHECK: B %bb.487 ; CHECK: bb.1:88 ; CHECK: successors: %bb.4(0x80000000)89 ; CHECK: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF90 ; CHECK: B %bb.491 ; CHECK: bb.4:92 ; CHECK: [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.0, [[DEF]], %bb.193 ; CHECK: $s0 = COPY [[PHI]]94 ; CHECK: RET_ReallyLR implicit $s095 bb.0.entry:96 successors: %bb.1, %bb.297 liveins: $s1, $w098 99 %5:gpr32common = COPY $w0100 %4:fpr32 = COPY $s1101 %6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv102 Bcc 1, %bb.2, implicit $nzcv103 B %bb.1104 105 bb.4:106 successors: %bb.3107 108 ; Make sure we also handle the case when there are extra predecessors on109 ; the tail block.110 %3:fpr32 = IMPLICIT_DEF111 B %bb.3112 113 bb.1:114 successors: %bb.3115 116 %0:fpr32 = FMOVS0117 B %bb.3118 119 bb.2:120 successors: %bb.3121 122 %1:fpr32 = FMOVS0123 124 bb.3:125 %2:fpr32 = PHI %1, %bb.2, %0, %bb.1, %3, %bb.4126 $s0 = COPY %2127 RET_ReallyLR implicit $s0128 129...130---131name: copy_physreg132tracksRegLiveness: true133registers:134 - { id: 0, class: fpr32, preferred-register: '' }135 - { id: 1, class: fpr32, preferred-register: '' }136 - { id: 2, class: fpr32, preferred-register: '' }137 - { id: 3, class: fpr32, preferred-register: '' }138 - { id: 4, class: fpr32, preferred-register: '' }139 - { id: 5, class: gpr32common, preferred-register: '' }140 - { id: 6, class: gpr32, preferred-register: '' }141 - { id: 7, class: fpr32, preferred-register: '' }142 - { id: 8, class: fpr32, preferred-register: '' }143 - { id: 9, class: fpr32, preferred-register: '' }144 - { id: 10, class: fpr32, preferred-register: '' }145liveins:146 - { reg: '$s1', virtual-reg: '%4' }147 - { reg: '$w0', virtual-reg: '%5' }148body: |149 ; CHECK-LABEL: name: copy_physreg150 ; CHECK: bb.0.entry:151 ; CHECK: liveins: $s1, $w0152 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0153 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1154 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv155 ; CHECK: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF implicit-def $s1156 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1157 ; CHECK: [[DEF1:%[0-9]+]]:fpr32 = IMPLICIT_DEF implicit-def $s1158 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1159 ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY2]], [[COPY3]], 1, implicit $nzcv160 ; CHECK: $s0 = COPY [[FCSELSrrr]]161 ; CHECK: RET_ReallyLR implicit $s0162 bb.0.entry:163 successors: %bb.1, %bb.2164 liveins: $s1, $w0165 166 %5:gpr32common = COPY $w0167 %4:fpr32 = COPY $s1168 %6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv169 Bcc 1, %bb.2, implicit $nzcv170 B %bb.1171 172 bb.1:173 successors: %bb.3174 175 %9:fpr32 = IMPLICIT_DEF implicit-def $s1176 %0:fpr32 = COPY $s1177 B %bb.3178 179 bb.2:180 successors: %bb.3181 182 %10:fpr32 = IMPLICIT_DEF implicit-def $s1183 %1:fpr32 = COPY $s1184 185 bb.3:186 %2:fpr32 = PHI %1, %bb.2, %0, %bb.1187 $s0 = COPY %2188 RET_ReallyLR implicit $s0189 190...191---192name: same_def_different_operand193tracksRegLiveness: true194registers:195 - { id: 0, class: fpr32, preferred-register: '' }196 - { id: 1, class: fpr32, preferred-register: '' }197 - { id: 2, class: gpr64common, preferred-register: '' }198 - { id: 3, class: fpr32, preferred-register: '' }199 - { id: 4, class: fpr32, preferred-register: '' }200 - { id: 5, class: gpr32common, preferred-register: '' }201 - { id: 6, class: gpr32, preferred-register: '' }202 - { id: 7, class: fpr32, preferred-register: '' }203 - { id: 8, class: fpr32, preferred-register: '' }204 - { id: 9, class: gpr64common, preferred-register: '' }205 - { id: 10, class: gpr64, preferred-register: '' }206 - { id: 11, class: gpr64common, preferred-register: '' }207liveins:208 - { reg: '$s1', virtual-reg: '%4' }209 - { reg: '$w0', virtual-reg: '%5' }210 - { reg: '$x2', virtual-reg: '%9' }211body: |212 ; CHECK-LABEL: name: same_def_different_operand213 ; CHECK: bb.0.entry:214 ; CHECK: liveins: $s1, $w0, $x2215 ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0216 ; CHECK: early-clobber %11:gpr64common, %10:gpr64 = LDRXpre [[COPY]], 16217 ; CHECK: [[COPY1:%[0-9]+]]:gpr32common = COPY $w0218 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1219 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 1, 0, implicit-def $nzcv220 ; CHECK: [[CSELXr:%[0-9]+]]:gpr64common = CSELXr %11, %10, 1, implicit $nzcv221 ; CHECK: $x2 = COPY [[CSELXr]]222 ; CHECK: RET_ReallyLR implicit $x2223 bb.0.entry:224 successors: %bb.1, %bb.2225 liveins: $s1, $w0, $x2226 227 %9:gpr64common = COPY $x0228 early-clobber %11:gpr64common, %10:gpr64 = LDRXpre %9:gpr64common, 16229 230 %5:gpr32common = COPY $w0231 %4:fpr32 = COPY $s1232 %6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv233 Bcc 1, %bb.2, implicit $nzcv234 B %bb.1235 236 bb.1:237 successors: %bb.3238 239 B %bb.3240 241 bb.2:242 successors: %bb.3243 244 B %bb.3245 246 bb.3:247 %2:gpr64common = PHI %11, %bb.2, %10, %bb.1248 $x2 = COPY %2249 RET_ReallyLR implicit $x2250 251...252