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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <2 x i32> @and_extract_zext_idx0(<4 x i16> %vec) nounwind {6; CHECK-SD-LABEL: and_extract_zext_idx0:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #09; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q010; CHECK-SD-NEXT: ret11;12; CHECK-GI-LABEL: and_extract_zext_idx0:13; CHECK-GI: // %bb.0:14; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff15; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #016; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b17; CHECK-GI-NEXT: ret18 %zext = zext <4 x i16> %vec to <4 x i32>19 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)20 %and = and <2 x i32> %extract, <i32 65535, i32 65535>21 ret <2 x i32> %and22}23 24define <4 x i16> @and_extract_sext_idx0(<8 x i8> %vec) nounwind {25; CHECK-SD-LABEL: and_extract_sext_idx0:26; CHECK-SD: // %bb.0:27; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #028; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q029; CHECK-SD-NEXT: ret30;31; CHECK-GI-LABEL: and_extract_sext_idx0:32; CHECK-GI: // %bb.0:33; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff34; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #035; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b36; CHECK-GI-NEXT: ret37 %sext = sext <8 x i8> %vec to <8 x i16>38 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)39 %and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>40 ret <4 x i16> %and41}42 43define <2 x i32> @and_extract_zext_idx2(<4 x i16> %vec) nounwind {44; CHECK-SD-LABEL: and_extract_zext_idx2:45; CHECK-SD: // %bb.0:46; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #047; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #848; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q049; CHECK-SD-NEXT: ret50;51; CHECK-GI-LABEL: and_extract_zext_idx2:52; CHECK-GI: // %bb.0:53; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #054; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff55; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #856; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b57; CHECK-GI-NEXT: ret58 %zext = zext <4 x i16> %vec to <4 x i32>59 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)60 %and = and <2 x i32> %extract, <i32 65535, i32 65535>61 ret <2 x i32> %and62}63 64define <4 x i16> @and_extract_sext_idx4(<8 x i8> %vec) nounwind {65; CHECK-SD-LABEL: and_extract_sext_idx4:66; CHECK-SD: // %bb.0:67; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #068; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #869; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q070; CHECK-SD-NEXT: ret71;72; CHECK-GI-LABEL: and_extract_sext_idx4:73; CHECK-GI: // %bb.0:74; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #075; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff76; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #877; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b78; CHECK-GI-NEXT: ret79 %sext = sext <8 x i8> %vec to <8 x i16>80 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)81 %and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>82 ret <4 x i16> %and83}84 85define <2 x i32> @sext_extract_zext_idx0(<4 x i16> %vec) nounwind {86; CHECK-SD-LABEL: sext_extract_zext_idx0:87; CHECK-SD: // %bb.0:88; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #089; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q090; CHECK-SD-NEXT: ret91;92; CHECK-GI-LABEL: sext_extract_zext_idx0:93; CHECK-GI: // %bb.0:94; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #095; CHECK-GI-NEXT: shl v0.2s, v0.2s, #1696; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #1697; CHECK-GI-NEXT: ret98 %zext = zext <4 x i16> %vec to <4 x i32>99 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)100 %sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>101 %sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>102 ret <2 x i32> %sext_inreg103}104 105; Negative test, combine should not fire if sign extension is for a different width.106define <2 x i32> @sext_extract_zext_idx0_negtest(<4 x i16> %vec) nounwind {107; CHECK-SD-LABEL: sext_extract_zext_idx0_negtest:108; CHECK-SD: // %bb.0:109; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h110; CHECK-SD-NEXT: shl v0.2s, v0.2s, #17111; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #17112; CHECK-SD-NEXT: ret113;114; CHECK-GI-LABEL: sext_extract_zext_idx0_negtest:115; CHECK-GI: // %bb.0:116; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0117; CHECK-GI-NEXT: shl v0.2s, v0.2s, #17118; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17119; CHECK-GI-NEXT: ret120 %zext = zext <4 x i16> %vec to <4 x i32>121 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)122 %sext_inreg_step0 = shl <2 x i32> %extract, <i32 17, i32 17>123 %sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 17, i32 17>124 ret <2 x i32> %sext_inreg125}126 127define <4 x i16> @sext_extract_sext_idx0(<8 x i8> %vec) nounwind {128; CHECK-SD-LABEL: sext_extract_sext_idx0:129; CHECK-SD: // %bb.0:130; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0131; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0132; CHECK-SD-NEXT: ret133;134; CHECK-GI-LABEL: sext_extract_sext_idx0:135; CHECK-GI: // %bb.0:136; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0137; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8138; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8139; CHECK-GI-NEXT: ret140 %sext = sext <8 x i8> %vec to <8 x i16>141 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)142 %sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>143 %sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>144 ret <4 x i16> %sext_inreg145}146 147define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {148; CHECK-SD-LABEL: sext_extract_zext_idx2:149; CHECK-SD: // %bb.0:150; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0151; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8152; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0153; CHECK-SD-NEXT: ret154;155; CHECK-GI-LABEL: sext_extract_zext_idx2:156; CHECK-GI: // %bb.0:157; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0158; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8159; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16160; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16161; CHECK-GI-NEXT: ret162 %zext = zext <4 x i16> %vec to <4 x i32>163 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)164 %sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>165 %sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>166 ret <2 x i32> %sext_inreg167}168 169define <4 x i16> @sext_extract_sext_idx4(<8 x i8> %vec) nounwind {170; CHECK-SD-LABEL: sext_extract_sext_idx4:171; CHECK-SD: // %bb.0:172; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0173; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8174; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0175; CHECK-SD-NEXT: ret176;177; CHECK-GI-LABEL: sext_extract_sext_idx4:178; CHECK-GI: // %bb.0:179; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0180; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8181; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8182; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8183; CHECK-GI-NEXT: ret184 %sext = sext <8 x i8> %vec to <8 x i16>185 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)186 %sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>187 %sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>188 ret <4 x i16> %sext_inreg189}190 191define <8 x i8> @sext_extract_idx(<16 x i8> %vec) nounwind {192; CHECK-LABEL: sext_extract_idx:193; CHECK: // %bb.0:194; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0195; CHECK-NEXT: ret196 %extract = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %vec, i64 0)197 ret <8 x i8> %extract198}199 200declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)201declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)202declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)203