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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for insert_vscale_8_i16_zero6; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_8_i167; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_16_i8_zero8; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_16_i89; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_vscale_16_i810; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_vscale_16_i8_zero11 12define <vscale x 2 x i64> @insert_vscale_2_i64_zero(<vscale x 2 x i64> %vec, i64 %elt) {13; CHECK-SD-LABEL: insert_vscale_2_i64_zero:14; CHECK-SD: // %bb.0: // %entry15; CHECK-SD-NEXT: ptrue p0.d, vl116; CHECK-SD-NEXT: mov z0.d, p0/m, x017; CHECK-SD-NEXT: ret18;19; CHECK-GI-LABEL: insert_vscale_2_i64_zero:20; CHECK-GI: // %bb.0: // %entry21; CHECK-GI-NEXT: mov x8, xzr22; CHECK-GI-NEXT: index z1.d, #0, #123; CHECK-GI-NEXT: ptrue p0.d24; CHECK-GI-NEXT: mov z2.d, x825; CHECK-GI-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d26; CHECK-GI-NEXT: mov z0.d, p0/m, x027; CHECK-GI-NEXT: ret28entry:29 %d = insertelement <vscale x 2 x i64> %vec, i64 %elt, i64 030 ret <vscale x 2 x i64> %d31}32 33define <vscale x 2 x i64> @insert_vscale_2_i64(<vscale x 2 x i64> %vec, i64 %elt, i64 %idx) {34; CHECK-LABEL: insert_vscale_2_i64:35; CHECK: // %bb.0: // %entry36; CHECK-NEXT: index z1.d, #0, #137; CHECK-NEXT: mov z2.d, x138; CHECK-NEXT: ptrue p0.d39; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d40; CHECK-NEXT: mov z0.d, p0/m, x041; CHECK-NEXT: ret42entry:43 %d = insertelement <vscale x 2 x i64> %vec, i64 %elt, i64 %idx44 ret <vscale x 2 x i64> %d45}46 47define <vscale x 4 x i32> @insert_vscale_4_i32_zero(<vscale x 4 x i32> %vec, i32 %elt) {48; CHECK-SD-LABEL: insert_vscale_4_i32_zero:49; CHECK-SD: // %bb.0: // %entry50; CHECK-SD-NEXT: ptrue p0.s, vl151; CHECK-SD-NEXT: mov z0.s, p0/m, w052; CHECK-SD-NEXT: ret53;54; CHECK-GI-LABEL: insert_vscale_4_i32_zero:55; CHECK-GI: // %bb.0: // %entry56; CHECK-GI-NEXT: mov w8, wzr57; CHECK-GI-NEXT: index z1.s, #0, #158; CHECK-GI-NEXT: ptrue p0.s59; CHECK-GI-NEXT: mov z2.s, w860; CHECK-GI-NEXT: cmpeq p0.s, p0/z, z1.s, z2.s61; CHECK-GI-NEXT: mov z0.s, p0/m, w062; CHECK-GI-NEXT: ret63entry:64 %d = insertelement <vscale x 4 x i32> %vec, i32 %elt, i64 065 ret <vscale x 4 x i32> %d66}67 68define <vscale x 4 x i32> @insert_vscale_4_i32(<vscale x 4 x i32> %vec, i32 %elt, i64 %idx) {69; CHECK-LABEL: insert_vscale_4_i32:70; CHECK: // %bb.0: // %entry71; CHECK-NEXT: index z1.s, #0, #172; CHECK-NEXT: mov z2.s, w173; CHECK-NEXT: ptrue p0.s74; CHECK-NEXT: cmpeq p0.s, p0/z, z1.s, z2.s75; CHECK-NEXT: mov z0.s, p0/m, w076; CHECK-NEXT: ret77entry:78 %d = insertelement <vscale x 4 x i32> %vec, i32 %elt, i64 %idx79 ret <vscale x 4 x i32> %d80}81 82define <vscale x 8 x i16> @insert_vscale_8_i16_zero(<vscale x 8 x i16> %vec, i16 %elt) {83; CHECK-LABEL: insert_vscale_8_i16_zero:84; CHECK: // %bb.0: // %entry85; CHECK-NEXT: ptrue p0.h, vl186; CHECK-NEXT: mov z0.h, p0/m, w087; CHECK-NEXT: ret88entry:89 %d = insertelement <vscale x 8 x i16> %vec, i16 %elt, i64 090 ret <vscale x 8 x i16> %d91}92 93define <vscale x 8 x i16> @insert_vscale_8_i16(<vscale x 8 x i16> %vec, i16 %elt, i64 %idx) {94; CHECK-LABEL: insert_vscale_8_i16:95; CHECK: // %bb.0: // %entry96; CHECK-NEXT: index z1.h, #0, #197; CHECK-NEXT: mov z2.h, w198; CHECK-NEXT: ptrue p0.h99; CHECK-NEXT: cmpeq p0.h, p0/z, z1.h, z2.h100; CHECK-NEXT: mov z0.h, p0/m, w0101; CHECK-NEXT: ret102entry:103 %d = insertelement <vscale x 8 x i16> %vec, i16 %elt, i64 %idx104 ret <vscale x 8 x i16> %d105}106 107define <vscale x 16 x i8> @insert_vscale_16_i8_zero(<vscale x 16 x i8> %vec, i8 %elt) {108; CHECK-LABEL: insert_vscale_16_i8_zero:109; CHECK: // %bb.0: // %entry110; CHECK-NEXT: ptrue p0.b, vl1111; CHECK-NEXT: mov z0.b, p0/m, w0112; CHECK-NEXT: ret113entry:114 %d = insertelement <vscale x 16 x i8> %vec, i8 %elt, i64 0115 ret <vscale x 16 x i8> %d116}117 118define <vscale x 16 x i8> @insert_vscale_16_i8(<vscale x 16 x i8> %vec, i8 %elt, i64 %idx) {119; CHECK-LABEL: insert_vscale_16_i8:120; CHECK: // %bb.0: // %entry121; CHECK-NEXT: index z1.b, #0, #1122; CHECK-NEXT: mov z2.b, w1123; CHECK-NEXT: ptrue p0.b124; CHECK-NEXT: cmpeq p0.b, p0/z, z1.b, z2.b125; CHECK-NEXT: mov z0.b, p0/m, w0126; CHECK-NEXT: ret127entry:128 %d = insertelement <vscale x 16 x i8> %vec, i8 %elt, i64 %idx129 ret <vscale x 16 x i8> %d130}131 132define i64 @extract_vscale_2_i64(<vscale x 2 x i64> %vec, i64 %idx) {133; CHECK-SD-LABEL: extract_vscale_2_i64:134; CHECK-SD: // %bb.0: // %entry135; CHECK-SD-NEXT: whilels p0.d, xzr, x0136; CHECK-SD-NEXT: lastb x0, p0, z0.d137; CHECK-SD-NEXT: ret138;139; CHECK-GI-LABEL: extract_vscale_2_i64:140; CHECK-GI: // %bb.0: // %entry141; CHECK-GI-NEXT: whilels p0.d, xzr, x0142; CHECK-GI-NEXT: lastb d0, p0, z0.d143; CHECK-GI-NEXT: fmov x0, d0144; CHECK-GI-NEXT: ret145entry:146 %d = extractelement <vscale x 2 x i64> %vec, i64 %idx147 ret i64 %d148}149 150define i64 @extract_vscale_2_i64_zero(<vscale x 2 x i64> %vec, i64 %idx) {151; CHECK-LABEL: extract_vscale_2_i64_zero:152; CHECK: // %bb.0: // %entry153; CHECK-NEXT: fmov x0, d0154; CHECK-NEXT: ret155entry:156 %d = extractelement <vscale x 2 x i64> %vec, i64 0157 ret i64 %d158}159 160define i32 @extract_vscale_4_i32(<vscale x 4 x i32> %vec, i64 %idx) {161; CHECK-SD-LABEL: extract_vscale_4_i32:162; CHECK-SD: // %bb.0: // %entry163; CHECK-SD-NEXT: whilels p0.s, xzr, x0164; CHECK-SD-NEXT: lastb w0, p0, z0.s165; CHECK-SD-NEXT: ret166;167; CHECK-GI-LABEL: extract_vscale_4_i32:168; CHECK-GI: // %bb.0: // %entry169; CHECK-GI-NEXT: whilels p0.s, xzr, x0170; CHECK-GI-NEXT: lastb s0, p0, z0.s171; CHECK-GI-NEXT: fmov w0, s0172; CHECK-GI-NEXT: ret173entry:174 %d = extractelement <vscale x 4 x i32> %vec, i64 %idx175 ret i32 %d176}177 178define i32 @extract_vscale_4_i32_zero(<vscale x 4 x i32> %vec, i64 %idx) {179; CHECK-LABEL: extract_vscale_4_i32_zero:180; CHECK: // %bb.0: // %entry181; CHECK-NEXT: fmov w0, s0182; CHECK-NEXT: ret183entry:184 %d = extractelement <vscale x 4 x i32> %vec, i64 0185 ret i32 %d186}187 188define i16 @extract_vscale_8_i16(<vscale x 8 x i16> %vec, i64 %idx) {189; CHECK-SD-LABEL: extract_vscale_8_i16:190; CHECK-SD: // %bb.0: // %entry191; CHECK-SD-NEXT: whilels p0.h, xzr, x0192; CHECK-SD-NEXT: lastb w0, p0, z0.h193; CHECK-SD-NEXT: ret194;195; CHECK-GI-LABEL: extract_vscale_8_i16:196; CHECK-GI: // %bb.0: // %entry197; CHECK-GI-NEXT: whilels p0.h, xzr, x0198; CHECK-GI-NEXT: lastb h0, p0, z0.h199; CHECK-GI-NEXT: fmov w0, s0200; CHECK-GI-NEXT: ret201entry:202 %d = extractelement <vscale x 8 x i16> %vec, i64 %idx203 ret i16 %d204}205 206define i16 @extract_vscale_8_i16_zero(<vscale x 8 x i16> %vec, i64 %idx) {207; CHECK-LABEL: extract_vscale_8_i16_zero:208; CHECK: // %bb.0: // %entry209; CHECK-NEXT: fmov w0, s0210; CHECK-NEXT: ret211entry:212 %d = extractelement <vscale x 8 x i16> %vec, i64 0213 ret i16 %d214}215 216define i8 @extract_vscale_16_i8(<vscale x 16 x i8> %vec, i64 %idx) {217; CHECK-LABEL: extract_vscale_16_i8:218; CHECK: // %bb.0: // %entry219; CHECK-NEXT: whilels p0.b, xzr, x0220; CHECK-NEXT: lastb w0, p0, z0.b221; CHECK-NEXT: ret222entry:223 %d = extractelement <vscale x 16 x i8> %vec, i64 %idx224 ret i8 %d225}226 227define i8 @extract_vscale_16_i8_zero(<vscale x 16 x i8> %vec, i64 %idx) {228; CHECK-LABEL: extract_vscale_16_i8_zero:229; CHECK: // %bb.0: // %entry230; CHECK-NEXT: fmov w0, s0231; CHECK-NEXT: ret232entry:233 %d = extractelement <vscale x 16 x i8> %vec, i64 0234 ret i8 %d235}236