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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for extract_v4i32_vector_insert6; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_insert_const7; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract8; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract_const9 10define i64 @extract_v2i64_undef_index(<2 x i64> %a, i32 %c) {11; CHECK-SD-LABEL: extract_v2i64_undef_index:12; CHECK-SD: // %bb.0: // %entry13; CHECK-SD-NEXT: fmov x0, d014; CHECK-SD-NEXT: ret15;16; CHECK-GI-LABEL: extract_v2i64_undef_index:17; CHECK-GI: // %bb.0: // %entry18; CHECK-GI-NEXT: str q0, [sp, #-16]!19; CHECK-GI-NEXT: .cfi_def_cfa_offset 1620; CHECK-GI-NEXT: ldr x0, [sp], #1621; CHECK-GI-NEXT: ret22entry:23 %d = extractelement <2 x i64> %a, i32 undef24 ret i64 %d25}26 27define i64 @extract_v2i64_undef_vector(<2 x i64> %a, i32 %c) {28; CHECK-LABEL: extract_v2i64_undef_vector:29; CHECK: // %bb.0: // %entry30; CHECK-NEXT: ret31entry:32 %d = extractelement <2 x i64> undef, i32 %c33 ret i64 %d34}35 36define i64 @extract_v2i64_opaque(<2 x i64> %a, i32 %c) {37; CHECK-SD-LABEL: extract_v2i64_opaque:38; CHECK-SD: // %bb.0: // %entry39; CHECK-SD-NEXT: sub sp, sp, #1640; CHECK-SD-NEXT: .cfi_def_cfa_offset 1641; CHECK-SD-NEXT: mov x8, sp42; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x043; CHECK-SD-NEXT: str q0, [sp]44; CHECK-SD-NEXT: bfi x8, x0, #3, #145; CHECK-SD-NEXT: ldr x0, [x8]46; CHECK-SD-NEXT: add sp, sp, #1647; CHECK-SD-NEXT: ret48;49; CHECK-GI-LABEL: extract_v2i64_opaque:50; CHECK-GI: // %bb.0: // %entry51; CHECK-GI-NEXT: sub sp, sp, #1652; CHECK-GI-NEXT: .cfi_def_cfa_offset 1653; CHECK-GI-NEXT: mov w9, w054; CHECK-GI-NEXT: mov x8, sp55; CHECK-GI-NEXT: str q0, [sp]56; CHECK-GI-NEXT: and x9, x9, #0x157; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]58; CHECK-GI-NEXT: add sp, sp, #1659; CHECK-GI-NEXT: ret60entry:61 %d = extractelement <2 x i64> %a, i32 %c62 ret i64 %d63}64 65define i64 @extract_v2i64_oob(<2 x i64> %a, i32 %c) {66; CHECK-LABEL: extract_v2i64_oob:67; CHECK: // %bb.0: // %entry68; CHECK-NEXT: ret69entry:70 %d = extractelement <2 x i64> %a, i32 571 ret i64 %d72}73 74define i64 @extract_v2i64_freeze(<2 x i64> %a, i32 %c) {75; CHECK-SD-LABEL: extract_v2i64_freeze:76; CHECK-SD: // %bb.0: // %entry77; CHECK-SD-NEXT: sub sp, sp, #1678; CHECK-SD-NEXT: .cfi_def_cfa_offset 1679; CHECK-SD-NEXT: mov x8, sp80; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x081; CHECK-SD-NEXT: str q0, [sp]82; CHECK-SD-NEXT: bfi x8, x0, #3, #183; CHECK-SD-NEXT: ldr x0, [x8]84; CHECK-SD-NEXT: add sp, sp, #1685; CHECK-SD-NEXT: ret86;87; CHECK-GI-LABEL: extract_v2i64_freeze:88; CHECK-GI: // %bb.0: // %entry89; CHECK-GI-NEXT: sub sp, sp, #1690; CHECK-GI-NEXT: .cfi_def_cfa_offset 1691; CHECK-GI-NEXT: mov w9, w092; CHECK-GI-NEXT: mov x8, sp93; CHECK-GI-NEXT: str q0, [sp]94; CHECK-GI-NEXT: and x9, x9, #0x195; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]96; CHECK-GI-NEXT: add sp, sp, #1697; CHECK-GI-NEXT: ret98entry:99 %fvector = freeze <2 x i64> %a100 %d = extractelement <2 x i64> %fvector, i32 %c101 ret i64 %d102}103 104define i64 @extract_v2i64_extract_of_insert(<2 x i64> %a, i64 %element, i64 %c) {105; CHECK-LABEL: extract_v2i64_extract_of_insert:106; CHECK: // %bb.0: // %entry107; CHECK-NEXT: ret108entry:109 %vector = insertelement <2 x i64> %a, i64 %element, i64 %c110 %d = extractelement <2 x i64> %vector, i64 %c111 ret i64 %d112}113 114define i64 @extract_v2i64_extract_of_insert_different_const(<2 x i64> %a, i64 %element) {115; CHECK-SD-LABEL: extract_v2i64_extract_of_insert_different_const:116; CHECK-SD: // %bb.0: // %entry117; CHECK-SD-NEXT: mov x0, v0.d[1]118; CHECK-SD-NEXT: ret119;120; CHECK-GI-LABEL: extract_v2i64_extract_of_insert_different_const:121; CHECK-GI: // %bb.0: // %entry122; CHECK-GI-NEXT: mov d0, v0.d[1]123; CHECK-GI-NEXT: fmov x0, d0124; CHECK-GI-NEXT: ret125entry:126 %vector = insertelement <2 x i64> %a, i64 %element, i64 0127 %d = extractelement <2 x i64> %vector, i64 1128 ret i64 %d129}130 131define i64 @extract_v2i64_extract_build_vector_const(<2 x i64> %a, i32 %c) {132; CHECK-LABEL: extract_v2i64_extract_build_vector_const:133; CHECK: // %bb.0: // %entry134; CHECK-NEXT: mov w0, #11 // =0xb135; CHECK-NEXT: ret136entry:137 %d = extractelement <2 x i64> <i64 42, i64 11>, i32 1138 ret i64 %d139}140 141define i64 @extract_v2i64_extract_build_vector_opaque(<2 x i64> %a, i32 %c) {142; CHECK-SD-LABEL: extract_v2i64_extract_build_vector_opaque:143; CHECK-SD: // %bb.0: // %entry144; CHECK-SD-NEXT: sub sp, sp, #16145; CHECK-SD-NEXT: .cfi_def_cfa_offset 16146; CHECK-SD-NEXT: adrp x8, .LCPI8_0147; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0148; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI8_0]149; CHECK-SD-NEXT: mov x8, sp150; CHECK-SD-NEXT: bfi x8, x0, #3, #1151; CHECK-SD-NEXT: str q0, [sp]152; CHECK-SD-NEXT: ldr x0, [x8]153; CHECK-SD-NEXT: add sp, sp, #16154; CHECK-SD-NEXT: ret155;156; CHECK-GI-LABEL: extract_v2i64_extract_build_vector_opaque:157; CHECK-GI: // %bb.0: // %entry158; CHECK-GI-NEXT: sub sp, sp, #16159; CHECK-GI-NEXT: .cfi_def_cfa_offset 16160; CHECK-GI-NEXT: adrp x8, .LCPI8_0161; CHECK-GI-NEXT: mov x9, sp162; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI8_0]163; CHECK-GI-NEXT: mov w8, w0164; CHECK-GI-NEXT: and x8, x8, #0x1165; CHECK-GI-NEXT: str q0, [sp]166; CHECK-GI-NEXT: ldr x0, [x9, x8, lsl #3]167; CHECK-GI-NEXT: add sp, sp, #16168; CHECK-GI-NEXT: ret169entry:170 %d = extractelement <2 x i64> <i64 42, i64 11>, i32 %c171 ret i64 %d172}173 174 175define i64 @extract_v2i32_zext(<2 x i32> %a, i32 %c) {176; CHECK-SD-LABEL: extract_v2i32_zext:177; CHECK-SD: // %bb.0: // %entry178; CHECK-SD-NEXT: sub sp, sp, #16179; CHECK-SD-NEXT: .cfi_def_cfa_offset 16180; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0181; CHECK-SD-NEXT: mov x8, sp182; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0183; CHECK-SD-NEXT: bfi x8, x0, #3, #1184; CHECK-SD-NEXT: str q0, [sp]185; CHECK-SD-NEXT: ldr x0, [x8]186; CHECK-SD-NEXT: add sp, sp, #16187; CHECK-SD-NEXT: ret188;189; CHECK-GI-LABEL: extract_v2i32_zext:190; CHECK-GI: // %bb.0: // %entry191; CHECK-GI-NEXT: sub sp, sp, #16192; CHECK-GI-NEXT: .cfi_def_cfa_offset 16193; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0194; CHECK-GI-NEXT: mov w9, w0195; CHECK-GI-NEXT: mov x8, sp196; CHECK-GI-NEXT: and x9, x9, #0x1197; CHECK-GI-NEXT: str q0, [sp]198; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]199; CHECK-GI-NEXT: add sp, sp, #16200; CHECK-GI-NEXT: ret201entry:202 %zvector = zext <2 x i32> %a to <2 x i64>203 %d = extractelement <2 x i64> %zvector, i32 %c204 ret i64 %d205}206 207define i64 @extract_v2double_fptosi(<2 x double> %a, i32 %c) {208; CHECK-SD-LABEL: extract_v2double_fptosi:209; CHECK-SD: // %bb.0: // %entry210; CHECK-SD-NEXT: sub sp, sp, #16211; CHECK-SD-NEXT: .cfi_def_cfa_offset 16212; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d213; CHECK-SD-NEXT: mov x8, sp214; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0215; CHECK-SD-NEXT: bfi x8, x0, #3, #1216; CHECK-SD-NEXT: str q0, [sp]217; CHECK-SD-NEXT: ldr x0, [x8]218; CHECK-SD-NEXT: add sp, sp, #16219; CHECK-SD-NEXT: ret220;221; CHECK-GI-LABEL: extract_v2double_fptosi:222; CHECK-GI: // %bb.0: // %entry223; CHECK-GI-NEXT: sub sp, sp, #16224; CHECK-GI-NEXT: .cfi_def_cfa_offset 16225; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d226; CHECK-GI-NEXT: mov w9, w0227; CHECK-GI-NEXT: mov x8, sp228; CHECK-GI-NEXT: and x9, x9, #0x1229; CHECK-GI-NEXT: str q0, [sp]230; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]231; CHECK-GI-NEXT: add sp, sp, #16232; CHECK-GI-NEXT: ret233entry:234 %vector = fptosi <2 x double> %a to <2 x i64>235 %d = extractelement <2 x i64> %vector, i32 %c236 ret i64 %d237}238 239define double @extract_v2double_fneg(<2 x double> %a, i32 %c) {240; CHECK-SD-LABEL: extract_v2double_fneg:241; CHECK-SD: // %bb.0: // %entry242; CHECK-SD-NEXT: sub sp, sp, #16243; CHECK-SD-NEXT: .cfi_def_cfa_offset 16244; CHECK-SD-NEXT: fneg v0.2d, v0.2d245; CHECK-SD-NEXT: mov x8, sp246; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0247; CHECK-SD-NEXT: bfi x8, x0, #3, #1248; CHECK-SD-NEXT: str q0, [sp]249; CHECK-SD-NEXT: ldr d0, [x8]250; CHECK-SD-NEXT: add sp, sp, #16251; CHECK-SD-NEXT: ret252;253; CHECK-GI-LABEL: extract_v2double_fneg:254; CHECK-GI: // %bb.0: // %entry255; CHECK-GI-NEXT: sub sp, sp, #16256; CHECK-GI-NEXT: .cfi_def_cfa_offset 16257; CHECK-GI-NEXT: fneg v0.2d, v0.2d258; CHECK-GI-NEXT: mov w9, w0259; CHECK-GI-NEXT: mov x8, sp260; CHECK-GI-NEXT: and x9, x9, #0x1261; CHECK-GI-NEXT: str q0, [sp]262; CHECK-GI-NEXT: ldr d0, [x8, x9, lsl #3]263; CHECK-GI-NEXT: add sp, sp, #16264; CHECK-GI-NEXT: ret265entry:266 %vector = fneg <2 x double> %a267 %d = extractelement <2 x double> %vector, i32 %c268 ret double %d269}270 271define i32 @extract_v4i32_add(<4 x i32> %a, <4 x i32> %b, i32 %c) {272; CHECK-SD-LABEL: extract_v4i32_add:273; CHECK-SD: // %bb.0: // %entry274; CHECK-SD-NEXT: sub sp, sp, #16275; CHECK-SD-NEXT: .cfi_def_cfa_offset 16276; CHECK-SD-NEXT: adrp x8, .LCPI12_0277; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0278; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]279; CHECK-SD-NEXT: mov x8, sp280; CHECK-SD-NEXT: bfi x8, x0, #2, #2281; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s282; CHECK-SD-NEXT: str q0, [sp]283; CHECK-SD-NEXT: ldr w0, [x8]284; CHECK-SD-NEXT: add sp, sp, #16285; CHECK-SD-NEXT: ret286;287; CHECK-GI-LABEL: extract_v4i32_add:288; CHECK-GI: // %bb.0: // %entry289; CHECK-GI-NEXT: sub sp, sp, #16290; CHECK-GI-NEXT: .cfi_def_cfa_offset 16291; CHECK-GI-NEXT: adrp x8, .LCPI12_0292; CHECK-GI-NEXT: mov x9, sp293; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]294; CHECK-GI-NEXT: mov w8, w0295; CHECK-GI-NEXT: and x8, x8, #0x3296; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s297; CHECK-GI-NEXT: str q0, [sp]298; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]299; CHECK-GI-NEXT: add sp, sp, #16300; CHECK-GI-NEXT: ret301entry:302 %vector = add <4 x i32> %a, <i32 42, i32 11, i32 17, i32 6>303 %d = extractelement <4 x i32> %vector, i32 %c304 ret i32 %d305}306 307define float @extract_v4i32_minimum(<4 x float> %a, <4 x float> %b, i32 %c) {308; CHECK-SD-LABEL: extract_v4i32_minimum:309; CHECK-SD: // %bb.0: // %entry310; CHECK-SD-NEXT: sub sp, sp, #16311; CHECK-SD-NEXT: .cfi_def_cfa_offset 16312; CHECK-SD-NEXT: fmin v0.4s, v0.4s, v1.4s313; CHECK-SD-NEXT: mov x8, sp314; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0315; CHECK-SD-NEXT: bfi x8, x0, #2, #2316; CHECK-SD-NEXT: str q0, [sp]317; CHECK-SD-NEXT: ldr s0, [x8]318; CHECK-SD-NEXT: add sp, sp, #16319; CHECK-SD-NEXT: ret320;321; CHECK-GI-LABEL: extract_v4i32_minimum:322; CHECK-GI: // %bb.0: // %entry323; CHECK-GI-NEXT: sub sp, sp, #16324; CHECK-GI-NEXT: .cfi_def_cfa_offset 16325; CHECK-GI-NEXT: fmin v0.4s, v0.4s, v1.4s326; CHECK-GI-NEXT: mov w8, w0327; CHECK-GI-NEXT: mov x9, sp328; CHECK-GI-NEXT: and x8, x8, #0x3329; CHECK-GI-NEXT: str q0, [sp]330; CHECK-GI-NEXT: ldr s0, [x9, x8, lsl #2]331; CHECK-GI-NEXT: add sp, sp, #16332; CHECK-GI-NEXT: ret333entry:334 %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)335 %d = extractelement <4 x float> %vector, i32 %c336 ret float %d337}338 339define float @extract_v4i32_minimum_build_vector(<4 x float> %a, <4 x float> %b, i32 %c) {340; CHECK-SD-LABEL: extract_v4i32_minimum_build_vector:341; CHECK-SD: // %bb.0: // %entry342; CHECK-SD-NEXT: sub sp, sp, #16343; CHECK-SD-NEXT: .cfi_def_cfa_offset 16344; CHECK-SD-NEXT: adrp x8, .LCPI14_0345; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0346; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]347; CHECK-SD-NEXT: mov x8, sp348; CHECK-SD-NEXT: bfi x8, x0, #2, #2349; CHECK-SD-NEXT: fmin v0.4s, v0.4s, v1.4s350; CHECK-SD-NEXT: str q0, [sp]351; CHECK-SD-NEXT: ldr s0, [x8]352; CHECK-SD-NEXT: add sp, sp, #16353; CHECK-SD-NEXT: ret354;355; CHECK-GI-LABEL: extract_v4i32_minimum_build_vector:356; CHECK-GI: // %bb.0: // %entry357; CHECK-GI-NEXT: sub sp, sp, #16358; CHECK-GI-NEXT: .cfi_def_cfa_offset 16359; CHECK-GI-NEXT: adrp x8, .LCPI14_0360; CHECK-GI-NEXT: mov x9, sp361; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]362; CHECK-GI-NEXT: mov w8, w0363; CHECK-GI-NEXT: and x8, x8, #0x3364; CHECK-GI-NEXT: fmin v0.4s, v0.4s, v1.4s365; CHECK-GI-NEXT: str q0, [sp]366; CHECK-GI-NEXT: ldr s0, [x9, x8, lsl #2]367; CHECK-GI-NEXT: add sp, sp, #16368; CHECK-GI-NEXT: ret369entry:370 %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)371 %d = extractelement <4 x float> %vector, i32 %c372 ret float %d373}374 375define float @extract_v4i32_minimum_build_vector_const(<4 x float> %a, <4 x float> %b, i32 %c) {376; CHECK-LABEL: extract_v4i32_minimum_build_vector_const:377; CHECK: // %bb.0: // %entry378; CHECK-NEXT: adrp x8, .LCPI15_0379; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]380; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s381; CHECK-NEXT: mov s0, v0.s[1]382; CHECK-NEXT: ret383entry:384 %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)385 %d = extractelement <4 x float> %vector, i32 1386 ret float %d387}388 389define float @extract_v4i32_copysign_build_vector(<4 x float> %a, <4 x float> %b, i32 %c) {390; CHECK-SD-LABEL: extract_v4i32_copysign_build_vector:391; CHECK-SD: // %bb.0: // %entry392; CHECK-SD-NEXT: sub sp, sp, #16393; CHECK-SD-NEXT: .cfi_def_cfa_offset 16394; CHECK-SD-NEXT: fabs v0.4s, v0.4s395; CHECK-SD-NEXT: mov x8, sp396; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0397; CHECK-SD-NEXT: bfi x8, x0, #2, #2398; CHECK-SD-NEXT: str q0, [sp]399; CHECK-SD-NEXT: ldr s0, [x8]400; CHECK-SD-NEXT: add sp, sp, #16401; CHECK-SD-NEXT: ret402;403; CHECK-GI-LABEL: extract_v4i32_copysign_build_vector:404; CHECK-GI: // %bb.0: // %entry405; CHECK-GI-NEXT: sub sp, sp, #16406; CHECK-GI-NEXT: .cfi_def_cfa_offset 16407; CHECK-GI-NEXT: mvni v1.4s, #128, lsl #24408; CHECK-GI-NEXT: mov w8, w0409; CHECK-GI-NEXT: mov x9, sp410; CHECK-GI-NEXT: and x8, x8, #0x3411; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b412; CHECK-GI-NEXT: str q0, [sp]413; CHECK-GI-NEXT: ldr s0, [x9, x8, lsl #2]414; CHECK-GI-NEXT: add sp, sp, #16415; CHECK-GI-NEXT: ret416entry:417 %vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)418 %d = extractelement <4 x float> %vector, i32 %c419 ret float %d420}421 422define float @extract_v4i32_copysign_build_vector_const(<4 x float> %a, <4 x float> %b, i32 %c) {423; CHECK-SD-LABEL: extract_v4i32_copysign_build_vector_const:424; CHECK-SD: // %bb.0: // %entry425; CHECK-SD-NEXT: fabs v0.4s, v0.4s426; CHECK-SD-NEXT: mov s0, v0.s[2]427; CHECK-SD-NEXT: ret428;429; CHECK-GI-LABEL: extract_v4i32_copysign_build_vector_const:430; CHECK-GI: // %bb.0: // %entry431; CHECK-GI-NEXT: mvni v1.4s, #128, lsl #24432; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b433; CHECK-GI-NEXT: mov s0, v0.s[2]434; CHECK-GI-NEXT: ret435entry:436 %vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)437 %d = extractelement <4 x float> %vector, i32 2438 ret float %d439}440 441 442define i32 @extract_v4i32_icmp(<4 x i32> %a, <4 x i32> %b, i32 %c) {443; CHECK-SD-LABEL: extract_v4i32_icmp:444; CHECK-SD: // %bb.0: // %entry445; CHECK-SD-NEXT: sub sp, sp, #16446; CHECK-SD-NEXT: .cfi_def_cfa_offset 16447; CHECK-SD-NEXT: adrp x8, .LCPI18_0448; CHECK-SD-NEXT: movi v2.4s, #1449; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0450; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]451; CHECK-SD-NEXT: mov x8, sp452; CHECK-SD-NEXT: bfi x8, x0, #2, #2453; CHECK-SD-NEXT: cmge v0.4s, v1.4s, v0.4s454; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b455; CHECK-SD-NEXT: str q0, [sp]456; CHECK-SD-NEXT: ldr w0, [x8]457; CHECK-SD-NEXT: add sp, sp, #16458; CHECK-SD-NEXT: ret459;460; CHECK-GI-LABEL: extract_v4i32_icmp:461; CHECK-GI: // %bb.0: // %entry462; CHECK-GI-NEXT: sub sp, sp, #16463; CHECK-GI-NEXT: .cfi_def_cfa_offset 16464; CHECK-GI-NEXT: adrp x8, .LCPI18_0465; CHECK-GI-NEXT: movi v2.4s, #1466; CHECK-GI-NEXT: mov x9, sp467; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]468; CHECK-GI-NEXT: mov w8, w0469; CHECK-GI-NEXT: and x8, x8, #0x3470; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s471; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b472; CHECK-GI-NEXT: str q0, [sp]473; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]474; CHECK-GI-NEXT: add sp, sp, #16475; CHECK-GI-NEXT: ret476entry:477 %vector = icmp sle <4 x i32> %a, <i32 42, i32 11, i32 17, i32 6>478 %zvector = zext <4 x i1> %vector to <4 x i32>479 %d = extractelement <4 x i32> %zvector, i32 %c480 ret i32 %d481}482 483define i32 @extract_v4i32_icmp_const(<4 x i32> %a, <4 x i32> %b, i32 %c) {484; CHECK-SD-LABEL: extract_v4i32_icmp_const:485; CHECK-SD: // %bb.0: // %entry486; CHECK-SD-NEXT: adrp x8, .LCPI19_0487; CHECK-SD-NEXT: movi v2.4s, #1488; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]489; CHECK-SD-NEXT: cmge v0.4s, v1.4s, v0.4s490; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b491; CHECK-SD-NEXT: mov w0, v0.s[2]492; CHECK-SD-NEXT: ret493;494; CHECK-GI-LABEL: extract_v4i32_icmp_const:495; CHECK-GI: // %bb.0: // %entry496; CHECK-GI-NEXT: adrp x8, .LCPI19_0497; CHECK-GI-NEXT: movi v2.4s, #1498; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]499; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s500; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b501; CHECK-GI-NEXT: mov s0, v0.s[2]502; CHECK-GI-NEXT: fmov w0, s0503; CHECK-GI-NEXT: ret504entry:505 %vector = icmp sle <4 x i32> %a, <i32 42, i32 11, i32 17, i32 6>506 %zvector = zext <4 x i1> %vector to <4 x i32>507 %d = extractelement <4 x i32> %zvector, i32 2508 ret i32 %d509}510 511define i32 @extract_v4f32_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {512; CHECK-SD-LABEL: extract_v4f32_fcmp:513; CHECK-SD: // %bb.0: // %entry514; CHECK-SD-NEXT: sub sp, sp, #16515; CHECK-SD-NEXT: .cfi_def_cfa_offset 16516; CHECK-SD-NEXT: movi v1.4s, #1517; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s518; CHECK-SD-NEXT: mov x8, sp519; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0520; CHECK-SD-NEXT: bfi x8, x0, #2, #2521; CHECK-SD-NEXT: bic v0.16b, v1.16b, v0.16b522; CHECK-SD-NEXT: str q0, [sp]523; CHECK-SD-NEXT: ldr w0, [x8]524; CHECK-SD-NEXT: add sp, sp, #16525; CHECK-SD-NEXT: ret526;527; CHECK-GI-LABEL: extract_v4f32_fcmp:528; CHECK-GI: // %bb.0: // %entry529; CHECK-GI-NEXT: sub sp, sp, #16530; CHECK-GI-NEXT: .cfi_def_cfa_offset 16531; CHECK-GI-NEXT: fmov v1.4s, #1.00000000532; CHECK-GI-NEXT: mov w8, w0533; CHECK-GI-NEXT: mov x9, sp534; CHECK-GI-NEXT: and x8, x8, #0x3535; CHECK-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s536; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s537; CHECK-GI-NEXT: movi v1.4s, #1538; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b539; CHECK-GI-NEXT: bic v0.16b, v1.16b, v0.16b540; CHECK-GI-NEXT: str q0, [sp]541; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]542; CHECK-GI-NEXT: add sp, sp, #16543; CHECK-GI-NEXT: ret544entry:545 %vector = fcmp uno <4 x float> %a, <float 1.0, float 1.0, float 1.0, float 1.0>546 %zvector = zext <4 x i1> %vector to <4 x i32>547 %d = extractelement <4 x i32> %zvector, i32 %c548 ret i32 %d549}550 551define i32 @extract_v4f32_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {552; CHECK-SD-LABEL: extract_v4f32_fcmp_const:553; CHECK-SD: // %bb.0: // %entry554; CHECK-SD-NEXT: movi v1.4s, #1555; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s556; CHECK-SD-NEXT: bic v0.16b, v1.16b, v0.16b557; CHECK-SD-NEXT: mov w0, v0.s[1]558; CHECK-SD-NEXT: ret559;560; CHECK-GI-LABEL: extract_v4f32_fcmp_const:561; CHECK-GI: // %bb.0: // %entry562; CHECK-GI-NEXT: fmov v1.4s, #1.00000000563; CHECK-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s564; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s565; CHECK-GI-NEXT: movi v1.4s, #1566; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b567; CHECK-GI-NEXT: bic v0.16b, v1.16b, v0.16b568; CHECK-GI-NEXT: mov s0, v0.s[1]569; CHECK-GI-NEXT: fmov w0, s0570; CHECK-GI-NEXT: ret571entry:572 %vector = fcmp uno <4 x float> %a, <float 1.0, float 1.0, float 1.0, float 1.0>573 %zvector = zext <4 x i1> %vector to <4 x i32>574 %d = extractelement <4 x i32> %zvector, i32 1575 ret i32 %d576}577 578define i32 @extract_v4i32_select(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %cond) {579; CHECK-SD-LABEL: extract_v4i32_select:580; CHECK-SD: // %bb.0: // %entry581; CHECK-SD-NEXT: sub sp, sp, #16582; CHECK-SD-NEXT: .cfi_def_cfa_offset 16583; CHECK-SD-NEXT: ushll v1.4s, v2.4h, #0584; CHECK-SD-NEXT: adrp x8, .LCPI22_0585; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0586; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI22_0]587; CHECK-SD-NEXT: mov x8, sp588; CHECK-SD-NEXT: bfi x8, x0, #2, #2589; CHECK-SD-NEXT: shl v1.4s, v1.4s, #31590; CHECK-SD-NEXT: cmlt v1.4s, v1.4s, #0591; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b592; CHECK-SD-NEXT: str q0, [sp]593; CHECK-SD-NEXT: ldr w0, [x8]594; CHECK-SD-NEXT: add sp, sp, #16595; CHECK-SD-NEXT: ret596;597; CHECK-GI-LABEL: extract_v4i32_select:598; CHECK-GI: // %bb.0: // %entry599; CHECK-GI-NEXT: sub sp, sp, #16600; CHECK-GI-NEXT: .cfi_def_cfa_offset 16601; CHECK-GI-NEXT: ushll v1.4s, v2.4h, #0602; CHECK-GI-NEXT: adrp x8, .LCPI22_0603; CHECK-GI-NEXT: mov x9, sp604; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI22_0]605; CHECK-GI-NEXT: mov w8, w0606; CHECK-GI-NEXT: and x8, x8, #0x3607; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31608; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0609; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b610; CHECK-GI-NEXT: str q0, [sp]611; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]612; CHECK-GI-NEXT: add sp, sp, #16613; CHECK-GI-NEXT: ret614entry:615 %vector = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> <i32 42, i32 11, i32 17, i32 6>616 %d = extractelement <4 x i32> %vector, i32 %c617 ret i32 %d618}619 620define i32 @extract_v4i32_select_const(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %cond) {621; CHECK-SD-LABEL: extract_v4i32_select_const:622; CHECK-SD: // %bb.0: // %entry623; CHECK-SD-NEXT: ushll v1.4s, v2.4h, #0624; CHECK-SD-NEXT: movi v2.4s, #17625; CHECK-SD-NEXT: shl v1.4s, v1.4s, #31626; CHECK-SD-NEXT: cmlt v1.4s, v1.4s, #0627; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b628; CHECK-SD-NEXT: mov w0, v0.s[2]629; CHECK-SD-NEXT: ret630;631; CHECK-GI-LABEL: extract_v4i32_select_const:632; CHECK-GI: // %bb.0: // %entry633; CHECK-GI-NEXT: ushll v1.4s, v2.4h, #0634; CHECK-GI-NEXT: adrp x8, .LCPI23_0635; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI23_0]636; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31637; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0638; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b639; CHECK-GI-NEXT: mov s0, v0.s[2]640; CHECK-GI-NEXT: fmov w0, s0641; CHECK-GI-NEXT: ret642entry:643 %vector = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> <i32 42, i32 11, i32 17, i32 6>644 %d = extractelement <4 x i32> %vector, i32 2645 ret i32 %d646}647 648define i32 @extract_v4i32_abs(<4 x float> %a, i32 %c) {649; CHECK-SD-LABEL: extract_v4i32_abs:650; CHECK-SD: // %bb.0: // %entry651; CHECK-SD-NEXT: sub sp, sp, #16652; CHECK-SD-NEXT: .cfi_def_cfa_offset 16653; CHECK-SD-NEXT: frintp v0.4s, v0.4s654; CHECK-SD-NEXT: mov x8, sp655; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0656; CHECK-SD-NEXT: bfi x8, x0, #2, #2657; CHECK-SD-NEXT: frintm v0.4s, v0.4s658; CHECK-SD-NEXT: fabs v0.4s, v0.4s659; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s660; CHECK-SD-NEXT: abs v0.4s, v0.4s661; CHECK-SD-NEXT: str q0, [sp]662; CHECK-SD-NEXT: ldr w0, [x8]663; CHECK-SD-NEXT: add sp, sp, #16664; CHECK-SD-NEXT: ret665;666; CHECK-GI-LABEL: extract_v4i32_abs:667; CHECK-GI: // %bb.0: // %entry668; CHECK-GI-NEXT: sub sp, sp, #16669; CHECK-GI-NEXT: .cfi_def_cfa_offset 16670; CHECK-GI-NEXT: frintp v0.4s, v0.4s671; CHECK-GI-NEXT: mov w9, w0672; CHECK-GI-NEXT: mov x8, sp673; CHECK-GI-NEXT: and x9, x9, #0x3674; CHECK-GI-NEXT: frintm v0.4s, v0.4s675; CHECK-GI-NEXT: fabs v0.4s, v0.4s676; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s677; CHECK-GI-NEXT: abs v0.4s, v0.4s678; CHECK-GI-NEXT: str q0, [sp]679; CHECK-GI-NEXT: ldr w0, [x8, x9, lsl #2]680; CHECK-GI-NEXT: add sp, sp, #16681; CHECK-GI-NEXT: ret682entry:683 %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)684 %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)685 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)686 %abs = fptosi <4 x float> %fabs to <4 x i32>687 %vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)688 %d = extractelement <4 x i32> %vector, i32 %c689 ret i32 %d690}691 692define i32 @extract_v4i32_abs_const(<4 x float> %a, i32 %c) {693; CHECK-SD-LABEL: extract_v4i32_abs_const:694; CHECK-SD: // %bb.0: // %entry695; CHECK-SD-NEXT: mov w0, #4 // =0x4696; CHECK-SD-NEXT: ret697;698; CHECK-GI-LABEL: extract_v4i32_abs_const:699; CHECK-GI: // %bb.0: // %entry700; CHECK-GI-NEXT: adrp x8, .LCPI25_0701; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI25_0]702; CHECK-GI-NEXT: frintp v0.4s, v0.4s703; CHECK-GI-NEXT: frintm v0.4s, v0.4s704; CHECK-GI-NEXT: fabs v0.4s, v0.4s705; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s706; CHECK-GI-NEXT: abs v0.4s, v0.4s707; CHECK-GI-NEXT: mov s0, v0.s[1]708; CHECK-GI-NEXT: fmov w0, s0709; CHECK-GI-NEXT: ret710entry:711 %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)712 %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)713 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)714 %abs = fptosi <4 x float> %fabs to <4 x i32>715 %vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)716 %d = extractelement <4 x i32> %vector, i32 1717 ret i32 %d718}719 720define i32 @extract_v4i32_abs_half_const(<4 x float> %a, i32 %c) {721; CHECK-SD-LABEL: extract_v4i32_abs_half_const:722; CHECK-SD: // %bb.0: // %entry723; CHECK-SD-NEXT: sub sp, sp, #16724; CHECK-SD-NEXT: .cfi_def_cfa_offset 16725; CHECK-SD-NEXT: adrp x8, .LCPI26_0726; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0727; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI26_0]728; CHECK-SD-NEXT: mov x8, sp729; CHECK-SD-NEXT: bfi x8, x0, #2, #2730; CHECK-SD-NEXT: str q0, [sp]731; CHECK-SD-NEXT: ldr w0, [x8]732; CHECK-SD-NEXT: add sp, sp, #16733; CHECK-SD-NEXT: ret734;735; CHECK-GI-LABEL: extract_v4i32_abs_half_const:736; CHECK-GI: // %bb.0: // %entry737; CHECK-GI-NEXT: sub sp, sp, #16738; CHECK-GI-NEXT: .cfi_def_cfa_offset 16739; CHECK-GI-NEXT: adrp x8, .LCPI26_0740; CHECK-GI-NEXT: mov x9, sp741; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI26_0]742; CHECK-GI-NEXT: mov w8, w0743; CHECK-GI-NEXT: and x8, x8, #0x3744; CHECK-GI-NEXT: frintp v0.4s, v0.4s745; CHECK-GI-NEXT: frintm v0.4s, v0.4s746; CHECK-GI-NEXT: fabs v0.4s, v0.4s747; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s748; CHECK-GI-NEXT: abs v0.4s, v0.4s749; CHECK-GI-NEXT: str q0, [sp]750; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]751; CHECK-GI-NEXT: add sp, sp, #16752; CHECK-GI-NEXT: ret753entry:754 %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)755 %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)756 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)757 %abs = fptosi <4 x float> %fabs to <4 x i32>758 %vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)759 %d = extractelement <4 x i32> %vector, i32 %c760 ret i32 %d761}762 763define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {764; CHECK-LABEL: extract_v4i32_vector_insert:765; CHECK: // %bb.0: // %entry766; CHECK-NEXT: sub sp, sp, #16767; CHECK-NEXT: .cfi_def_cfa_offset 16768; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8769; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1770; CHECK-NEXT: mov x8, sp771; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0772; CHECK-NEXT: bfi x8, x0, #2, #2773; CHECK-NEXT: mov v1.d[1], v0.d[0]774; CHECK-NEXT: str q1, [sp]775; CHECK-NEXT: ldr w0, [x8]776; CHECK-NEXT: add sp, sp, #16777; CHECK-NEXT: ret778entry:779 %vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)780 %d = extractelement <4 x i32> %vector, i32 %c781 ret i32 %d782}783 784define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {785; CHECK-LABEL: extract_v4i32_vector_insert_const:786; CHECK: // %bb.0: // %entry787; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1788; CHECK-NEXT: mov w0, v1.s[1]789; CHECK-NEXT: ret790entry:791 %vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)792 %d = extractelement <4 x i32> %vector, i32 1793 ret i32 %d794}795 796define i32 @extract_v4i32_vector_extract(<4 x i32> %a, <2 x i32> %b, i32 %c) {797; CHECK-LABEL: extract_v4i32_vector_extract:798; CHECK: // %bb.0: // %entry799; CHECK-NEXT: sub sp, sp, #16800; CHECK-NEXT: .cfi_def_cfa_offset 16801; CHECK-NEXT: mov x8, sp802; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0803; CHECK-NEXT: str q0, [sp]804; CHECK-NEXT: bfi x8, x0, #2, #2805; CHECK-NEXT: ldr w0, [x8]806; CHECK-NEXT: add sp, sp, #16807; CHECK-NEXT: ret808entry:809 %vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)810 %d = extractelement <4 x i32> %vector, i32 %c811 ret i32 %d812}813 814define i32 @extract_v4i32_vector_extract_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {815; CHECK-LABEL: extract_v4i32_vector_extract_const:816; CHECK: // %bb.0: // %entry817; CHECK-NEXT: fmov w0, s0818; CHECK-NEXT: ret819entry:820 %vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)821 %d = extractelement <4 x i32> %vector, i32 0822 ret i32 %d823}824 825define i32 @extract_v4i32_load(<4 x i32> %a, <2 x i32> %b, i32 %c, ptr %arg) {826; CHECK-SD-LABEL: extract_v4i32_load:827; CHECK-SD: // %bb.0: // %entry828; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0829; CHECK-SD-NEXT: and x8, x0, #0x3830; CHECK-SD-NEXT: ldr w0, [x1, x8, lsl #2]831; CHECK-SD-NEXT: ret832;833; CHECK-GI-LABEL: extract_v4i32_load:834; CHECK-GI: // %bb.0: // %entry835; CHECK-GI-NEXT: mov w8, w0836; CHECK-GI-NEXT: and x8, x8, #0x3837; CHECK-GI-NEXT: ldr w0, [x1, x8, lsl #2]838; CHECK-GI-NEXT: ret839entry:840 %vector = load <4 x i32>, ptr %arg841 %d = extractelement <4 x i32> %vector, i32 %c842 ret i32 %d843}844 845define i32 @extract_v4i32_load_const(<4 x i32> %a, <2 x i32> %b, i32 %c, ptr %arg) {846; CHECK-LABEL: extract_v4i32_load_const:847; CHECK: // %bb.0: // %entry848; CHECK-NEXT: ldr w0, [x1]849; CHECK-NEXT: ret850entry:851 %vector = load <4 x i32>, ptr %arg852 %d = extractelement <4 x i32> %vector, i32 0853 ret i32 %d854}855 856define double @extract_v4i32_bitcast(<4 x i32> %a, i32 %c) {857; CHECK-SD-LABEL: extract_v4i32_bitcast:858; CHECK-SD: // %bb.0: // %entry859; CHECK-SD-NEXT: sub sp, sp, #16860; CHECK-SD-NEXT: .cfi_def_cfa_offset 16861; CHECK-SD-NEXT: mov x8, sp862; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0863; CHECK-SD-NEXT: str q0, [sp]864; CHECK-SD-NEXT: bfi x8, x0, #3, #1865; CHECK-SD-NEXT: ldr d0, [x8]866; CHECK-SD-NEXT: add sp, sp, #16867; CHECK-SD-NEXT: ret868;869; CHECK-GI-LABEL: extract_v4i32_bitcast:870; CHECK-GI: // %bb.0: // %entry871; CHECK-GI-NEXT: sub sp, sp, #16872; CHECK-GI-NEXT: .cfi_def_cfa_offset 16873; CHECK-GI-NEXT: mov w9, w0874; CHECK-GI-NEXT: mov x8, sp875; CHECK-GI-NEXT: str q0, [sp]876; CHECK-GI-NEXT: and x9, x9, #0x1877; CHECK-GI-NEXT: ldr d0, [x8, x9, lsl #3]878; CHECK-GI-NEXT: add sp, sp, #16879; CHECK-GI-NEXT: ret880entry:881 %vector = bitcast <4 x i32> %a to <2 x double>882 %d = extractelement <2 x double> %vector, i32 %c883 ret double %d884}885 886define double @extract_v4i32_bitcast_const(<4 x i32> %a, i32 %c) {887; CHECK-LABEL: extract_v4i32_bitcast_const:888; CHECK: // %bb.0: // %entry889; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0890; CHECK-NEXT: ret891entry:892 %vector = bitcast <4 x i32> %a to <2 x double>893 %d = extractelement <2 x double> %vector, i32 0894 ret double %d895}896 897define i32 @extract_v4i32_shuffle(<4 x i32> %a, <4 x i32> %b, i32 %c) {898; CHECK-SD-LABEL: extract_v4i32_shuffle:899; CHECK-SD: // %bb.0: // %entry900; CHECK-SD-NEXT: sub sp, sp, #16901; CHECK-SD-NEXT: .cfi_def_cfa_offset 16902; CHECK-SD-NEXT: uzp1 v1.4s, v0.4s, v1.4s903; CHECK-SD-NEXT: mov x8, sp904; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0905; CHECK-SD-NEXT: bfi x8, x0, #2, #2906; CHECK-SD-NEXT: mov v1.s[3], v0.s[3]907; CHECK-SD-NEXT: str q1, [sp]908; CHECK-SD-NEXT: ldr w0, [x8]909; CHECK-SD-NEXT: add sp, sp, #16910; CHECK-SD-NEXT: ret911;912; CHECK-GI-LABEL: extract_v4i32_shuffle:913; CHECK-GI: // %bb.0: // %entry914; CHECK-GI-NEXT: sub sp, sp, #16915; CHECK-GI-NEXT: .cfi_def_cfa_offset 16916; CHECK-GI-NEXT: adrp x8, .LCPI35_0917; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1918; CHECK-GI-NEXT: mov x9, sp919; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI35_0]920; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1921; CHECK-GI-NEXT: mov w8, w0922; CHECK-GI-NEXT: and x8, x8, #0x3923; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b924; CHECK-GI-NEXT: str q0, [sp]925; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]926; CHECK-GI-NEXT: add sp, sp, #16927; CHECK-GI-NEXT: ret928entry:929 %vector = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 3>930 %d = extractelement <4 x i32> %vector, i32 %c931 ret i32 %d932}933 934define i32 @extract_v4i32_shuffle_const(<4 x i32> %a, <4 x i32> %b, i32 %c) {935; CHECK-LABEL: extract_v4i32_shuffle_const:936; CHECK: // %bb.0: // %entry937; CHECK-NEXT: fmov w0, s1938; CHECK-NEXT: ret939entry:940 %vector = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 3>941 %d = extractelement <4 x i32> %vector, i32 2942 ret i32 %d943}944 945define i32 @extract_v4i32_splat(<4 x i32> %a, <2 x i32> %b, i32 %c) {946; CHECK-SD-LABEL: extract_v4i32_splat:947; CHECK-SD: // %bb.0: // %entry948; CHECK-SD-NEXT: sub sp, sp, #16949; CHECK-SD-NEXT: .cfi_def_cfa_offset 16950; CHECK-SD-NEXT: movi v0.4s, #11951; CHECK-SD-NEXT: mov x8, sp952; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0953; CHECK-SD-NEXT: bfi x8, x0, #2, #2954; CHECK-SD-NEXT: str q0, [sp]955; CHECK-SD-NEXT: ldr w0, [x8]956; CHECK-SD-NEXT: add sp, sp, #16957; CHECK-SD-NEXT: ret958;959; CHECK-GI-LABEL: extract_v4i32_splat:960; CHECK-GI: // %bb.0: // %entry961; CHECK-GI-NEXT: sub sp, sp, #16962; CHECK-GI-NEXT: .cfi_def_cfa_offset 16963; CHECK-GI-NEXT: movi v0.4s, #11964; CHECK-GI-NEXT: mov w8, w0965; CHECK-GI-NEXT: mov x9, sp966; CHECK-GI-NEXT: and x8, x8, #0x3967; CHECK-GI-NEXT: str q0, [sp]968; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]969; CHECK-GI-NEXT: add sp, sp, #16970; CHECK-GI-NEXT: ret971entry:972 %d = extractelement <4 x i32> splat (i32 11), i32 %c973 ret i32 %d974}975 976define i32 @extract_v4i32_splat_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {977; CHECK-LABEL: extract_v4i32_splat_const:978; CHECK: // %bb.0: // %entry979; CHECK-NEXT: mov w0, #11 // =0xb980; CHECK-NEXT: ret981entry:982 %d = extractelement <4 x i32> splat (i32 11), i32 0983 ret i32 %d984}985 986define i32 @extract_v4i32_vp_add(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %mask, i32 %evl) {987; CHECK-SD-LABEL: extract_v4i32_vp_add:988; CHECK-SD: // %bb.0: // %entry989; CHECK-SD-NEXT: sub sp, sp, #16990; CHECK-SD-NEXT: .cfi_def_cfa_offset 16991; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s992; CHECK-SD-NEXT: mov x8, sp993; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0994; CHECK-SD-NEXT: bfi x8, x0, #2, #2995; CHECK-SD-NEXT: str q0, [sp]996; CHECK-SD-NEXT: ldr w0, [x8]997; CHECK-SD-NEXT: add sp, sp, #16998; CHECK-SD-NEXT: ret999;1000; CHECK-GI-LABEL: extract_v4i32_vp_add:1001; CHECK-GI: // %bb.0: // %entry1002; CHECK-GI-NEXT: sub sp, sp, #161003; CHECK-GI-NEXT: .cfi_def_cfa_offset 161004; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s1005; CHECK-GI-NEXT: mov w8, w01006; CHECK-GI-NEXT: mov x9, sp1007; CHECK-GI-NEXT: and x8, x8, #0x31008; CHECK-GI-NEXT: str q0, [sp]1009; CHECK-GI-NEXT: ldr w0, [x9, x8, lsl #2]1010; CHECK-GI-NEXT: add sp, sp, #161011; CHECK-GI-NEXT: ret1012entry:1013 %vector = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)1014 %d = extractelement <4 x i32> %vector, i32 %c1015 ret i32 %d1016}1017 1018define i32 @extract_v4i32_vp_add_const(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %mask, i32 %evl) {1019; CHECK-SD-LABEL: extract_v4i32_vp_add_const:1020; CHECK-SD: // %bb.0: // %entry1021; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s1022; CHECK-SD-NEXT: mov w0, v0.s[3]1023; CHECK-SD-NEXT: ret1024;1025; CHECK-GI-LABEL: extract_v4i32_vp_add_const:1026; CHECK-GI: // %bb.0: // %entry1027; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s1028; CHECK-GI-NEXT: mov s0, v0.s[3]1029; CHECK-GI-NEXT: fmov w0, s01030; CHECK-GI-NEXT: ret1031entry:1032 %vector = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)1033 %d = extractelement <4 x i32> %vector, i32 31034 ret i32 %d1035}1036 1037define i32 @extract_v4i32_phi(i64 %val, i32 %limit, ptr %ptr) {1038; CHECK-SD-LABEL: extract_v4i32_phi:1039; CHECK-SD: // %bb.0: // %entry1040; CHECK-SD-NEXT: dup v1.2s, w01041; CHECK-SD-NEXT: adrp x8, .LCPI41_01042; CHECK-SD-NEXT: movi v0.2s, #161043; CHECK-SD-NEXT: ldr d2, [x8, :lo12:.LCPI41_0]1044; CHECK-SD-NEXT: add v1.2s, v1.2s, v2.2s1045; CHECK-SD-NEXT: .LBB41_1: // %loop1046; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=11047; CHECK-SD-NEXT: fmov w8, s11048; CHECK-SD-NEXT: add v1.2s, v1.2s, v0.2s1049; CHECK-SD-NEXT: cmp w8, w11050; CHECK-SD-NEXT: add w0, w8, #101051; CHECK-SD-NEXT: str w0, [x2, w8, sxtw #2]1052; CHECK-SD-NEXT: b.lo .LBB41_11053; CHECK-SD-NEXT: // %bb.2: // %ret1054; CHECK-SD-NEXT: ret1055;1056; CHECK-GI-LABEL: extract_v4i32_phi:1057; CHECK-GI: // %bb.0: // %entry1058; CHECK-GI-NEXT: adrp x8, .LCPI41_01059; CHECK-GI-NEXT: dup v0.2d, x01060; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI41_0]1061; CHECK-GI-NEXT: add v1.2d, v0.2d, v1.2d1062; CHECK-GI-NEXT: movi v0.2s, #161063; CHECK-GI-NEXT: xtn v1.2s, v1.2d1064; CHECK-GI-NEXT: .LBB41_1: // %loop1065; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=11066; CHECK-GI-NEXT: fmov w8, s11067; CHECK-GI-NEXT: fmov w9, s11068; CHECK-GI-NEXT: add v1.2s, v1.2s, v0.2s1069; CHECK-GI-NEXT: cmp w8, w11070; CHECK-GI-NEXT: add w0, w9, #101071; CHECK-GI-NEXT: str w0, [x2, w8, sxtw #2]1072; CHECK-GI-NEXT: b.lo .LBB41_11073; CHECK-GI-NEXT: // %bb.2: // %ret1074; CHECK-GI-NEXT: ret1075entry:1076 %tempvector = insertelement <2 x i64> undef, i64 %val, i32 01077 %vector = shufflevector <2 x i64> %tempvector, <2 x i64> undef, <2 x i32> zeroinitializer1078 %0 = add <2 x i64> %vector, <i64 1, i64 2>1079 %1 = trunc <2 x i64> %0 to <2 x i32>1080 br label %loop1081 1082loop:1083 %2 = phi <2 x i32> [ %1, %entry ], [ %inc, %loop ]1084 %elt = extractelement <2 x i32> %2, i32 01085 %end = icmp ult i32 %elt, %limit1086 %3 = add i32 10, %elt1087 %4 = sext i32 %elt to i641088 %5 = getelementptr i32, ptr %ptr, i64 %41089 store i32 %3, ptr %51090 %inc = add <2 x i32> %2, <i32 16, i32 16>1091 br i1 %end, label %loop, label %ret1092 1093ret:1094 ret i32 %31095}1096 1097define <3 x ptr> @v3move(<3 x ptr> %a, <3 x ptr> %b, <3 x ptr> %x) {1098; CHECK-SD-LABEL: v3move:1099; CHECK-SD: // %bb.0: // %entry1100; CHECK-SD-NEXT: fmov d1, d71101; CHECK-SD-NEXT: fmov d0, d61102; CHECK-SD-NEXT: ldr d2, [sp]1103; CHECK-SD-NEXT: ret1104;1105; CHECK-GI-LABEL: v3move:1106; CHECK-GI: // %bb.0: // %entry1107; CHECK-GI-NEXT: ldr x8, [sp]1108; CHECK-GI-NEXT: fmov d0, d61109; CHECK-GI-NEXT: fmov d1, d71110; CHECK-GI-NEXT: fmov d2, x81111; CHECK-GI-NEXT: ret1112entry:1113 ret <3 x ptr> %x1114}1115 1116define ptr @v3ext(<3 x ptr> %a, <3 x ptr> %b, <3 x ptr> %x) {1117; CHECK-LABEL: v3ext:1118; CHECK: // %bb.0: // %entry1119; CHECK-NEXT: ldr x0, [sp]1120; CHECK-NEXT: ret1121entry:1122 %c = extractelement <3 x ptr> %x, i32 21123 ret ptr %c1124}1125