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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD3; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD4; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI5; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI6 7define half @test_fadd(half %a, half %b) #0 {8; CHECK-CVT-SD-LABEL: test_fadd:9; CHECK-CVT-SD: // %bb.0:10; CHECK-CVT-SD-NEXT: fcvt s1, h111; CHECK-CVT-SD-NEXT: fcvt s0, h012; CHECK-CVT-SD-NEXT: fadd s0, s0, s113; CHECK-CVT-SD-NEXT: fcvt h0, s014; CHECK-CVT-SD-NEXT: ret15;16; CHECK-FP16-LABEL: test_fadd:17; CHECK-FP16: // %bb.0:18; CHECK-FP16-NEXT: fadd h0, h0, h119; CHECK-FP16-NEXT: ret20;21; CHECK-CVT-GI-LABEL: test_fadd:22; CHECK-CVT-GI: // %bb.0:23; CHECK-CVT-GI-NEXT: fcvt s0, h024; CHECK-CVT-GI-NEXT: fcvt s1, h125; CHECK-CVT-GI-NEXT: fadd s0, s0, s126; CHECK-CVT-GI-NEXT: fcvt h0, s027; CHECK-CVT-GI-NEXT: ret28 %r = fadd half %a, %b29 ret half %r30}31 32define half @test_fsub(half %a, half %b) #0 {33; CHECK-CVT-SD-LABEL: test_fsub:34; CHECK-CVT-SD: // %bb.0:35; CHECK-CVT-SD-NEXT: fcvt s1, h136; CHECK-CVT-SD-NEXT: fcvt s0, h037; CHECK-CVT-SD-NEXT: fsub s0, s0, s138; CHECK-CVT-SD-NEXT: fcvt h0, s039; CHECK-CVT-SD-NEXT: ret40;41; CHECK-FP16-LABEL: test_fsub:42; CHECK-FP16: // %bb.0:43; CHECK-FP16-NEXT: fsub h0, h0, h144; CHECK-FP16-NEXT: ret45;46; CHECK-CVT-GI-LABEL: test_fsub:47; CHECK-CVT-GI: // %bb.0:48; CHECK-CVT-GI-NEXT: fcvt s0, h049; CHECK-CVT-GI-NEXT: fcvt s1, h150; CHECK-CVT-GI-NEXT: fsub s0, s0, s151; CHECK-CVT-GI-NEXT: fcvt h0, s052; CHECK-CVT-GI-NEXT: ret53 %r = fsub half %a, %b54 ret half %r55}56 57define half @test_fmul(half %a, half %b) #0 {58; CHECK-CVT-SD-LABEL: test_fmul:59; CHECK-CVT-SD: // %bb.0:60; CHECK-CVT-SD-NEXT: fcvt s1, h161; CHECK-CVT-SD-NEXT: fcvt s0, h062; CHECK-CVT-SD-NEXT: fmul s0, s0, s163; CHECK-CVT-SD-NEXT: fcvt h0, s064; CHECK-CVT-SD-NEXT: ret65;66; CHECK-FP16-LABEL: test_fmul:67; CHECK-FP16: // %bb.0:68; CHECK-FP16-NEXT: fmul h0, h0, h169; CHECK-FP16-NEXT: ret70;71; CHECK-CVT-GI-LABEL: test_fmul:72; CHECK-CVT-GI: // %bb.0:73; CHECK-CVT-GI-NEXT: fcvt s0, h074; CHECK-CVT-GI-NEXT: fcvt s1, h175; CHECK-CVT-GI-NEXT: fmul s0, s0, s176; CHECK-CVT-GI-NEXT: fcvt h0, s077; CHECK-CVT-GI-NEXT: ret78 %r = fmul half %a, %b79 ret half %r80}81 82define half @test_fmadd(half %a, half %b, half %c) #0 {83; CHECK-CVT-SD-LABEL: test_fmadd:84; CHECK-CVT-SD: // %bb.0:85; CHECK-CVT-SD-NEXT: fcvt s1, h186; CHECK-CVT-SD-NEXT: fcvt s0, h087; CHECK-CVT-SD-NEXT: fcvt s2, h288; CHECK-CVT-SD-NEXT: fmadd s0, s0, s1, s289; CHECK-CVT-SD-NEXT: fcvt h0, s090; CHECK-CVT-SD-NEXT: ret91;92; CHECK-FP16-LABEL: test_fmadd:93; CHECK-FP16: // %bb.0:94; CHECK-FP16-NEXT: fmadd h0, h0, h1, h295; CHECK-FP16-NEXT: ret96;97; CHECK-CVT-GI-LABEL: test_fmadd:98; CHECK-CVT-GI: // %bb.0:99; CHECK-CVT-GI-NEXT: fcvt s0, h0100; CHECK-CVT-GI-NEXT: fcvt s1, h1101; CHECK-CVT-GI-NEXT: fmul s0, s0, s1102; CHECK-CVT-GI-NEXT: fcvt s1, h2103; CHECK-CVT-GI-NEXT: fcvt h0, s0104; CHECK-CVT-GI-NEXT: fcvt s0, h0105; CHECK-CVT-GI-NEXT: fadd s0, s0, s1106; CHECK-CVT-GI-NEXT: fcvt h0, s0107; CHECK-CVT-GI-NEXT: ret108 %mul = fmul fast half %a, %b109 %r = fadd fast half %mul, %c110 ret half %r111}112 113define half @test_fdiv(half %a, half %b) #0 {114; CHECK-CVT-SD-LABEL: test_fdiv:115; CHECK-CVT-SD: // %bb.0:116; CHECK-CVT-SD-NEXT: fcvt s1, h1117; CHECK-CVT-SD-NEXT: fcvt s0, h0118; CHECK-CVT-SD-NEXT: fdiv s0, s0, s1119; CHECK-CVT-SD-NEXT: fcvt h0, s0120; CHECK-CVT-SD-NEXT: ret121;122; CHECK-FP16-LABEL: test_fdiv:123; CHECK-FP16: // %bb.0:124; CHECK-FP16-NEXT: fdiv h0, h0, h1125; CHECK-FP16-NEXT: ret126;127; CHECK-CVT-GI-LABEL: test_fdiv:128; CHECK-CVT-GI: // %bb.0:129; CHECK-CVT-GI-NEXT: fcvt s0, h0130; CHECK-CVT-GI-NEXT: fcvt s1, h1131; CHECK-CVT-GI-NEXT: fdiv s0, s0, s1132; CHECK-CVT-GI-NEXT: fcvt h0, s0133; CHECK-CVT-GI-NEXT: ret134 %r = fdiv half %a, %b135 ret half %r136}137 138define half @test_frem(half %a, half %b) #0 {139; CHECK-LABEL: test_frem:140; CHECK: // %bb.0:141; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill142; CHECK-NEXT: fcvt s0, h0143; CHECK-NEXT: fcvt s1, h1144; CHECK-NEXT: bl fmodf145; CHECK-NEXT: fcvt h0, s0146; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload147; CHECK-NEXT: ret148 %r = frem half %a, %b149 ret half %r150}151 152define void @test_store(half %a, ptr %b) #0 {153; CHECK-LABEL: test_store:154; CHECK: // %bb.0:155; CHECK-NEXT: str h0, [x0]156; CHECK-NEXT: ret157 store half %a, ptr %b158 ret void159}160 161define half @test_load(ptr %a) #0 {162; CHECK-LABEL: test_load:163; CHECK: // %bb.0:164; CHECK-NEXT: ldr h0, [x0]165; CHECK-NEXT: ret166 %r = load half, ptr %a167 ret half %r168}169 170declare half @test_callee(half %a, half %b) #0171 172define half @test_call(half %a, half %b) #0 {173; CHECK-LABEL: test_call:174; CHECK: // %bb.0:175; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill176; CHECK-NEXT: bl test_callee177; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload178; CHECK-NEXT: ret179 %r = call half @test_callee(half %a, half %b)180 ret half %r181}182 183define half @test_call_flipped(half %a, half %b) #0 {184; CHECK-LABEL: test_call_flipped:185; CHECK: // %bb.0:186; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill187; CHECK-NEXT: fmov s2, s0188; CHECK-NEXT: fmov s0, s1189; CHECK-NEXT: fmov s1, s2190; CHECK-NEXT: bl test_callee191; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload192; CHECK-NEXT: ret193 %r = call half @test_callee(half %b, half %a)194 ret half %r195}196 197define half @test_tailcall_flipped(half %a, half %b) #0 {198; CHECK-LABEL: test_tailcall_flipped:199; CHECK: // %bb.0:200; CHECK-NEXT: fmov s2, s0201; CHECK-NEXT: fmov s0, s1202; CHECK-NEXT: fmov s1, s2203; CHECK-NEXT: b test_callee204 %r = tail call half @test_callee(half %b, half %a)205 ret half %r206}207 208define half @test_select(half %a, half %b, i1 zeroext %c) #0 {209; CHECK-CVT-SD-LABEL: test_select:210; CHECK-CVT-SD: // %bb.0:211; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $s0212; CHECK-CVT-SD-NEXT: cmp w0, #0213; CHECK-CVT-SD-NEXT: // kill: def $h1 killed $h1 def $s1214; CHECK-CVT-SD-NEXT: fcsel s0, s0, s1, ne215; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $s0216; CHECK-CVT-SD-NEXT: ret217;218; CHECK-FP16-SD-LABEL: test_select:219; CHECK-FP16-SD: // %bb.0:220; CHECK-FP16-SD-NEXT: cmp w0, #0221; CHECK-FP16-SD-NEXT: fcsel h0, h0, h1, ne222; CHECK-FP16-SD-NEXT: ret223;224; CHECK-CVT-GI-LABEL: test_select:225; CHECK-CVT-GI: // %bb.0:226; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0227; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $s1228; CHECK-CVT-GI-NEXT: fmov w8, s0229; CHECK-CVT-GI-NEXT: fmov w9, s1230; CHECK-CVT-GI-NEXT: tst w0, #0x1231; CHECK-CVT-GI-NEXT: csel w8, w8, w9, ne232; CHECK-CVT-GI-NEXT: fmov s0, w8233; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $s0234; CHECK-CVT-GI-NEXT: ret235;236; CHECK-FP16-GI-LABEL: test_select:237; CHECK-FP16-GI: // %bb.0:238; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $s0239; CHECK-FP16-GI-NEXT: // kill: def $h1 killed $h1 def $s1240; CHECK-FP16-GI-NEXT: fmov w8, s0241; CHECK-FP16-GI-NEXT: fmov w9, s1242; CHECK-FP16-GI-NEXT: tst w0, #0x1243; CHECK-FP16-GI-NEXT: csel w8, w8, w9, ne244; CHECK-FP16-GI-NEXT: fmov s0, w8245; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $s0246; CHECK-FP16-GI-NEXT: ret247 %r = select i1 %c, half %a, half %b248 ret half %r249}250 251define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {252; CHECK-CVT-SD-LABEL: test_select_cc:253; CHECK-CVT-SD: // %bb.0:254; CHECK-CVT-SD-NEXT: fcvt s3, h3255; CHECK-CVT-SD-NEXT: fcvt s2, h2256; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $s0257; CHECK-CVT-SD-NEXT: // kill: def $h1 killed $h1 def $s1258; CHECK-CVT-SD-NEXT: fcmp s2, s3259; CHECK-CVT-SD-NEXT: fcsel s0, s0, s1, ne260; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $s0261; CHECK-CVT-SD-NEXT: ret262;263; CHECK-FP16-SD-LABEL: test_select_cc:264; CHECK-FP16-SD: // %bb.0:265; CHECK-FP16-SD-NEXT: fcmp h2, h3266; CHECK-FP16-SD-NEXT: fcsel h0, h0, h1, ne267; CHECK-FP16-SD-NEXT: ret268;269; CHECK-CVT-GI-LABEL: test_select_cc:270; CHECK-CVT-GI: // %bb.0:271; CHECK-CVT-GI-NEXT: fcvt s2, h2272; CHECK-CVT-GI-NEXT: fcvt s3, h3273; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0274; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $s1275; CHECK-CVT-GI-NEXT: fmov w8, s0276; CHECK-CVT-GI-NEXT: fmov w9, s1277; CHECK-CVT-GI-NEXT: fcmp s2, s3278; CHECK-CVT-GI-NEXT: csel w8, w8, w9, ne279; CHECK-CVT-GI-NEXT: fmov s0, w8280; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $s0281; CHECK-CVT-GI-NEXT: ret282;283; CHECK-FP16-GI-LABEL: test_select_cc:284; CHECK-FP16-GI: // %bb.0:285; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $s0286; CHECK-FP16-GI-NEXT: // kill: def $h1 killed $h1 def $s1287; CHECK-FP16-GI-NEXT: fcmp h2, h3288; CHECK-FP16-GI-NEXT: fmov w8, s0289; CHECK-FP16-GI-NEXT: fmov w9, s1290; CHECK-FP16-GI-NEXT: csel w8, w8, w9, ne291; CHECK-FP16-GI-NEXT: fmov s0, w8292; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $s0293; CHECK-FP16-GI-NEXT: ret294 %cc = fcmp une half %c, %d295 %r = select i1 %cc, half %a, half %b296 ret half %r297}298 299define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {300; CHECK-CVT-SD-LABEL: test_select_cc_f32_f16:301; CHECK-CVT-SD: // %bb.0:302; CHECK-CVT-SD-NEXT: fcvt s3, h3303; CHECK-CVT-SD-NEXT: fcvt s2, h2304; CHECK-CVT-SD-NEXT: fcmp s2, s3305; CHECK-CVT-SD-NEXT: fcsel s0, s0, s1, ne306; CHECK-CVT-SD-NEXT: ret307;308; CHECK-FP16-LABEL: test_select_cc_f32_f16:309; CHECK-FP16: // %bb.0:310; CHECK-FP16-NEXT: fcmp h2, h3311; CHECK-FP16-NEXT: fcsel s0, s0, s1, ne312; CHECK-FP16-NEXT: ret313;314; CHECK-CVT-GI-LABEL: test_select_cc_f32_f16:315; CHECK-CVT-GI: // %bb.0:316; CHECK-CVT-GI-NEXT: fcvt s2, h2317; CHECK-CVT-GI-NEXT: fcvt s3, h3318; CHECK-CVT-GI-NEXT: fcmp s2, s3319; CHECK-CVT-GI-NEXT: fcsel s0, s0, s1, ne320; CHECK-CVT-GI-NEXT: ret321 %cc = fcmp une half %c, %d322 %r = select i1 %cc, float %a, float %b323 ret float %r324}325 326define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 {327; CHECK-CVT-SD-LABEL: test_select_cc_f16_f32:328; CHECK-CVT-SD: // %bb.0:329; CHECK-CVT-SD-NEXT: fcmp s2, s3330; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $s0331; CHECK-CVT-SD-NEXT: // kill: def $h1 killed $h1 def $s1332; CHECK-CVT-SD-NEXT: fcsel s0, s0, s1, ne333; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $s0334; CHECK-CVT-SD-NEXT: ret335;336; CHECK-FP16-SD-LABEL: test_select_cc_f16_f32:337; CHECK-FP16-SD: // %bb.0:338; CHECK-FP16-SD-NEXT: fcmp s2, s3339; CHECK-FP16-SD-NEXT: fcsel h0, h0, h1, ne340; CHECK-FP16-SD-NEXT: ret341;342; CHECK-CVT-GI-LABEL: test_select_cc_f16_f32:343; CHECK-CVT-GI: // %bb.0:344; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0345; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $s1346; CHECK-CVT-GI-NEXT: fcmp s2, s3347; CHECK-CVT-GI-NEXT: fmov w8, s0348; CHECK-CVT-GI-NEXT: fmov w9, s1349; CHECK-CVT-GI-NEXT: csel w8, w8, w9, ne350; CHECK-CVT-GI-NEXT: fmov s0, w8351; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $s0352; CHECK-CVT-GI-NEXT: ret353;354; CHECK-FP16-GI-LABEL: test_select_cc_f16_f32:355; CHECK-FP16-GI: // %bb.0:356; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $s0357; CHECK-FP16-GI-NEXT: // kill: def $h1 killed $h1 def $s1358; CHECK-FP16-GI-NEXT: fcmp s2, s3359; CHECK-FP16-GI-NEXT: fmov w8, s0360; CHECK-FP16-GI-NEXT: fmov w9, s1361; CHECK-FP16-GI-NEXT: csel w8, w8, w9, ne362; CHECK-FP16-GI-NEXT: fmov s0, w8363; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $s0364; CHECK-FP16-GI-NEXT: ret365 %cc = fcmp une float %c, %d366 %r = select i1 %cc, half %a, half %b367 ret half %r368}369 370define i1 @test_fcmp_une(half %a, half %b) #0 {371; CHECK-CVT-SD-LABEL: test_fcmp_une:372; CHECK-CVT-SD: // %bb.0:373; CHECK-CVT-SD-NEXT: fcvt s1, h1374; CHECK-CVT-SD-NEXT: fcvt s0, h0375; CHECK-CVT-SD-NEXT: fcmp s0, s1376; CHECK-CVT-SD-NEXT: cset w0, ne377; CHECK-CVT-SD-NEXT: ret378;379; CHECK-FP16-LABEL: test_fcmp_une:380; CHECK-FP16: // %bb.0:381; CHECK-FP16-NEXT: fcmp h0, h1382; CHECK-FP16-NEXT: cset w0, ne383; CHECK-FP16-NEXT: ret384;385; CHECK-CVT-GI-LABEL: test_fcmp_une:386; CHECK-CVT-GI: // %bb.0:387; CHECK-CVT-GI-NEXT: fcvt s0, h0388; CHECK-CVT-GI-NEXT: fcvt s1, h1389; CHECK-CVT-GI-NEXT: fcmp s0, s1390; CHECK-CVT-GI-NEXT: cset w0, ne391; CHECK-CVT-GI-NEXT: ret392 %r = fcmp une half %a, %b393 ret i1 %r394}395 396define i1 @test_fcmp_ueq(half %a, half %b) #0 {397; CHECK-CVT-SD-LABEL: test_fcmp_ueq:398; CHECK-CVT-SD: // %bb.0:399; CHECK-CVT-SD-NEXT: fcvt s1, h1400; CHECK-CVT-SD-NEXT: fcvt s0, h0401; CHECK-CVT-SD-NEXT: fcmp s0, s1402; CHECK-CVT-SD-NEXT: cset w8, eq403; CHECK-CVT-SD-NEXT: csinc w0, w8, wzr, vc404; CHECK-CVT-SD-NEXT: ret405;406; CHECK-FP16-SD-LABEL: test_fcmp_ueq:407; CHECK-FP16-SD: // %bb.0:408; CHECK-FP16-SD-NEXT: fcmp h0, h1409; CHECK-FP16-SD-NEXT: cset w8, eq410; CHECK-FP16-SD-NEXT: csinc w0, w8, wzr, vc411; CHECK-FP16-SD-NEXT: ret412;413; CHECK-CVT-GI-LABEL: test_fcmp_ueq:414; CHECK-CVT-GI: // %bb.0:415; CHECK-CVT-GI-NEXT: fcvt s0, h0416; CHECK-CVT-GI-NEXT: fcvt s1, h1417; CHECK-CVT-GI-NEXT: fcmp s0, s1418; CHECK-CVT-GI-NEXT: cset w8, eq419; CHECK-CVT-GI-NEXT: cset w9, vs420; CHECK-CVT-GI-NEXT: orr w0, w8, w9421; CHECK-CVT-GI-NEXT: ret422;423; CHECK-FP16-GI-LABEL: test_fcmp_ueq:424; CHECK-FP16-GI: // %bb.0:425; CHECK-FP16-GI-NEXT: fcmp h0, h1426; CHECK-FP16-GI-NEXT: cset w8, eq427; CHECK-FP16-GI-NEXT: cset w9, vs428; CHECK-FP16-GI-NEXT: orr w0, w8, w9429; CHECK-FP16-GI-NEXT: ret430 %r = fcmp ueq half %a, %b431 ret i1 %r432}433 434define i1 @test_fcmp_ugt(half %a, half %b) #0 {435; CHECK-CVT-SD-LABEL: test_fcmp_ugt:436; CHECK-CVT-SD: // %bb.0:437; CHECK-CVT-SD-NEXT: fcvt s1, h1438; CHECK-CVT-SD-NEXT: fcvt s0, h0439; CHECK-CVT-SD-NEXT: fcmp s0, s1440; CHECK-CVT-SD-NEXT: cset w0, hi441; CHECK-CVT-SD-NEXT: ret442;443; CHECK-FP16-LABEL: test_fcmp_ugt:444; CHECK-FP16: // %bb.0:445; CHECK-FP16-NEXT: fcmp h0, h1446; CHECK-FP16-NEXT: cset w0, hi447; CHECK-FP16-NEXT: ret448;449; CHECK-CVT-GI-LABEL: test_fcmp_ugt:450; CHECK-CVT-GI: // %bb.0:451; CHECK-CVT-GI-NEXT: fcvt s0, h0452; CHECK-CVT-GI-NEXT: fcvt s1, h1453; CHECK-CVT-GI-NEXT: fcmp s0, s1454; CHECK-CVT-GI-NEXT: cset w0, hi455; CHECK-CVT-GI-NEXT: ret456 %r = fcmp ugt half %a, %b457 ret i1 %r458}459 460define i1 @test_fcmp_uge(half %a, half %b) #0 {461; CHECK-CVT-SD-LABEL: test_fcmp_uge:462; CHECK-CVT-SD: // %bb.0:463; CHECK-CVT-SD-NEXT: fcvt s1, h1464; CHECK-CVT-SD-NEXT: fcvt s0, h0465; CHECK-CVT-SD-NEXT: fcmp s0, s1466; CHECK-CVT-SD-NEXT: cset w0, pl467; CHECK-CVT-SD-NEXT: ret468;469; CHECK-FP16-LABEL: test_fcmp_uge:470; CHECK-FP16: // %bb.0:471; CHECK-FP16-NEXT: fcmp h0, h1472; CHECK-FP16-NEXT: cset w0, pl473; CHECK-FP16-NEXT: ret474;475; CHECK-CVT-GI-LABEL: test_fcmp_uge:476; CHECK-CVT-GI: // %bb.0:477; CHECK-CVT-GI-NEXT: fcvt s0, h0478; CHECK-CVT-GI-NEXT: fcvt s1, h1479; CHECK-CVT-GI-NEXT: fcmp s0, s1480; CHECK-CVT-GI-NEXT: cset w0, pl481; CHECK-CVT-GI-NEXT: ret482 %r = fcmp uge half %a, %b483 ret i1 %r484}485 486define i1 @test_fcmp_ult(half %a, half %b) #0 {487; CHECK-CVT-SD-LABEL: test_fcmp_ult:488; CHECK-CVT-SD: // %bb.0:489; CHECK-CVT-SD-NEXT: fcvt s1, h1490; CHECK-CVT-SD-NEXT: fcvt s0, h0491; CHECK-CVT-SD-NEXT: fcmp s0, s1492; CHECK-CVT-SD-NEXT: cset w0, lt493; CHECK-CVT-SD-NEXT: ret494;495; CHECK-FP16-LABEL: test_fcmp_ult:496; CHECK-FP16: // %bb.0:497; CHECK-FP16-NEXT: fcmp h0, h1498; CHECK-FP16-NEXT: cset w0, lt499; CHECK-FP16-NEXT: ret500;501; CHECK-CVT-GI-LABEL: test_fcmp_ult:502; CHECK-CVT-GI: // %bb.0:503; CHECK-CVT-GI-NEXT: fcvt s0, h0504; CHECK-CVT-GI-NEXT: fcvt s1, h1505; CHECK-CVT-GI-NEXT: fcmp s0, s1506; CHECK-CVT-GI-NEXT: cset w0, lt507; CHECK-CVT-GI-NEXT: ret508 %r = fcmp ult half %a, %b509 ret i1 %r510}511 512define i1 @test_fcmp_ule(half %a, half %b) #0 {513; CHECK-CVT-SD-LABEL: test_fcmp_ule:514; CHECK-CVT-SD: // %bb.0:515; CHECK-CVT-SD-NEXT: fcvt s1, h1516; CHECK-CVT-SD-NEXT: fcvt s0, h0517; CHECK-CVT-SD-NEXT: fcmp s0, s1518; CHECK-CVT-SD-NEXT: cset w0, le519; CHECK-CVT-SD-NEXT: ret520;521; CHECK-FP16-LABEL: test_fcmp_ule:522; CHECK-FP16: // %bb.0:523; CHECK-FP16-NEXT: fcmp h0, h1524; CHECK-FP16-NEXT: cset w0, le525; CHECK-FP16-NEXT: ret526;527; CHECK-CVT-GI-LABEL: test_fcmp_ule:528; CHECK-CVT-GI: // %bb.0:529; CHECK-CVT-GI-NEXT: fcvt s0, h0530; CHECK-CVT-GI-NEXT: fcvt s1, h1531; CHECK-CVT-GI-NEXT: fcmp s0, s1532; CHECK-CVT-GI-NEXT: cset w0, le533; CHECK-CVT-GI-NEXT: ret534 %r = fcmp ule half %a, %b535 ret i1 %r536}537 538define i1 @test_fcmp_uno(half %a, half %b) #0 {539; CHECK-CVT-SD-LABEL: test_fcmp_uno:540; CHECK-CVT-SD: // %bb.0:541; CHECK-CVT-SD-NEXT: fcvt s1, h1542; CHECK-CVT-SD-NEXT: fcvt s0, h0543; CHECK-CVT-SD-NEXT: fcmp s0, s1544; CHECK-CVT-SD-NEXT: cset w0, vs545; CHECK-CVT-SD-NEXT: ret546;547; CHECK-FP16-LABEL: test_fcmp_uno:548; CHECK-FP16: // %bb.0:549; CHECK-FP16-NEXT: fcmp h0, h1550; CHECK-FP16-NEXT: cset w0, vs551; CHECK-FP16-NEXT: ret552;553; CHECK-CVT-GI-LABEL: test_fcmp_uno:554; CHECK-CVT-GI: // %bb.0:555; CHECK-CVT-GI-NEXT: fcvt s0, h0556; CHECK-CVT-GI-NEXT: fcvt s1, h1557; CHECK-CVT-GI-NEXT: fcmp s0, s1558; CHECK-CVT-GI-NEXT: cset w0, vs559; CHECK-CVT-GI-NEXT: ret560 %r = fcmp uno half %a, %b561 ret i1 %r562}563 564define i1 @test_fcmp_one(half %a, half %b) #0 {565; CHECK-CVT-SD-LABEL: test_fcmp_one:566; CHECK-CVT-SD: // %bb.0:567; CHECK-CVT-SD-NEXT: fcvt s1, h1568; CHECK-CVT-SD-NEXT: fcvt s0, h0569; CHECK-CVT-SD-NEXT: fcmp s0, s1570; CHECK-CVT-SD-NEXT: cset w8, mi571; CHECK-CVT-SD-NEXT: csinc w0, w8, wzr, le572; CHECK-CVT-SD-NEXT: ret573;574; CHECK-FP16-SD-LABEL: test_fcmp_one:575; CHECK-FP16-SD: // %bb.0:576; CHECK-FP16-SD-NEXT: fcmp h0, h1577; CHECK-FP16-SD-NEXT: cset w8, mi578; CHECK-FP16-SD-NEXT: csinc w0, w8, wzr, le579; CHECK-FP16-SD-NEXT: ret580;581; CHECK-CVT-GI-LABEL: test_fcmp_one:582; CHECK-CVT-GI: // %bb.0:583; CHECK-CVT-GI-NEXT: fcvt s0, h0584; CHECK-CVT-GI-NEXT: fcvt s1, h1585; CHECK-CVT-GI-NEXT: fcmp s0, s1586; CHECK-CVT-GI-NEXT: cset w8, mi587; CHECK-CVT-GI-NEXT: cset w9, gt588; CHECK-CVT-GI-NEXT: orr w0, w8, w9589; CHECK-CVT-GI-NEXT: ret590;591; CHECK-FP16-GI-LABEL: test_fcmp_one:592; CHECK-FP16-GI: // %bb.0:593; CHECK-FP16-GI-NEXT: fcmp h0, h1594; CHECK-FP16-GI-NEXT: cset w8, mi595; CHECK-FP16-GI-NEXT: cset w9, gt596; CHECK-FP16-GI-NEXT: orr w0, w8, w9597; CHECK-FP16-GI-NEXT: ret598 %r = fcmp one half %a, %b599 ret i1 %r600}601 602define i1 @test_fcmp_oeq(half %a, half %b) #0 {603; CHECK-CVT-SD-LABEL: test_fcmp_oeq:604; CHECK-CVT-SD: // %bb.0:605; CHECK-CVT-SD-NEXT: fcvt s1, h1606; CHECK-CVT-SD-NEXT: fcvt s0, h0607; CHECK-CVT-SD-NEXT: fcmp s0, s1608; CHECK-CVT-SD-NEXT: cset w0, eq609; CHECK-CVT-SD-NEXT: ret610;611; CHECK-FP16-LABEL: test_fcmp_oeq:612; CHECK-FP16: // %bb.0:613; CHECK-FP16-NEXT: fcmp h0, h1614; CHECK-FP16-NEXT: cset w0, eq615; CHECK-FP16-NEXT: ret616;617; CHECK-CVT-GI-LABEL: test_fcmp_oeq:618; CHECK-CVT-GI: // %bb.0:619; CHECK-CVT-GI-NEXT: fcvt s0, h0620; CHECK-CVT-GI-NEXT: fcvt s1, h1621; CHECK-CVT-GI-NEXT: fcmp s0, s1622; CHECK-CVT-GI-NEXT: cset w0, eq623; CHECK-CVT-GI-NEXT: ret624 %r = fcmp oeq half %a, %b625 ret i1 %r626}627 628define i1 @test_fcmp_ogt(half %a, half %b) #0 {629; CHECK-CVT-SD-LABEL: test_fcmp_ogt:630; CHECK-CVT-SD: // %bb.0:631; CHECK-CVT-SD-NEXT: fcvt s1, h1632; CHECK-CVT-SD-NEXT: fcvt s0, h0633; CHECK-CVT-SD-NEXT: fcmp s0, s1634; CHECK-CVT-SD-NEXT: cset w0, gt635; CHECK-CVT-SD-NEXT: ret636;637; CHECK-FP16-LABEL: test_fcmp_ogt:638; CHECK-FP16: // %bb.0:639; CHECK-FP16-NEXT: fcmp h0, h1640; CHECK-FP16-NEXT: cset w0, gt641; CHECK-FP16-NEXT: ret642;643; CHECK-CVT-GI-LABEL: test_fcmp_ogt:644; CHECK-CVT-GI: // %bb.0:645; CHECK-CVT-GI-NEXT: fcvt s0, h0646; CHECK-CVT-GI-NEXT: fcvt s1, h1647; CHECK-CVT-GI-NEXT: fcmp s0, s1648; CHECK-CVT-GI-NEXT: cset w0, gt649; CHECK-CVT-GI-NEXT: ret650 %r = fcmp ogt half %a, %b651 ret i1 %r652}653 654define i1 @test_fcmp_oge(half %a, half %b) #0 {655; CHECK-CVT-SD-LABEL: test_fcmp_oge:656; CHECK-CVT-SD: // %bb.0:657; CHECK-CVT-SD-NEXT: fcvt s1, h1658; CHECK-CVT-SD-NEXT: fcvt s0, h0659; CHECK-CVT-SD-NEXT: fcmp s0, s1660; CHECK-CVT-SD-NEXT: cset w0, ge661; CHECK-CVT-SD-NEXT: ret662;663; CHECK-FP16-LABEL: test_fcmp_oge:664; CHECK-FP16: // %bb.0:665; CHECK-FP16-NEXT: fcmp h0, h1666; CHECK-FP16-NEXT: cset w0, ge667; CHECK-FP16-NEXT: ret668;669; CHECK-CVT-GI-LABEL: test_fcmp_oge:670; CHECK-CVT-GI: // %bb.0:671; CHECK-CVT-GI-NEXT: fcvt s0, h0672; CHECK-CVT-GI-NEXT: fcvt s1, h1673; CHECK-CVT-GI-NEXT: fcmp s0, s1674; CHECK-CVT-GI-NEXT: cset w0, ge675; CHECK-CVT-GI-NEXT: ret676 %r = fcmp oge half %a, %b677 ret i1 %r678}679 680define i1 @test_fcmp_olt(half %a, half %b) #0 {681; CHECK-CVT-SD-LABEL: test_fcmp_olt:682; CHECK-CVT-SD: // %bb.0:683; CHECK-CVT-SD-NEXT: fcvt s1, h1684; CHECK-CVT-SD-NEXT: fcvt s0, h0685; CHECK-CVT-SD-NEXT: fcmp s0, s1686; CHECK-CVT-SD-NEXT: cset w0, mi687; CHECK-CVT-SD-NEXT: ret688;689; CHECK-FP16-LABEL: test_fcmp_olt:690; CHECK-FP16: // %bb.0:691; CHECK-FP16-NEXT: fcmp h0, h1692; CHECK-FP16-NEXT: cset w0, mi693; CHECK-FP16-NEXT: ret694;695; CHECK-CVT-GI-LABEL: test_fcmp_olt:696; CHECK-CVT-GI: // %bb.0:697; CHECK-CVT-GI-NEXT: fcvt s0, h0698; CHECK-CVT-GI-NEXT: fcvt s1, h1699; CHECK-CVT-GI-NEXT: fcmp s0, s1700; CHECK-CVT-GI-NEXT: cset w0, mi701; CHECK-CVT-GI-NEXT: ret702 %r = fcmp olt half %a, %b703 ret i1 %r704}705 706define i1 @test_fcmp_ole(half %a, half %b) #0 {707; CHECK-CVT-SD-LABEL: test_fcmp_ole:708; CHECK-CVT-SD: // %bb.0:709; CHECK-CVT-SD-NEXT: fcvt s1, h1710; CHECK-CVT-SD-NEXT: fcvt s0, h0711; CHECK-CVT-SD-NEXT: fcmp s0, s1712; CHECK-CVT-SD-NEXT: cset w0, ls713; CHECK-CVT-SD-NEXT: ret714;715; CHECK-FP16-LABEL: test_fcmp_ole:716; CHECK-FP16: // %bb.0:717; CHECK-FP16-NEXT: fcmp h0, h1718; CHECK-FP16-NEXT: cset w0, ls719; CHECK-FP16-NEXT: ret720;721; CHECK-CVT-GI-LABEL: test_fcmp_ole:722; CHECK-CVT-GI: // %bb.0:723; CHECK-CVT-GI-NEXT: fcvt s0, h0724; CHECK-CVT-GI-NEXT: fcvt s1, h1725; CHECK-CVT-GI-NEXT: fcmp s0, s1726; CHECK-CVT-GI-NEXT: cset w0, ls727; CHECK-CVT-GI-NEXT: ret728 %r = fcmp ole half %a, %b729 ret i1 %r730}731 732define i1 @test_fcmp_ord(half %a, half %b) #0 {733; CHECK-CVT-SD-LABEL: test_fcmp_ord:734; CHECK-CVT-SD: // %bb.0:735; CHECK-CVT-SD-NEXT: fcvt s1, h1736; CHECK-CVT-SD-NEXT: fcvt s0, h0737; CHECK-CVT-SD-NEXT: fcmp s0, s1738; CHECK-CVT-SD-NEXT: cset w0, vc739; CHECK-CVT-SD-NEXT: ret740;741; CHECK-FP16-LABEL: test_fcmp_ord:742; CHECK-FP16: // %bb.0:743; CHECK-FP16-NEXT: fcmp h0, h1744; CHECK-FP16-NEXT: cset w0, vc745; CHECK-FP16-NEXT: ret746;747; CHECK-CVT-GI-LABEL: test_fcmp_ord:748; CHECK-CVT-GI: // %bb.0:749; CHECK-CVT-GI-NEXT: fcvt s0, h0750; CHECK-CVT-GI-NEXT: fcvt s1, h1751; CHECK-CVT-GI-NEXT: fcmp s0, s1752; CHECK-CVT-GI-NEXT: cset w0, vc753; CHECK-CVT-GI-NEXT: ret754 %r = fcmp ord half %a, %b755 ret i1 %r756}757 758define void @test_fccmp(half %in, ptr %out) {759; CHECK-CVT-SD-LABEL: test_fccmp:760; CHECK-CVT-SD: // %bb.0:761; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $s0762; CHECK-CVT-SD-NEXT: fcvt s1, h0763; CHECK-CVT-SD-NEXT: fmov s2, #5.00000000764; CHECK-CVT-SD-NEXT: adrp x8, .LCPI29_0765; CHECK-CVT-SD-NEXT: fcmp s1, s2766; CHECK-CVT-SD-NEXT: fmov s2, #8.00000000767; CHECK-CVT-SD-NEXT: fccmp s1, s2, #4, mi768; CHECK-CVT-SD-NEXT: ldr h1, [x8, :lo12:.LCPI29_0]769; CHECK-CVT-SD-NEXT: fcsel s0, s0, s1, gt770; CHECK-CVT-SD-NEXT: str h0, [x0]771; CHECK-CVT-SD-NEXT: ret772;773; CHECK-FP16-SD-LABEL: test_fccmp:774; CHECK-FP16-SD: // %bb.0:775; CHECK-FP16-SD-NEXT: fmov h1, #5.00000000776; CHECK-FP16-SD-NEXT: fmov h2, #8.00000000777; CHECK-FP16-SD-NEXT: fcmp h0, h1778; CHECK-FP16-SD-NEXT: fccmp h0, h2, #4, mi779; CHECK-FP16-SD-NEXT: fcsel h0, h0, h1, gt780; CHECK-FP16-SD-NEXT: str h0, [x0]781; CHECK-FP16-SD-NEXT: ret782;783; CHECK-CVT-GI-LABEL: test_fccmp:784; CHECK-CVT-GI: // %bb.0:785; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0786; CHECK-CVT-GI-NEXT: fcvt s1, h0787; CHECK-CVT-GI-NEXT: fmov s2, #5.00000000788; CHECK-CVT-GI-NEXT: adrp x8, .LCPI29_0789; CHECK-CVT-GI-NEXT: fmov s3, #8.00000000790; CHECK-CVT-GI-NEXT: fcmp s1, s2791; CHECK-CVT-GI-NEXT: ldr h2, [x8, :lo12:.LCPI29_0]792; CHECK-CVT-GI-NEXT: fmov w8, s0793; CHECK-CVT-GI-NEXT: fmov w9, s2794; CHECK-CVT-GI-NEXT: fccmp s1, s3, #4, mi795; CHECK-CVT-GI-NEXT: csel w8, w8, w9, gt796; CHECK-CVT-GI-NEXT: strh w8, [x0]797; CHECK-CVT-GI-NEXT: ret798;799; CHECK-FP16-GI-LABEL: test_fccmp:800; CHECK-FP16-GI: // %bb.0:801; CHECK-FP16-GI-NEXT: fmov h1, #5.00000000802; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $s0803; CHECK-FP16-GI-NEXT: fmov h2, #8.00000000804; CHECK-FP16-GI-NEXT: fmov w8, s0805; CHECK-FP16-GI-NEXT: fcmp h0, h1806; CHECK-FP16-GI-NEXT: fmov w9, s1807; CHECK-FP16-GI-NEXT: fccmp h0, h2, #4, mi808; CHECK-FP16-GI-NEXT: csel w8, w8, w9, gt809; CHECK-FP16-GI-NEXT: strh w8, [x0]810; CHECK-FP16-GI-NEXT: ret811 %cmp1 = fcmp ogt half %in, 0xH4800812 %cmp2 = fcmp olt half %in, 0xH4500813 %cond = and i1 %cmp1, %cmp2814 %result = select i1 %cond, half %in, half 0xH4500815 store half %result, ptr %out816 ret void817}818 819define void @test_br_cc(half %a, half %b, ptr %p1, ptr %p2) #0 {820; CHECK-CVT-SD-LABEL: test_br_cc:821; CHECK-CVT-SD: // %bb.0: // %common.ret822; CHECK-CVT-SD-NEXT: fcvt s1, h1823; CHECK-CVT-SD-NEXT: fcvt s0, h0824; CHECK-CVT-SD-NEXT: fcmp s0, s1825; CHECK-CVT-SD-NEXT: csel x8, x0, x1, pl826; CHECK-CVT-SD-NEXT: str wzr, [x8]827; CHECK-CVT-SD-NEXT: ret828;829; CHECK-FP16-LABEL: test_br_cc:830; CHECK-FP16: // %bb.0: // %common.ret831; CHECK-FP16-NEXT: fcmp h0, h1832; CHECK-FP16-NEXT: csel x8, x0, x1, pl833; CHECK-FP16-NEXT: str wzr, [x8]834; CHECK-FP16-NEXT: ret835;836; CHECK-CVT-GI-LABEL: test_br_cc:837; CHECK-CVT-GI: // %bb.0: // %common.ret838; CHECK-CVT-GI-NEXT: fcvt s0, h0839; CHECK-CVT-GI-NEXT: fcvt s1, h1840; CHECK-CVT-GI-NEXT: fcmp s0, s1841; CHECK-CVT-GI-NEXT: csel x8, x0, x1, pl842; CHECK-CVT-GI-NEXT: str wzr, [x8]843; CHECK-CVT-GI-NEXT: ret844 %c = fcmp uge half %a, %b845 br i1 %c, label %then, label %else846then:847 store i32 0, ptr %p1848 ret void849else:850 store i32 0, ptr %p2851 ret void852}853 854define half @test_phi(ptr %p1) #0 {855; CHECK-LABEL: test_phi:856; CHECK: // %bb.0: // %entry857; CHECK-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill858; CHECK-NEXT: ldr h9, [x0]859; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill860; CHECK-NEXT: mov x19, x0861; CHECK-NEXT: .LBB31_1: // %loop862; CHECK-NEXT: // =>This Inner Loop Header: Depth=1863; CHECK-NEXT: fmov s8, s9864; CHECK-NEXT: ldr h9, [x19]865; CHECK-NEXT: mov x0, x19866; CHECK-NEXT: bl test_dummy867; CHECK-NEXT: tbnz w0, #0, .LBB31_1868; CHECK-NEXT: // %bb.2: // %return869; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload870; CHECK-NEXT: fmov s0, s8871; CHECK-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload872; CHECK-NEXT: ret873entry:874 %a = load half, ptr %p1875 br label %loop876loop:877 %r = phi half [%a, %entry], [%b, %loop]878 %b = load half, ptr %p1879 %c = call i1 @test_dummy(ptr %p1)880 br i1 %c, label %loop, label %return881return:882 ret half %r883}884 885declare i1 @test_dummy(ptr %p1) #0886 887define i32 @test_fptosi_i32(half %a) #0 {888; CHECK-CVT-LABEL: test_fptosi_i32:889; CHECK-CVT: // %bb.0:890; CHECK-CVT-NEXT: fcvt s0, h0891; CHECK-CVT-NEXT: fcvtzs w0, s0892; CHECK-CVT-NEXT: ret893;894; CHECK-FP16-LABEL: test_fptosi_i32:895; CHECK-FP16: // %bb.0:896; CHECK-FP16-NEXT: fcvtzs w0, h0897; CHECK-FP16-NEXT: ret898 %r = fptosi half %a to i32899 ret i32 %r900}901 902define i64 @test_fptosi_i64(half %a) #0 {903; CHECK-CVT-LABEL: test_fptosi_i64:904; CHECK-CVT: // %bb.0:905; CHECK-CVT-NEXT: fcvt s0, h0906; CHECK-CVT-NEXT: fcvtzs x0, s0907; CHECK-CVT-NEXT: ret908;909; CHECK-FP16-LABEL: test_fptosi_i64:910; CHECK-FP16: // %bb.0:911; CHECK-FP16-NEXT: fcvtzs x0, h0912; CHECK-FP16-NEXT: ret913 %r = fptosi half %a to i64914 ret i64 %r915}916 917define i32 @test_fptoui_i32(half %a) #0 {918; CHECK-CVT-LABEL: test_fptoui_i32:919; CHECK-CVT: // %bb.0:920; CHECK-CVT-NEXT: fcvt s0, h0921; CHECK-CVT-NEXT: fcvtzu w0, s0922; CHECK-CVT-NEXT: ret923;924; CHECK-FP16-LABEL: test_fptoui_i32:925; CHECK-FP16: // %bb.0:926; CHECK-FP16-NEXT: fcvtzu w0, h0927; CHECK-FP16-NEXT: ret928 %r = fptoui half %a to i32929 ret i32 %r930}931 932define i64 @test_fptoui_i64(half %a) #0 {933; CHECK-CVT-LABEL: test_fptoui_i64:934; CHECK-CVT: // %bb.0:935; CHECK-CVT-NEXT: fcvt s0, h0936; CHECK-CVT-NEXT: fcvtzu x0, s0937; CHECK-CVT-NEXT: ret938;939; CHECK-FP16-LABEL: test_fptoui_i64:940; CHECK-FP16: // %bb.0:941; CHECK-FP16-NEXT: fcvtzu x0, h0942; CHECK-FP16-NEXT: ret943 %r = fptoui half %a to i64944 ret i64 %r945}946 947define half @test_uitofp_i32(i32 %a) #0 {948; CHECK-CVT-LABEL: test_uitofp_i32:949; CHECK-CVT: // %bb.0:950; CHECK-CVT-NEXT: ucvtf s0, w0951; CHECK-CVT-NEXT: fcvt h0, s0952; CHECK-CVT-NEXT: ret953;954; CHECK-FP16-LABEL: test_uitofp_i32:955; CHECK-FP16: // %bb.0:956; CHECK-FP16-NEXT: ucvtf h0, w0957; CHECK-FP16-NEXT: ret958 %r = uitofp i32 %a to half959 ret half %r960}961 962define half @test_uitofp_i64(i64 %a) #0 {963; CHECK-CVT-LABEL: test_uitofp_i64:964; CHECK-CVT: // %bb.0:965; CHECK-CVT-NEXT: ucvtf s0, x0966; CHECK-CVT-NEXT: fcvt h0, s0967; CHECK-CVT-NEXT: ret968;969; CHECK-FP16-LABEL: test_uitofp_i64:970; CHECK-FP16: // %bb.0:971; CHECK-FP16-NEXT: ucvtf h0, x0972; CHECK-FP16-NEXT: ret973 %r = uitofp i64 %a to half974 ret half %r975}976 977define half @test_sitofp_i32(i32 %a) #0 {978; CHECK-CVT-LABEL: test_sitofp_i32:979; CHECK-CVT: // %bb.0:980; CHECK-CVT-NEXT: scvtf s0, w0981; CHECK-CVT-NEXT: fcvt h0, s0982; CHECK-CVT-NEXT: ret983;984; CHECK-FP16-LABEL: test_sitofp_i32:985; CHECK-FP16: // %bb.0:986; CHECK-FP16-NEXT: scvtf h0, w0987; CHECK-FP16-NEXT: ret988 %r = sitofp i32 %a to half989 ret half %r990}991 992define half @test_sitofp_i64(i64 %a) #0 {993; CHECK-CVT-LABEL: test_sitofp_i64:994; CHECK-CVT: // %bb.0:995; CHECK-CVT-NEXT: scvtf s0, x0996; CHECK-CVT-NEXT: fcvt h0, s0997; CHECK-CVT-NEXT: ret998;999; CHECK-FP16-LABEL: test_sitofp_i64:1000; CHECK-FP16: // %bb.0:1001; CHECK-FP16-NEXT: scvtf h0, x01002; CHECK-FP16-NEXT: ret1003 %r = sitofp i64 %a to half1004 ret half %r1005}1006 1007define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 {1008; CHECK-CVT-LABEL: test_uitofp_i32_fadd:1009; CHECK-CVT: // %bb.0:1010; CHECK-CVT-NEXT: ucvtf s1, w01011; CHECK-CVT-NEXT: fcvt s0, h01012; CHECK-CVT-NEXT: fcvt h1, s11013; CHECK-CVT-NEXT: fcvt s1, h11014; CHECK-CVT-NEXT: fadd s0, s0, s11015; CHECK-CVT-NEXT: fcvt h0, s01016; CHECK-CVT-NEXT: ret1017;1018; CHECK-FP16-LABEL: test_uitofp_i32_fadd:1019; CHECK-FP16: // %bb.0:1020; CHECK-FP16-NEXT: ucvtf h1, w01021; CHECK-FP16-NEXT: fadd h0, h0, h11022; CHECK-FP16-NEXT: ret1023 %c = uitofp i32 %a to half1024 %r = fadd half %b, %c1025 ret half %r1026}1027 1028define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 {1029; CHECK-CVT-LABEL: test_sitofp_i32_fadd:1030; CHECK-CVT: // %bb.0:1031; CHECK-CVT-NEXT: scvtf s1, w01032; CHECK-CVT-NEXT: fcvt s0, h01033; CHECK-CVT-NEXT: fcvt h1, s11034; CHECK-CVT-NEXT: fcvt s1, h11035; CHECK-CVT-NEXT: fadd s0, s0, s11036; CHECK-CVT-NEXT: fcvt h0, s01037; CHECK-CVT-NEXT: ret1038;1039; CHECK-FP16-LABEL: test_sitofp_i32_fadd:1040; CHECK-FP16: // %bb.0:1041; CHECK-FP16-NEXT: scvtf h1, w01042; CHECK-FP16-NEXT: fadd h0, h0, h11043; CHECK-FP16-NEXT: ret1044 %c = sitofp i32 %a to half1045 %r = fadd half %b, %c1046 ret half %r1047}1048 1049define half @test_fptrunc_float(float %a) #0 {1050; CHECK-LABEL: test_fptrunc_float:1051; CHECK: // %bb.0:1052; CHECK-NEXT: fcvt h0, s01053; CHECK-NEXT: ret1054 %r = fptrunc float %a to half1055 ret half %r1056}1057 1058define half @test_fptrunc_double(double %a) #0 {1059; CHECK-LABEL: test_fptrunc_double:1060; CHECK: // %bb.0:1061; CHECK-NEXT: fcvt h0, d01062; CHECK-NEXT: ret1063 %r = fptrunc double %a to half1064 ret half %r1065}1066 1067define float @test_fpext_float(half %a) #0 {1068; CHECK-LABEL: test_fpext_float:1069; CHECK: // %bb.0:1070; CHECK-NEXT: fcvt s0, h01071; CHECK-NEXT: ret1072 %r = fpext half %a to float1073 ret float %r1074}1075 1076define double @test_fpext_double(half %a) #0 {1077; CHECK-LABEL: test_fpext_double:1078; CHECK: // %bb.0:1079; CHECK-NEXT: fcvt d0, h01080; CHECK-NEXT: ret1081 %r = fpext half %a to double1082 ret double %r1083}1084 1085define i16 @test_bitcast_halftoi16(half %a) #0 {1086; CHECK-LABEL: test_bitcast_halftoi16:1087; CHECK: // %bb.0:1088; CHECK-NEXT: // kill: def $h0 killed $h0 def $s01089; CHECK-NEXT: fmov w0, s01090; CHECK-NEXT: ret1091 %r = bitcast half %a to i161092 ret i16 %r1093}1094 1095define half @test_bitcast_i16tohalf(i16 %a) #0 {1096; CHECK-LABEL: test_bitcast_i16tohalf:1097; CHECK: // %bb.0:1098; CHECK-NEXT: fmov s0, w01099; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s01100; CHECK-NEXT: ret1101 %r = bitcast i16 %a to half1102 ret half %r1103}1104 1105declare half @llvm.sqrt.f16(half %a) #01106declare half @llvm.powi.f16.i32(half %a, i32 %b) #01107declare half @llvm.sin.f16(half %a) #01108declare half @llvm.cos.f16(half %a) #01109declare half @llvm.tan.f16(half %a) #01110declare half @llvm.asin.f16(half %a) #01111declare half @llvm.acos.f16(half %a) #01112declare half @llvm.atan.f16(half %a) #01113declare half @llvm.atan2.f16(half %a, half %b) #01114declare half @llvm.sinh.f16(half %a) #01115declare half @llvm.cosh.f16(half %a) #01116declare half @llvm.tanh.f16(half %a) #01117declare half @llvm.pow.f16(half %a, half %b) #01118declare half @llvm.exp.f16(half %a) #01119declare half @llvm.exp2.f16(half %a) #01120declare half @llvm.log.f16(half %a) #01121declare half @llvm.log10.f16(half %a) #01122declare half @llvm.log2.f16(half %a) #01123declare half @llvm.fma.f16(half %a, half %b, half %c) #01124declare half @llvm.fabs.f16(half %a) #01125declare half @llvm.minnum.f16(half %a, half %b) #01126declare half @llvm.maxnum.f16(half %a, half %b) #01127declare half @llvm.copysign.f16(half %a, half %b) #01128declare half @llvm.floor.f16(half %a) #01129declare half @llvm.ceil.f16(half %a) #01130declare half @llvm.trunc.f16(half %a) #01131declare half @llvm.rint.f16(half %a) #01132declare half @llvm.nearbyint.f16(half %a) #01133declare half @llvm.round.f16(half %a) #01134declare half @llvm.roundeven.f16(half %a) #01135declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #01136 1137 1138define half @test_sqrt(half %a) #0 {1139; CHECK-CVT-LABEL: test_sqrt:1140; CHECK-CVT: // %bb.0:1141; CHECK-CVT-NEXT: fcvt s0, h01142; CHECK-CVT-NEXT: fsqrt s0, s01143; CHECK-CVT-NEXT: fcvt h0, s01144; CHECK-CVT-NEXT: ret1145;1146; CHECK-FP16-LABEL: test_sqrt:1147; CHECK-FP16: // %bb.0:1148; CHECK-FP16-NEXT: fsqrt h0, h01149; CHECK-FP16-NEXT: ret1150 %r = call half @llvm.sqrt.f16(half %a)1151 ret half %r1152}1153 1154define half @test_powi(half %a, i32 %b) #0 {1155; CHECK-LABEL: test_powi:1156; CHECK: // %bb.0:1157; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1158; CHECK-NEXT: fcvt s0, h01159; CHECK-NEXT: bl __powisf21160; CHECK-NEXT: fcvt h0, s01161; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1162; CHECK-NEXT: ret1163 %r = call half @llvm.powi.f16.i32(half %a, i32 %b)1164 ret half %r1165}1166 1167 1168define half @test_sin(half %a) #0 {1169; CHECK-LABEL: test_sin:1170; CHECK: // %bb.0:1171; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1172; CHECK-NEXT: fcvt s0, h01173; CHECK-NEXT: bl sinf1174; CHECK-NEXT: fcvt h0, s01175; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1176; CHECK-NEXT: ret1177 %r = call half @llvm.sin.f16(half %a)1178 ret half %r1179}1180 1181define half @test_cos(half %a) #0 {1182; CHECK-LABEL: test_cos:1183; CHECK: // %bb.0:1184; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1185; CHECK-NEXT: fcvt s0, h01186; CHECK-NEXT: bl cosf1187; CHECK-NEXT: fcvt h0, s01188; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1189; CHECK-NEXT: ret1190 %r = call half @llvm.cos.f16(half %a)1191 ret half %r1192}1193 1194define half @test_tan(half %a) #0 {1195; CHECK-LABEL: test_tan:1196; CHECK: // %bb.0:1197; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1198; CHECK-NEXT: fcvt s0, h01199; CHECK-NEXT: bl tanf1200; CHECK-NEXT: fcvt h0, s01201; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1202; CHECK-NEXT: ret1203 %r = call half @llvm.tan.f16(half %a)1204 ret half %r1205}1206 1207define half @test_acos(half %a) #0 {1208; CHECK-LABEL: test_acos:1209; CHECK: // %bb.0:1210; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1211; CHECK-NEXT: fcvt s0, h01212; CHECK-NEXT: bl acosf1213; CHECK-NEXT: fcvt h0, s01214; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1215; CHECK-NEXT: ret1216 %r = call half @llvm.acos.f16(half %a)1217 ret half %r1218}1219 1220define half @test_asin(half %a) #0 {1221; CHECK-LABEL: test_asin:1222; CHECK: // %bb.0:1223; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1224; CHECK-NEXT: fcvt s0, h01225; CHECK-NEXT: bl asinf1226; CHECK-NEXT: fcvt h0, s01227; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1228; CHECK-NEXT: ret1229 %r = call half @llvm.asin.f16(half %a)1230 ret half %r1231}1232 1233define half @test_atan(half %a) #0 {1234; CHECK-LABEL: test_atan:1235; CHECK: // %bb.0:1236; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1237; CHECK-NEXT: fcvt s0, h01238; CHECK-NEXT: bl atanf1239; CHECK-NEXT: fcvt h0, s01240; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1241; CHECK-NEXT: ret1242 %r = call half @llvm.atan.f16(half %a)1243 ret half %r1244}1245 1246define half @test_atan2(half %a, half %b) #0 {1247; CHECK-LABEL: test_atan2:1248; CHECK: // %bb.0:1249; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1250; CHECK-NEXT: fcvt s0, h01251; CHECK-NEXT: fcvt s1, h11252; CHECK-NEXT: bl atan2f1253; CHECK-NEXT: fcvt h0, s01254; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1255; CHECK-NEXT: ret1256 %r = call half @llvm.atan2.f16(half %a, half %b)1257 ret half %r1258}1259 1260define half @test_cosh(half %a) #0 {1261; CHECK-LABEL: test_cosh:1262; CHECK: // %bb.0:1263; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1264; CHECK-NEXT: fcvt s0, h01265; CHECK-NEXT: bl coshf1266; CHECK-NEXT: fcvt h0, s01267; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1268; CHECK-NEXT: ret1269 %r = call half @llvm.cosh.f16(half %a)1270 ret half %r1271}1272 1273define half @test_sinh(half %a) #0 {1274; CHECK-LABEL: test_sinh:1275; CHECK: // %bb.0:1276; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1277; CHECK-NEXT: fcvt s0, h01278; CHECK-NEXT: bl sinhf1279; CHECK-NEXT: fcvt h0, s01280; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1281; CHECK-NEXT: ret1282 %r = call half @llvm.sinh.f16(half %a)1283 ret half %r1284}1285 1286define half @test_tanh(half %a) #0 {1287; CHECK-LABEL: test_tanh:1288; CHECK: // %bb.0:1289; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1290; CHECK-NEXT: fcvt s0, h01291; CHECK-NEXT: bl tanhf1292; CHECK-NEXT: fcvt h0, s01293; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1294; CHECK-NEXT: ret1295 %r = call half @llvm.tanh.f16(half %a)1296 ret half %r1297}1298 1299define half @test_pow(half %a, half %b) #0 {1300; CHECK-LABEL: test_pow:1301; CHECK: // %bb.0:1302; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1303; CHECK-NEXT: fcvt s0, h01304; CHECK-NEXT: fcvt s1, h11305; CHECK-NEXT: bl powf1306; CHECK-NEXT: fcvt h0, s01307; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1308; CHECK-NEXT: ret1309 %r = call half @llvm.pow.f16(half %a, half %b)1310 ret half %r1311}1312 1313define half @test_exp(half %a) #0 {1314; CHECK-LABEL: test_exp:1315; CHECK: // %bb.0:1316; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1317; CHECK-NEXT: fcvt s0, h01318; CHECK-NEXT: bl expf1319; CHECK-NEXT: fcvt h0, s01320; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1321; CHECK-NEXT: ret1322 %r = call half @llvm.exp.f16(half %a)1323 ret half %r1324}1325 1326define half @test_exp2(half %a) #0 {1327; CHECK-LABEL: test_exp2:1328; CHECK: // %bb.0:1329; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1330; CHECK-NEXT: fcvt s0, h01331; CHECK-NEXT: bl exp2f1332; CHECK-NEXT: fcvt h0, s01333; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1334; CHECK-NEXT: ret1335 %r = call half @llvm.exp2.f16(half %a)1336 ret half %r1337}1338 1339define half @test_log(half %a) #0 {1340; CHECK-LABEL: test_log:1341; CHECK: // %bb.0:1342; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1343; CHECK-NEXT: fcvt s0, h01344; CHECK-NEXT: bl logf1345; CHECK-NEXT: fcvt h0, s01346; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1347; CHECK-NEXT: ret1348 %r = call half @llvm.log.f16(half %a)1349 ret half %r1350}1351 1352define half @test_log10(half %a) #0 {1353; CHECK-LABEL: test_log10:1354; CHECK: // %bb.0:1355; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1356; CHECK-NEXT: fcvt s0, h01357; CHECK-NEXT: bl log10f1358; CHECK-NEXT: fcvt h0, s01359; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1360; CHECK-NEXT: ret1361 %r = call half @llvm.log10.f16(half %a)1362 ret half %r1363}1364 1365define half @test_log2(half %a) #0 {1366; CHECK-LABEL: test_log2:1367; CHECK: // %bb.0:1368; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1369; CHECK-NEXT: fcvt s0, h01370; CHECK-NEXT: bl log2f1371; CHECK-NEXT: fcvt h0, s01372; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1373; CHECK-NEXT: ret1374 %r = call half @llvm.log2.f16(half %a)1375 ret half %r1376}1377 1378define half @test_fma(half %a, half %b, half %c) #0 {1379; CHECK-CVT-SD-LABEL: test_fma:1380; CHECK-CVT-SD: // %bb.0:1381; CHECK-CVT-SD-NEXT: fcvt s2, h21382; CHECK-CVT-SD-NEXT: fcvt s1, h11383; CHECK-CVT-SD-NEXT: fcvt s0, h01384; CHECK-CVT-SD-NEXT: fmadd s0, s0, s1, s21385; CHECK-CVT-SD-NEXT: fcvt h0, s01386; CHECK-CVT-SD-NEXT: ret1387;1388; CHECK-FP16-LABEL: test_fma:1389; CHECK-FP16: // %bb.0:1390; CHECK-FP16-NEXT: fmadd h0, h0, h1, h21391; CHECK-FP16-NEXT: ret1392;1393; CHECK-CVT-GI-LABEL: test_fma:1394; CHECK-CVT-GI: // %bb.0:1395; CHECK-CVT-GI-NEXT: fcvt s0, h01396; CHECK-CVT-GI-NEXT: fcvt s1, h11397; CHECK-CVT-GI-NEXT: fcvt s2, h21398; CHECK-CVT-GI-NEXT: fmadd s0, s0, s1, s21399; CHECK-CVT-GI-NEXT: fcvt h0, s01400; CHECK-CVT-GI-NEXT: ret1401 %r = call half @llvm.fma.f16(half %a, half %b, half %c)1402 ret half %r1403}1404 1405define half @test_fabs(half %a) #0 {1406; CHECK-CVT-LABEL: test_fabs:1407; CHECK-CVT: // %bb.0:1408; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s01409; CHECK-CVT-NEXT: fmov w8, s01410; CHECK-CVT-NEXT: and w8, w8, #0x7fff1411; CHECK-CVT-NEXT: fmov s0, w81412; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s01413; CHECK-CVT-NEXT: ret1414;1415; CHECK-FP16-LABEL: test_fabs:1416; CHECK-FP16: // %bb.0:1417; CHECK-FP16-NEXT: fabs h0, h01418; CHECK-FP16-NEXT: ret1419 %r = call half @llvm.fabs.f16(half %a)1420 ret half %r1421}1422 1423define half @test_minnum(half %a, half %b) #0 {1424; CHECK-CVT-SD-LABEL: test_minnum:1425; CHECK-CVT-SD: // %bb.0:1426; CHECK-CVT-SD-NEXT: fcvt s1, h11427; CHECK-CVT-SD-NEXT: fcvt s0, h01428; CHECK-CVT-SD-NEXT: fminnm s0, s0, s11429; CHECK-CVT-SD-NEXT: fcvt h0, s01430; CHECK-CVT-SD-NEXT: ret1431;1432; CHECK-FP16-LABEL: test_minnum:1433; CHECK-FP16: // %bb.0:1434; CHECK-FP16-NEXT: fminnm h0, h0, h11435; CHECK-FP16-NEXT: ret1436;1437; CHECK-CVT-GI-LABEL: test_minnum:1438; CHECK-CVT-GI: // %bb.0:1439; CHECK-CVT-GI-NEXT: fcvt s0, h01440; CHECK-CVT-GI-NEXT: fcvt s1, h11441; CHECK-CVT-GI-NEXT: fminnm s0, s0, s11442; CHECK-CVT-GI-NEXT: fcvt h0, s01443; CHECK-CVT-GI-NEXT: ret1444 %r = call half @llvm.minnum.f16(half %a, half %b)1445 ret half %r1446}1447 1448define half @test_maxnum(half %a, half %b) #0 {1449; CHECK-CVT-SD-LABEL: test_maxnum:1450; CHECK-CVT-SD: // %bb.0:1451; CHECK-CVT-SD-NEXT: fcvt s1, h11452; CHECK-CVT-SD-NEXT: fcvt s0, h01453; CHECK-CVT-SD-NEXT: fmaxnm s0, s0, s11454; CHECK-CVT-SD-NEXT: fcvt h0, s01455; CHECK-CVT-SD-NEXT: ret1456;1457; CHECK-FP16-LABEL: test_maxnum:1458; CHECK-FP16: // %bb.0:1459; CHECK-FP16-NEXT: fmaxnm h0, h0, h11460; CHECK-FP16-NEXT: ret1461;1462; CHECK-CVT-GI-LABEL: test_maxnum:1463; CHECK-CVT-GI: // %bb.0:1464; CHECK-CVT-GI-NEXT: fcvt s0, h01465; CHECK-CVT-GI-NEXT: fcvt s1, h11466; CHECK-CVT-GI-NEXT: fmaxnm s0, s0, s11467; CHECK-CVT-GI-NEXT: fcvt h0, s01468; CHECK-CVT-GI-NEXT: ret1469 %r = call half @llvm.maxnum.f16(half %a, half %b)1470 ret half %r1471}1472 1473define half @test_copysign(half %a, half %b) #0 {1474; CHECK-CVT-SD-LABEL: test_copysign:1475; CHECK-CVT-SD: // %bb.0:1476; CHECK-CVT-SD-NEXT: fcvt s1, h11477; CHECK-CVT-SD-NEXT: fcvt s0, h01478; CHECK-CVT-SD-NEXT: mvni v2.4s, #128, lsl #241479; CHECK-CVT-SD-NEXT: bif v0.16b, v1.16b, v2.16b1480; CHECK-CVT-SD-NEXT: fcvt h0, s01481; CHECK-CVT-SD-NEXT: ret1482;1483; CHECK-FP16-SD-LABEL: test_copysign:1484; CHECK-FP16-SD: // %bb.0:1485; CHECK-FP16-SD-NEXT: mvni v2.8h, #128, lsl #81486; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 def $q01487; CHECK-FP16-SD-NEXT: // kill: def $h1 killed $h1 def $q11488; CHECK-FP16-SD-NEXT: bif v0.16b, v1.16b, v2.16b1489; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q01490; CHECK-FP16-SD-NEXT: ret1491;1492; CHECK-CVT-GI-LABEL: test_copysign:1493; CHECK-CVT-GI: // %bb.0:1494; CHECK-CVT-GI-NEXT: mvni v2.4h, #128, lsl #81495; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $d01496; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $d11497; CHECK-CVT-GI-NEXT: bif v0.8b, v1.8b, v2.8b1498; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $d01499; CHECK-CVT-GI-NEXT: ret1500;1501; CHECK-FP16-GI-LABEL: test_copysign:1502; CHECK-FP16-GI: // %bb.0:1503; CHECK-FP16-GI-NEXT: mvni v2.4h, #128, lsl #81504; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $d01505; CHECK-FP16-GI-NEXT: // kill: def $h1 killed $h1 def $d11506; CHECK-FP16-GI-NEXT: bif v0.8b, v1.8b, v2.8b1507; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $d01508; CHECK-FP16-GI-NEXT: ret1509 %r = call half @llvm.copysign.f16(half %a, half %b)1510 ret half %r1511}1512 1513define half @test_copysign_f32(half %a, float %b) #0 {1514; CHECK-CVT-SD-LABEL: test_copysign_f32:1515; CHECK-CVT-SD: // %bb.0:1516; CHECK-CVT-SD-NEXT: fcvt s0, h01517; CHECK-CVT-SD-NEXT: mvni v2.4s, #128, lsl #241518; CHECK-CVT-SD-NEXT: // kill: def $s1 killed $s1 def $q11519; CHECK-CVT-SD-NEXT: bif v0.16b, v1.16b, v2.16b1520; CHECK-CVT-SD-NEXT: fcvt h0, s01521; CHECK-CVT-SD-NEXT: ret1522;1523; CHECK-FP16-SD-LABEL: test_copysign_f32:1524; CHECK-FP16-SD: // %bb.0:1525; CHECK-FP16-SD-NEXT: fcvt h1, s11526; CHECK-FP16-SD-NEXT: mvni v2.8h, #128, lsl #81527; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 def $q01528; CHECK-FP16-SD-NEXT: bif v0.16b, v1.16b, v2.16b1529; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q01530; CHECK-FP16-SD-NEXT: ret1531;1532; CHECK-CVT-GI-LABEL: test_copysign_f32:1533; CHECK-CVT-GI: // %bb.0:1534; CHECK-CVT-GI-NEXT: fcvt h1, s11535; CHECK-CVT-GI-NEXT: mvni v2.4h, #128, lsl #81536; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $d01537; CHECK-CVT-GI-NEXT: bif v0.8b, v1.8b, v2.8b1538; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $d01539; CHECK-CVT-GI-NEXT: ret1540;1541; CHECK-FP16-GI-LABEL: test_copysign_f32:1542; CHECK-FP16-GI: // %bb.0:1543; CHECK-FP16-GI-NEXT: fcvt h1, s11544; CHECK-FP16-GI-NEXT: mvni v2.4h, #128, lsl #81545; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $d01546; CHECK-FP16-GI-NEXT: bif v0.8b, v1.8b, v2.8b1547; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $d01548; CHECK-FP16-GI-NEXT: ret1549 %tb = fptrunc float %b to half1550 %r = call half @llvm.copysign.f16(half %a, half %tb)1551 ret half %r1552}1553 1554define half @test_copysign_f64(half %a, double %b) #0 {1555; CHECK-CVT-SD-LABEL: test_copysign_f64:1556; CHECK-CVT-SD: // %bb.0:1557; CHECK-CVT-SD-NEXT: fcvt s1, d11558; CHECK-CVT-SD-NEXT: fcvt s0, h01559; CHECK-CVT-SD-NEXT: mvni v2.4s, #128, lsl #241560; CHECK-CVT-SD-NEXT: bif v0.16b, v1.16b, v2.16b1561; CHECK-CVT-SD-NEXT: fcvt h0, s01562; CHECK-CVT-SD-NEXT: ret1563;1564; CHECK-FP16-SD-LABEL: test_copysign_f64:1565; CHECK-FP16-SD: // %bb.0:1566; CHECK-FP16-SD-NEXT: fcvt h1, d11567; CHECK-FP16-SD-NEXT: mvni v2.8h, #128, lsl #81568; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 def $q01569; CHECK-FP16-SD-NEXT: bif v0.16b, v1.16b, v2.16b1570; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q01571; CHECK-FP16-SD-NEXT: ret1572;1573; CHECK-CVT-GI-LABEL: test_copysign_f64:1574; CHECK-CVT-GI: // %bb.0:1575; CHECK-CVT-GI-NEXT: fcvt h1, d11576; CHECK-CVT-GI-NEXT: mvni v2.4h, #128, lsl #81577; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $d01578; CHECK-CVT-GI-NEXT: bif v0.8b, v1.8b, v2.8b1579; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $d01580; CHECK-CVT-GI-NEXT: ret1581;1582; CHECK-FP16-GI-LABEL: test_copysign_f64:1583; CHECK-FP16-GI: // %bb.0:1584; CHECK-FP16-GI-NEXT: fcvt h1, d11585; CHECK-FP16-GI-NEXT: mvni v2.4h, #128, lsl #81586; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $d01587; CHECK-FP16-GI-NEXT: bif v0.8b, v1.8b, v2.8b1588; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $d01589; CHECK-FP16-GI-NEXT: ret1590 %tb = fptrunc double %b to half1591 %r = call half @llvm.copysign.f16(half %a, half %tb)1592 ret half %r1593}1594 1595; Check that the FP promotion will use a truncating FP_ROUND, so we can fold1596; away the (fpext (fp_round <result>)) here.1597 1598define float @test_copysign_extended(half %a, half %b) #0 {1599; CHECK-CVT-SD-LABEL: test_copysign_extended:1600; CHECK-CVT-SD: // %bb.0:1601; CHECK-CVT-SD-NEXT: fcvt s1, h11602; CHECK-CVT-SD-NEXT: fcvt s0, h01603; CHECK-CVT-SD-NEXT: mvni v2.4s, #128, lsl #241604; CHECK-CVT-SD-NEXT: bif v0.16b, v1.16b, v2.16b1605; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q01606; CHECK-CVT-SD-NEXT: ret1607;1608; CHECK-FP16-SD-LABEL: test_copysign_extended:1609; CHECK-FP16-SD: // %bb.0:1610; CHECK-FP16-SD-NEXT: mvni v2.8h, #128, lsl #81611; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 def $q01612; CHECK-FP16-SD-NEXT: // kill: def $h1 killed $h1 def $q11613; CHECK-FP16-SD-NEXT: bif v0.16b, v1.16b, v2.16b1614; CHECK-FP16-SD-NEXT: fcvt s0, h01615; CHECK-FP16-SD-NEXT: ret1616;1617; CHECK-CVT-GI-LABEL: test_copysign_extended:1618; CHECK-CVT-GI: // %bb.0:1619; CHECK-CVT-GI-NEXT: mvni v2.4h, #128, lsl #81620; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $d01621; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $d11622; CHECK-CVT-GI-NEXT: bif v0.8b, v1.8b, v2.8b1623; CHECK-CVT-GI-NEXT: fcvt s0, h01624; CHECK-CVT-GI-NEXT: ret1625;1626; CHECK-FP16-GI-LABEL: test_copysign_extended:1627; CHECK-FP16-GI: // %bb.0:1628; CHECK-FP16-GI-NEXT: mvni v2.4h, #128, lsl #81629; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 def $d01630; CHECK-FP16-GI-NEXT: // kill: def $h1 killed $h1 def $d11631; CHECK-FP16-GI-NEXT: bif v0.8b, v1.8b, v2.8b1632; CHECK-FP16-GI-NEXT: fcvt s0, h01633; CHECK-FP16-GI-NEXT: ret1634 %r = call half @llvm.copysign.f16(half %a, half %b)1635 %xr = fpext half %r to float1636 ret float %xr1637}1638 1639define half @test_floor(half %a) #0 {1640; CHECK-CVT-LABEL: test_floor:1641; CHECK-CVT: // %bb.0:1642; CHECK-CVT-NEXT: fcvt s0, h01643; CHECK-CVT-NEXT: frintm s0, s01644; CHECK-CVT-NEXT: fcvt h0, s01645; CHECK-CVT-NEXT: ret1646;1647; CHECK-FP16-LABEL: test_floor:1648; CHECK-FP16: // %bb.0:1649; CHECK-FP16-NEXT: frintm h0, h01650; CHECK-FP16-NEXT: ret1651 %r = call half @llvm.floor.f16(half %a)1652 ret half %r1653}1654 1655define half @test_ceil(half %a) #0 {1656; CHECK-CVT-LABEL: test_ceil:1657; CHECK-CVT: // %bb.0:1658; CHECK-CVT-NEXT: fcvt s0, h01659; CHECK-CVT-NEXT: frintp s0, s01660; CHECK-CVT-NEXT: fcvt h0, s01661; CHECK-CVT-NEXT: ret1662;1663; CHECK-FP16-LABEL: test_ceil:1664; CHECK-FP16: // %bb.0:1665; CHECK-FP16-NEXT: frintp h0, h01666; CHECK-FP16-NEXT: ret1667 %r = call half @llvm.ceil.f16(half %a)1668 ret half %r1669}1670 1671define half @test_trunc(half %a) #0 {1672; CHECK-CVT-LABEL: test_trunc:1673; CHECK-CVT: // %bb.0:1674; CHECK-CVT-NEXT: fcvt s0, h01675; CHECK-CVT-NEXT: frintz s0, s01676; CHECK-CVT-NEXT: fcvt h0, s01677; CHECK-CVT-NEXT: ret1678;1679; CHECK-FP16-LABEL: test_trunc:1680; CHECK-FP16: // %bb.0:1681; CHECK-FP16-NEXT: frintz h0, h01682; CHECK-FP16-NEXT: ret1683 %r = call half @llvm.trunc.f16(half %a)1684 ret half %r1685}1686 1687define half @test_rint(half %a) #0 {1688; CHECK-CVT-LABEL: test_rint:1689; CHECK-CVT: // %bb.0:1690; CHECK-CVT-NEXT: fcvt s0, h01691; CHECK-CVT-NEXT: frintx s0, s01692; CHECK-CVT-NEXT: fcvt h0, s01693; CHECK-CVT-NEXT: ret1694;1695; CHECK-FP16-LABEL: test_rint:1696; CHECK-FP16: // %bb.0:1697; CHECK-FP16-NEXT: frintx h0, h01698; CHECK-FP16-NEXT: ret1699 %r = call half @llvm.rint.f16(half %a)1700 ret half %r1701}1702 1703define half @test_nearbyint(half %a) #0 {1704; CHECK-CVT-LABEL: test_nearbyint:1705; CHECK-CVT: // %bb.0:1706; CHECK-CVT-NEXT: fcvt s0, h01707; CHECK-CVT-NEXT: frinti s0, s01708; CHECK-CVT-NEXT: fcvt h0, s01709; CHECK-CVT-NEXT: ret1710;1711; CHECK-FP16-LABEL: test_nearbyint:1712; CHECK-FP16: // %bb.0:1713; CHECK-FP16-NEXT: frinti h0, h01714; CHECK-FP16-NEXT: ret1715 %r = call half @llvm.nearbyint.f16(half %a)1716 ret half %r1717}1718 1719define half @test_round(half %a) #0 {1720; CHECK-CVT-LABEL: test_round:1721; CHECK-CVT: // %bb.0:1722; CHECK-CVT-NEXT: fcvt s0, h01723; CHECK-CVT-NEXT: frinta s0, s01724; CHECK-CVT-NEXT: fcvt h0, s01725; CHECK-CVT-NEXT: ret1726;1727; CHECK-FP16-LABEL: test_round:1728; CHECK-FP16: // %bb.0:1729; CHECK-FP16-NEXT: frinta h0, h01730; CHECK-FP16-NEXT: ret1731 %r = call half @llvm.round.f16(half %a)1732 ret half %r1733}1734 1735define half @test_roundeven(half %a) #0 {1736; CHECK-CVT-LABEL: test_roundeven:1737; CHECK-CVT: // %bb.0:1738; CHECK-CVT-NEXT: fcvt s0, h01739; CHECK-CVT-NEXT: frintn s0, s01740; CHECK-CVT-NEXT: fcvt h0, s01741; CHECK-CVT-NEXT: ret1742;1743; CHECK-FP16-LABEL: test_roundeven:1744; CHECK-FP16: // %bb.0:1745; CHECK-FP16-NEXT: frintn h0, h01746; CHECK-FP16-NEXT: ret1747 %r = call half @llvm.roundeven.f16(half %a)1748 ret half %r1749}1750 1751define half @test_fmuladd(half %a, half %b, half %c) #0 {1752; CHECK-CVT-SD-LABEL: test_fmuladd:1753; CHECK-CVT-SD: // %bb.0:1754; CHECK-CVT-SD-NEXT: fcvt s1, h11755; CHECK-CVT-SD-NEXT: fcvt s0, h01756; CHECK-CVT-SD-NEXT: fmul s0, s0, s11757; CHECK-CVT-SD-NEXT: fcvt s1, h21758; CHECK-CVT-SD-NEXT: fcvt h0, s01759; CHECK-CVT-SD-NEXT: fcvt s0, h01760; CHECK-CVT-SD-NEXT: fadd s0, s0, s11761; CHECK-CVT-SD-NEXT: fcvt h0, s01762; CHECK-CVT-SD-NEXT: ret1763;1764; CHECK-FP16-LABEL: test_fmuladd:1765; CHECK-FP16: // %bb.0:1766; CHECK-FP16-NEXT: fmadd h0, h0, h1, h21767; CHECK-FP16-NEXT: ret1768;1769; CHECK-CVT-GI-LABEL: test_fmuladd:1770; CHECK-CVT-GI: // %bb.0:1771; CHECK-CVT-GI-NEXT: fcvt s0, h01772; CHECK-CVT-GI-NEXT: fcvt s1, h11773; CHECK-CVT-GI-NEXT: fmul s0, s0, s11774; CHECK-CVT-GI-NEXT: fcvt s1, h21775; CHECK-CVT-GI-NEXT: fcvt h0, s01776; CHECK-CVT-GI-NEXT: fcvt s0, h01777; CHECK-CVT-GI-NEXT: fadd s0, s0, s11778; CHECK-CVT-GI-NEXT: fcvt h0, s01779; CHECK-CVT-GI-NEXT: ret1780 %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)1781 ret half %r1782}1783 1784attributes #0 = { nounwind }1785