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1# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass aarch64-falkor-hwpf-fix-late -o - %s | FileCheck %s2---3# Verify that the tag collision between the loads is resolved for various load opcodes.4 5# CHECK-LABEL: name: hwpf16# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 07# CHECK: LDRWui $[[BASE]], 08# CHECK: LDRWui $x1, 19name: hwpf110tracksRegLiveness: true11body: |12 bb.0:13 liveins: $w0, $x114 15 $w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load (s32))16 $w2 = LDRWui $x1, 117 18 $w0 = SUBWri $w0, 1, 019 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv20 Bcc 9, %bb.0, implicit $nzcv21 22 bb.1:23 RET_ReallyLR24...25---26# CHECK-LABEL: name: hwpf227# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 028# CHECK: LD1i64 $q2, 0, $[[BASE]]29# CHECK: LDRWui $x1, 030name: hwpf231tracksRegLiveness: true32body: |33 bb.0:34 liveins: $w0, $x1, $q235 36 $q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load (s32))37 $w2 = LDRWui $x1, 038 39 $w0 = SUBWri $w0, 1, 040 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv41 Bcc 9, %bb.0, implicit $nzcv42 43 bb.1:44 RET_ReallyLR45...46---47# CHECK-LABEL: name: hwpf348# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 049# CHECK: LD1i8 $q2, 0, $[[BASE]]50# CHECK: LDRWui $x1, 051name: hwpf352tracksRegLiveness: true53body: |54 bb.0:55 liveins: $w0, $x1, $q256 57 $q2 = LD1i8 $q2, 0, $x1 :: ("aarch64-strided-access" load (s32))58 $w0 = LDRWui $x1, 059 60 $w0 = SUBWri $w0, 1, 061 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv62 Bcc 9, %bb.0, implicit $nzcv63 64 bb.1:65 RET_ReallyLR66...67---68# CHECK-LABEL: name: hwpf469# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 070# CHECK: LD1Onev1d $[[BASE]]71# CHECK: LDRWui $x1, 072name: hwpf473tracksRegLiveness: true74body: |75 bb.0:76 liveins: $w0, $x177 78 $d2 = LD1Onev1d $x1 :: ("aarch64-strided-access" load (s32))79 $w2 = LDRWui $x1, 080 81 $w0 = SUBWri $w0, 1, 082 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv83 Bcc 9, %bb.0, implicit $nzcv84 85 bb.1:86 RET_ReallyLR87...88---89# CHECK-LABEL: name: hwpf590# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 091# CHECK: LD1Twov1d $[[BASE]]92# CHECK: LDRWui $x1, 093name: hwpf594tracksRegLiveness: true95body: |96 bb.0:97 liveins: $w0, $x198 99 $d2_d3 = LD1Twov1d $x1 :: ("aarch64-strided-access" load (s32))100 $w0 = LDRWui $x1, 0101 102 $w0 = SUBWri $w0, 1, 0103 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv104 Bcc 9, %bb.0, implicit $nzcv105 106 bb.1:107 RET_ReallyLR108...109---110# CHECK-LABEL: name: hwpf6111# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0112# CHECK: LDPQi $[[BASE]]113# CHECK: LDRWui $x1, 3114name: hwpf6115tracksRegLiveness: true116body: |117 bb.0:118 liveins: $w0, $x1119 120 $q2, $q3 = LDPQi $x1, 3 :: ("aarch64-strided-access" load (s32))121 $w0 = LDRWui $x1, 3122 123 $w0 = SUBWri $w0, 1, 0124 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv125 Bcc 9, %bb.0, implicit $nzcv126 127 bb.1:128 RET_ReallyLR129...130---131# CHECK-LABEL: name: hwpf7132# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0133# CHECK: LDPXi $[[BASE]]134# CHECK: LDRWui $x1, 2135name: hwpf7136tracksRegLiveness: true137body: |138 bb.0:139 liveins: $w0, $x1140 141 $x2, $x3 = LDPXi $x1, 3 :: ("aarch64-strided-access" load (s32))142 $w2 = LDRWui $x1, 2143 144 $w0 = SUBWri $w0, 1, 0145 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv146 Bcc 9, %bb.0, implicit $nzcv147 148 bb.1:149 RET_ReallyLR150...151---152# Verify that the tag collision between the loads is resolved and written back153# for post increment addressing for various load opcodes.154 155# CHECK-LABEL: name: hwpfinc1156# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0157# CHECK: LDRWpost $[[BASE]], 0158# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0159# CHECK: LDRWui $x1, 1160name: hwpfinc1161tracksRegLiveness: true162body: |163 bb.0:164 liveins: $w0, $x1165 166 $x1, $w2 = LDRWpost $x1, 0 :: ("aarch64-strided-access" load (s32))167 $w2 = LDRWui $x1, 1168 169 $w0 = SUBWri $w0, 1, 0170 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv171 Bcc 9, %bb.0, implicit $nzcv172 173 bb.1:174 RET_ReallyLR175...176---177# CHECK-LABEL: name: hwpfinc2178# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0179# CHECK: LD1i64_POST $q2, 0, $[[BASE]]180# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0181# CHECK: LDRWui $x1, 1182name: hwpfinc2183tracksRegLiveness: true184body: |185 bb.0:186 liveins: $w0, $x1, $q2187 188 $x1, $q2 = LD1i64_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load (s32))189 $w2 = LDRWui $x1, 132190 191 $w0 = SUBWri $w0, 1, 0192 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv193 Bcc 9, %bb.0, implicit $nzcv194 195 bb.1:196 RET_ReallyLR197...198---199# CHECK-LABEL: name: hwpfinc3200# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0201# CHECK: LD1i8_POST $q2, 0, $[[BASE]]202# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0203# CHECK: LDRWui $x1, 132204name: hwpfinc3205tracksRegLiveness: true206body: |207 bb.0:208 liveins: $w0, $x1, $q2209 210 $x1, $q2 = LD1i8_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load (s32))211 $w0 = LDRWui $x1, 132212 213 $w0 = SUBWri $w0, 1, 0214 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv215 Bcc 9, %bb.0, implicit $nzcv216 217 bb.1:218 RET_ReallyLR219...220---221# CHECK-LABEL: name: hwpfinc4222# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0223# CHECK: LD1Rv1d_POST $[[BASE]]224# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0225# CHECK: LDRWui $x1, 252226name: hwpfinc4227tracksRegLiveness: true228body: |229 bb.0:230 liveins: $w0, $x1, $q2231 232 $x1, $d2 = LD1Rv1d_POST $x1, $xzr :: ("aarch64-strided-access" load (s32))233 $w2 = LDRWui $x1, 252234 235 $w0 = SUBWri $w0, 1, 0236 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv237 Bcc 9, %bb.0, implicit $nzcv238 239 bb.1:240 RET_ReallyLR241...242---243# CHECK-LABEL: name: hwpfinc5244# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0245# CHECK: LD3Threev2s_POST $[[BASE]]246# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0247# CHECK: LDRWroX $x17, $x0248name: hwpfinc5249tracksRegLiveness: true250body: |251 bb.0:252 liveins: $w0, $x1, $x17, $q2253 254 $x1, $d2_d3_d4 = LD3Threev2s_POST $x1, $x0 :: ("aarch64-strided-access" load (s32))255 $w0 = LDRWroX $x17, $x0, 0, 0256 257 $w0 = SUBWri $w0, 1, 0258 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv259 Bcc 9, %bb.0, implicit $nzcv260 261 bb.1:262 RET_ReallyLR263...264---265# CHECK-LABEL: name: hwpfinc6266# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0267# CHECK: LDPDpost $[[BASE]]268# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0269# CHECK: LDRWui $x17, 2270name: hwpfinc6271tracksRegLiveness: true272body: |273 bb.0:274 liveins: $w0, $x1, $x17, $q2275 276 $x1, $d2, $d3 = LDPDpost $x1, 3 :: ("aarch64-strided-access" load (s32))277 $w16 = LDRWui $x17, 2278 279 $w0 = SUBWri $w0, 1, 0280 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv281 Bcc 9, %bb.0, implicit $nzcv282 283 bb.1:284 RET_ReallyLR285...286---287# CHECK-LABEL: name: hwpfinc7288# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0289# CHECK: LDPXpost $[[BASE]]290# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0291# CHECK: LDRWui $x17, 2292name: hwpfinc7293tracksRegLiveness: true294body: |295 bb.0:296 liveins: $w0, $x1, $x17, $q2297 298 $x1, $x2, $x3 = LDPXpost $x1, 3 :: ("aarch64-strided-access" load (s32))299 $w18 = LDRWui $x17, 2300 301 $w0 = SUBWri $w0, 1, 0302 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv303 Bcc 9, %bb.0, implicit $nzcv304 305 bb.1:306 RET_ReallyLR307...308---309# Check that we handle case of strided load with no HW prefetcher tag correctly.310 311# CHECK-LABEL: name: hwpf_notagbug312# CHECK-NOT: ORRXrs $xzr313# CHECK: LDARW $x1314# CHECK-NOT: ORRXrs $xzr315# CHECK: LDRWui $x1316name: hwpf_notagbug317tracksRegLiveness: true318body: |319 bb.0:320 liveins: $w0, $x1, $x17321 322 $w1 = LDARW $x1 :: ("aarch64-strided-access" load (s32))323 $w1 = LDRWui $x1, 0 :: ("aarch64-strided-access" load (s32))324 $w17 = LDRWui $x17, 0 :: ("aarch64-strided-access" load (s32))325 326 $w0 = SUBWri $w0, 1, 0327 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv328 Bcc 9, %bb.0, implicit $nzcv329 330 bb.1:331 RET_ReallyLR332...333---334# Check that we treat sp based loads as non-prefetching.335 336# CHECK-LABEL: name: hwpf_spbase337# CHECK-NOT: ORRXrs $xzr338# CHECK: LDRWui $x15339# CHECK: LDRWui $sp340name: hwpf_spbase341tracksRegLiveness: true342body: |343 bb.0:344 liveins: $w0, $x15345 346 $w1 = LDRWui $x15, 0 :: ("aarch64-strided-access" load (s32))347 $w17 = LDRWui $sp, 0348 349 $w0 = SUBWri $w0, 1, 0350 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv351 Bcc 9, %bb.0, implicit $nzcv352 353 bb.1:354 RET_ReallyLR355...356---357# Check that non-base registers are considered live when finding a358# scratch register by making sure we don't use $x2 for the scratch359# register for the inserted ORRXrs.360# CHECK-LABEL: name: hwpf_offreg361# CHECK: $x3 = ORRXrs $xzr, $x1, 0362# CHECK: $w10 = LDRWroX $x3, $x2, 0, 0363name: hwpf_offreg364tracksRegLiveness: true365body: |366 bb.0:367 liveins: $w0, $x1, $x2, $x17, $x18368 369 $w10 = LDRWroX $x1, $x2, 0, 0 :: ("aarch64-strided-access" load (s32))370 371 $x2 = ORRXrs $xzr, $x10, 0372 $w26 = LDRWroX $x1, $x2, 0, 0373 374 $w0 = SUBWri $w0, 1, 0375 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv376 Bcc 9, %bb.0, implicit $nzcv377 378 bb.1:379 RET_ReallyLR380...381