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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s2 3; Test invalid shift values. This will fall-back to SDAG.4; AND5define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {6; CHECK-LABEL: and_rs_i87; CHECK: and [[REG:w[0-9]+]], w0, w88; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff9 %1 = shl i8 %b, 810 %2 = and i8 %a, %111 ret i8 %212}13 14define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {15; CHECK-LABEL: and_rs_i1616; CHECK: and [[REG:w[0-9]+]], w0, w817; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff18 %1 = shl i16 %b, 1619 %2 = and i16 %a, %120 ret i16 %221}22 23define i32 @and_rs_i32(i32 %a, i32 %b) {24; CHECK-LABEL: and_rs_i3225; CHECK: and w0, w0, w826 %1 = shl i32 %b, 3227 %2 = and i32 %a, %128 ret i32 %229}30 31define i64 @and_rs_i64(i64 %a, i64 %b) {32; CHECK-LABEL: and_rs_i6433; CHECK: and x0, x0, x834 %1 = shl i64 %b, 6435 %2 = and i64 %a, %136 ret i64 %237}38 39; OR40define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {41; CHECK-LABEL: or_rs_i842; CHECK: orr [[REG:w[0-9]+]], w0, w843; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff44 %1 = shl i8 %b, 845 %2 = or i8 %a, %146 ret i8 %247}48 49define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {50; CHECK-LABEL: or_rs_i1651; CHECK: orr [[REG:w[0-9]+]], w0, w852; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff53 %1 = shl i16 %b, 1654 %2 = or i16 %a, %155 ret i16 %256}57 58define i32 @or_rs_i32(i32 %a, i32 %b) {59; CHECK-LABEL: or_rs_i3260; CHECK: orr w0, w0, w861 %1 = shl i32 %b, 3262 %2 = or i32 %a, %163 ret i32 %264}65 66define i64 @or_rs_i64(i64 %a, i64 %b) {67; CHECK-LABEL: or_rs_i6468; CHECK: orr x0, x0, x869 %1 = shl i64 %b, 6470 %2 = or i64 %a, %171 ret i64 %272}73 74; XOR75define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {76; CHECK-LABEL: xor_rs_i877; CHECK: eor [[REG:w[0-9]+]], w0, w878; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff79 %1 = shl i8 %b, 880 %2 = xor i8 %a, %181 ret i8 %282}83 84define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {85; CHECK-LABEL: xor_rs_i1686; CHECK: eor [[REG:w[0-9]+]], w0, w887; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff88 %1 = shl i16 %b, 1689 %2 = xor i16 %a, %190 ret i16 %291}92 93define i32 @xor_rs_i32(i32 %a, i32 %b) {94; CHECK-LABEL: xor_rs_i3295; CHECK: eor w0, w0, w896 %1 = shl i32 %b, 3297 %2 = xor i32 %a, %198 ret i32 %299}100 101define i64 @xor_rs_i64(i64 %a, i64 %b) {102; CHECK-LABEL: xor_rs_i64103; CHECK: eor x0, x0, x8104 %1 = shl i64 %b, 64105 %2 = xor i64 %a, %1106 ret i64 %2107}108 109;ADD110define i32 @add_rs_i32(i32 %a, i32 %b) {111; CHECK-LABEL: add_rs_i32112; CHECK: add w0, w0, w8113 %1 = shl i32 %b, 32114 %2 = add i32 %a, %1115 ret i32 %2116}117 118define i64 @add_rs_i64(i64 %a, i64 %b) {119; CHECK-LABEL: add_rs_i64120; CHECK: add x0, x0, x8121 %1 = shl i64 %b, 64122 %2 = add i64 %a, %1123 ret i64 %2124}125 126