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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-enable-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s2 3;4; Test folding of the sign-/zero-extend into the load instruction.5;6 7; Unscaled8define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {9; CHECK-LABEL: load_unscaled_zext_i8_to_i3210; CHECK: ldurb w0, [x0, #-8]11; CHECK-NOT: uxtb12 %1 = sub i64 %a, 813 %2 = inttoptr i64 %1 to ptr14 %3 = load i8, ptr %215 br label %bb216 17bb2:18 %4 = zext i8 %3 to i3219 ret i32 %420}21 22define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {23; CHECK-LABEL: load_unscaled_zext_i16_to_i3224; CHECK: ldurh w0, [x0, #-8]25; CHECK-NOT: uxth26 %1 = sub i64 %a, 827 %2 = inttoptr i64 %1 to ptr28 %3 = load i16, ptr %229 br label %bb230 31bb2:32 %4 = zext i16 %3 to i3233 ret i32 %434}35 36define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {37; CHECK-LABEL: load_unscaled_zext_i8_to_i6438; CHECK: ldurb w0, [x0, #-8]39; CHECK-NOT: uxtb40 %1 = sub i64 %a, 841 %2 = inttoptr i64 %1 to ptr42 %3 = load i8, ptr %243 br label %bb244 45bb2:46 %4 = zext i8 %3 to i6447 ret i64 %448}49 50define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {51; CHECK-LABEL: load_unscaled_zext_i16_to_i6452; CHECK: ldurh w0, [x0, #-8]53; CHECK-NOT: uxth54 %1 = sub i64 %a, 855 %2 = inttoptr i64 %1 to ptr56 %3 = load i16, ptr %257 br label %bb258 59bb2:60 %4 = zext i16 %3 to i6461 ret i64 %462}63 64define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {65; CHECK-LABEL: load_unscaled_zext_i32_to_i6466; CHECK: ldur w0, [x0, #-8]67; CHECK-NOT: uxtw68 %1 = sub i64 %a, 869 %2 = inttoptr i64 %1 to ptr70 %3 = load i32, ptr %271 br label %bb272 73bb2:74 %4 = zext i32 %3 to i6475 ret i64 %476}77 78define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {79; CHECK-LABEL: load_unscaled_sext_i8_to_i3280; CHECK: ldursb w0, [x0, #-8]81; CHECK-NOT: sxtb82 %1 = sub i64 %a, 883 %2 = inttoptr i64 %1 to ptr84 %3 = load i8, ptr %285 br label %bb286 87bb2:88 %4 = sext i8 %3 to i3289 ret i32 %490}91 92define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {93; CHECK-LABEL: load_unscaled_sext_i16_to_i3294; CHECK: ldursh w0, [x0, #-8]95; CHECK-NOT: sxth96 %1 = sub i64 %a, 897 %2 = inttoptr i64 %1 to ptr98 %3 = load i16, ptr %299 br label %bb2100 101bb2:102 %4 = sext i16 %3 to i32103 ret i32 %4104}105 106define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {107; CHECK-LABEL: load_unscaled_sext_i8_to_i64108; CHECK: ldursb x0, [x0, #-8]109; CHECK-NOT: sxtb110 %1 = sub i64 %a, 8111 %2 = inttoptr i64 %1 to ptr112 %3 = load i8, ptr %2113 br label %bb2114 115bb2:116 %4 = sext i8 %3 to i64117 ret i64 %4118}119 120define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {121; CHECK-LABEL: load_unscaled_sext_i16_to_i64122; CHECK: ldursh x0, [x0, #-8]123; CHECK-NOT: sxth124 %1 = sub i64 %a, 8125 %2 = inttoptr i64 %1 to ptr126 %3 = load i16, ptr %2127 br label %bb2128 129bb2:130 %4 = sext i16 %3 to i64131 ret i64 %4132}133 134define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {135; CHECK-LABEL: load_unscaled_sext_i32_to_i64136; CHECK: ldursw x0, [x0, #-8]137; CHECK-NOT: sxtw138 %1 = sub i64 %a, 8139 %2 = inttoptr i64 %1 to ptr140 %3 = load i32, ptr %2141 br label %bb2142 143bb2:144 %4 = sext i32 %3 to i64145 ret i64 %4146}147 148; Register149define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {150; CHECK-LABEL: load_register_zext_i8_to_i32151; CHECK: ldrb w0, [x0, x1]152; CHECK-NOT: uxtb153 %1 = add i64 %a, %b154 %2 = inttoptr i64 %1 to ptr155 %3 = load i8, ptr %2156 br label %bb2157 158bb2:159 %4 = zext i8 %3 to i32160 ret i32 %4161}162 163define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {164; CHECK-LABEL: load_register_zext_i16_to_i32165; CHECK: ldrh w0, [x0, x1]166; CHECK-NOT: uxth167 %1 = add i64 %a, %b168 %2 = inttoptr i64 %1 to ptr169 %3 = load i16, ptr %2170 br label %bb2171 172bb2:173 %4 = zext i16 %3 to i32174 ret i32 %4175}176 177define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {178; CHECK-LABEL: load_register_zext_i8_to_i64179; CHECK: ldrb w0, [x0, x1]180; CHECK-NOT: uxtb181 %1 = add i64 %a, %b182 %2 = inttoptr i64 %1 to ptr183 %3 = load i8, ptr %2184 br label %bb2185 186bb2:187 %4 = zext i8 %3 to i64188 ret i64 %4189}190 191define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {192; CHECK-LABEL: load_register_zext_i16_to_i64193; CHECK: ldrh w0, [x0, x1]194; CHECK-NOT: uxth195 %1 = add i64 %a, %b196 %2 = inttoptr i64 %1 to ptr197 %3 = load i16, ptr %2198 br label %bb2199 200bb2:201 %4 = zext i16 %3 to i64202 ret i64 %4203}204 205define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {206; CHECK-LABEL: load_register_zext_i32_to_i64207; CHECK: ldr w0, [x0, x1]208; CHECK-NOT: uxtw209 %1 = add i64 %a, %b210 %2 = inttoptr i64 %1 to ptr211 %3 = load i32, ptr %2212 br label %bb2213 214bb2:215 %4 = zext i32 %3 to i64216 ret i64 %4217}218 219define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {220; CHECK-LABEL: load_register_sext_i8_to_i32221; CHECK: ldrsb w0, [x0, x1]222; CHECK-NOT: sxtb223 %1 = add i64 %a, %b224 %2 = inttoptr i64 %1 to ptr225 %3 = load i8, ptr %2226 br label %bb2227 228bb2:229 %4 = sext i8 %3 to i32230 ret i32 %4231}232 233define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {234; CHECK-LABEL: load_register_sext_i16_to_i32235; CHECK: ldrsh w0, [x0, x1]236; CHECK-NOT: sxth237 %1 = add i64 %a, %b238 %2 = inttoptr i64 %1 to ptr239 %3 = load i16, ptr %2240 br label %bb2241 242bb2:243 %4 = sext i16 %3 to i32244 ret i32 %4245}246 247define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {248; CHECK-LABEL: load_register_sext_i8_to_i64249; CHECK: ldrsb x0, [x0, x1]250; CHECK-NOT: sxtb251 %1 = add i64 %a, %b252 %2 = inttoptr i64 %1 to ptr253 %3 = load i8, ptr %2254 br label %bb2255 256bb2:257 %4 = sext i8 %3 to i64258 ret i64 %4259}260 261define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {262; CHECK-LABEL: load_register_sext_i16_to_i64263; CHECK: ldrsh x0, [x0, x1]264; CHECK-NOT: sxth265 %1 = add i64 %a, %b266 %2 = inttoptr i64 %1 to ptr267 %3 = load i16, ptr %2268 br label %bb2269 270bb2:271 %4 = sext i16 %3 to i64272 ret i64 %4273}274 275define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {276; CHECK-LABEL: load_register_sext_i32_to_i64277; CHECK: ldrsw x0, [x0, x1]278; CHECK-NOT: sxtw279 %1 = add i64 %a, %b280 %2 = inttoptr i64 %1 to ptr281 %3 = load i32, ptr %2282 br label %bb2283 284bb2:285 %4 = sext i32 %3 to i64286 ret i64 %4287}288 289; Extend290define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {291; CHECK-LABEL: load_extend_zext_i8_to_i32292; CHECK: ldrb w0, [x0, w1, sxtw]293; CHECK-NOT: uxtb294 %1 = sext i32 %b to i64295 %2 = add i64 %a, %1296 %3 = inttoptr i64 %2 to ptr297 %4 = load i8, ptr %3298 br label %bb2299 300bb2:301 %5 = zext i8 %4 to i32302 ret i32 %5303}304 305define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {306; CHECK-LABEL: load_extend_zext_i16_to_i32307; CHECK: ldrh w0, [x0, w1, sxtw]308; CHECK-NOT: uxth309 %1 = sext i32 %b to i64310 %2 = add i64 %a, %1311 %3 = inttoptr i64 %2 to ptr312 %4 = load i16, ptr %3313 br label %bb2314 315bb2:316 %5 = zext i16 %4 to i32317 ret i32 %5318}319 320define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {321; CHECK-LABEL: load_extend_zext_i8_to_i64322; CHECK: ldrb w0, [x0, w1, sxtw]323; CHECK-NOT: uxtb324 %1 = sext i32 %b to i64325 %2 = add i64 %a, %1326 %3 = inttoptr i64 %2 to ptr327 %4 = load i8, ptr %3328 br label %bb2329 330bb2:331 %5 = zext i8 %4 to i64332 ret i64 %5333}334 335define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {336; CHECK-LABEL: load_extend_zext_i16_to_i64337; CHECK: ldrh w0, [x0, w1, sxtw]338; CHECK-NOT: uxth339 %1 = sext i32 %b to i64340 %2 = add i64 %a, %1341 %3 = inttoptr i64 %2 to ptr342 %4 = load i16, ptr %3343 br label %bb2344 345bb2:346 %5 = zext i16 %4 to i64347 ret i64 %5348}349 350define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {351; CHECK-LABEL: load_extend_zext_i32_to_i64352; CHECK: ldr w0, [x0, w1, sxtw]353; CHECK-NOT: uxtw354 %1 = sext i32 %b to i64355 %2 = add i64 %a, %1356 %3 = inttoptr i64 %2 to ptr357 %4 = load i32, ptr %3358 br label %bb2359 360bb2:361 %5 = zext i32 %4 to i64362 ret i64 %5363}364 365define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {366; CHECK-LABEL: load_extend_sext_i8_to_i32367; CHECK: ldrsb w0, [x0, w1, sxtw]368; CHECK-NOT: sxtb369 %1 = sext i32 %b to i64370 %2 = add i64 %a, %1371 %3 = inttoptr i64 %2 to ptr372 %4 = load i8, ptr %3373 br label %bb2374 375bb2:376 %5 = sext i8 %4 to i32377 ret i32 %5378}379 380define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {381; CHECK-LABEL: load_extend_sext_i16_to_i32382; CHECK: ldrsh w0, [x0, w1, sxtw]383; CHECK-NOT: sxth384 %1 = sext i32 %b to i64385 %2 = add i64 %a, %1386 %3 = inttoptr i64 %2 to ptr387 %4 = load i16, ptr %3388 br label %bb2389 390bb2:391 %5 = sext i16 %4 to i32392 ret i32 %5393}394 395define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {396; CHECK-LABEL: load_extend_sext_i8_to_i64397; CHECK: ldrsb x0, [x0, w1, sxtw]398; CHECK-NOT: sxtb399 %1 = sext i32 %b to i64400 %2 = add i64 %a, %1401 %3 = inttoptr i64 %2 to ptr402 %4 = load i8, ptr %3403 br label %bb2404 405bb2:406 %5 = sext i8 %4 to i64407 ret i64 %5408}409 410define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {411; CHECK-LABEL: load_extend_sext_i16_to_i64412; CHECK: ldrsh x0, [x0, w1, sxtw]413; CHECK-NOT: sxth414 %1 = sext i32 %b to i64415 %2 = add i64 %a, %1416 %3 = inttoptr i64 %2 to ptr417 %4 = load i16, ptr %3418 br label %bb2419 420bb2:421 %5 = sext i16 %4 to i64422 ret i64 %5423}424 425define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {426; CHECK-LABEL: load_extend_sext_i32_to_i64427; CHECK: ldrsw x0, [x0, w1, sxtw]428; CHECK-NOT: sxtw429 %1 = sext i32 %b to i64430 %2 = add i64 %a, %1431 %3 = inttoptr i64 %2 to ptr432 %4 = load i32, ptr %3433 br label %bb2434 435bb2:436 %5 = sext i32 %4 to i64437 ret i64 %5438}439 440