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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s2 3;4; Test folding of the sign-/zero-extend into the load instruction.5;6 7; Unscaled8define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {9; CHECK-LABEL: load_unscaled_zext_i8_to_i3210; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]11; CHECK: uxtb w0, [[REG]]12 %1 = sub i64 %a, 813 %2 = inttoptr i64 %1 to ptr addrspace(256)14 %3 = load i8, ptr addrspace(256) %215 %4 = zext i8 %3 to i3216 ret i32 %417}18 19define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {20; CHECK-LABEL: load_unscaled_zext_i16_to_i3221; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]22; CHECK: uxth w0, [[REG]]23 %1 = sub i64 %a, 824 %2 = inttoptr i64 %1 to ptr addrspace(256)25 %3 = load i16, ptr addrspace(256) %226 %4 = zext i16 %3 to i3227 ret i32 %428}29 30define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {31; CHECK-LABEL: load_unscaled_zext_i8_to_i6432; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8]33; CHECK: ubfx x0, x[[REG]], #0, #834 %1 = sub i64 %a, 835 %2 = inttoptr i64 %1 to ptr addrspace(256)36 %3 = load i8, ptr addrspace(256) %237 %4 = zext i8 %3 to i6438 ret i64 %439}40 41define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {42; CHECK-LABEL: load_unscaled_zext_i16_to_i6443; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8]44; CHECK: ubfx x0, x[[REG]], #0, #1645 %1 = sub i64 %a, 846 %2 = inttoptr i64 %1 to ptr addrspace(256)47 %3 = load i16, ptr addrspace(256) %248 %4 = zext i16 %3 to i6449 ret i64 %450}51 52define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {53; CHECK-LABEL: load_unscaled_zext_i32_to_i6454; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8]55; CHECK: lsr w0, w[[REG]], #056 %1 = sub i64 %a, 857 %2 = inttoptr i64 %1 to ptr addrspace(256)58 %3 = load i32, ptr addrspace(256) %259 %4 = zext i32 %3 to i6460 ret i64 %461}62 63define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {64; CHECK-LABEL: load_unscaled_sext_i8_to_i3265; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]66; CHECK: sxtb w0, [[REG]]67 %1 = sub i64 %a, 868 %2 = inttoptr i64 %1 to ptr addrspace(256)69 %3 = load i8, ptr addrspace(256) %270 %4 = sext i8 %3 to i3271 ret i32 %472}73 74define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {75; CHECK-LABEL: load_unscaled_sext_i16_to_i3276; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]77; CHECK: sxth w0, [[REG]]78 %1 = sub i64 %a, 879 %2 = inttoptr i64 %1 to ptr addrspace(256)80 %3 = load i16, ptr addrspace(256) %281 %4 = sext i16 %3 to i3282 ret i32 %483}84 85define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {86; CHECK-LABEL: load_unscaled_sext_i8_to_i6487; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]88; CHECK: sxtb x0, [[REG]]89 %1 = sub i64 %a, 890 %2 = inttoptr i64 %1 to ptr addrspace(256)91 %3 = load i8, ptr addrspace(256) %292 %4 = sext i8 %3 to i6493 ret i64 %494}95 96define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {97; CHECK-LABEL: load_unscaled_sext_i16_to_i6498; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]99; CHECK: sxth x0, [[REG]]100 %1 = sub i64 %a, 8101 %2 = inttoptr i64 %1 to ptr addrspace(256)102 %3 = load i16, ptr addrspace(256) %2103 %4 = sext i16 %3 to i64104 ret i64 %4105}106 107define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {108; CHECK-LABEL: load_unscaled_sext_i32_to_i64109; CHECK: ldur [[REG:w[0-9]+]], [x0, #-8]110; CHECK: sxtw x0, [[REG]]111 %1 = sub i64 %a, 8112 %2 = inttoptr i64 %1 to ptr addrspace(256)113 %3 = load i32, ptr addrspace(256) %2114 %4 = sext i32 %3 to i64115 ret i64 %4116}117 118