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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s3 4; AND5define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {6; CHECK-LABEL: and_rr_i17; CHECK: and [[REG:w[0-9]+]], w0, w18 %1 = and i1 %a, %b9 ret i1 %110}11 12define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {13; CHECK-LABEL: and_rr_i814; CHECK: and [[REG:w[0-9]+]], w0, w115; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff16 %1 = and i8 %a, %b17 ret i8 %118}19 20define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {21; CHECK-LABEL: and_rr_i1622; CHECK: and [[REG:w[0-9]+]], w0, w123; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff24 %1 = and i16 %a, %b25 ret i16 %126}27 28define i32 @and_rr_i32(i32 %a, i32 %b) {29; CHECK-LABEL: and_rr_i3230; CHECK: and w0, w0, w131 %1 = and i32 %a, %b32 ret i32 %133}34 35define i64 @and_rr_i64(i64 %a, i64 %b) {36; CHECK-LABEL: and_rr_i6437; CHECK: and x0, x0, x138 %1 = and i64 %a, %b39 ret i64 %140}41 42define zeroext i1 @and_ri_i1(i1 signext %a) {43; CHECK-LABEL: and_ri_i144; CHECK: and {{w[0-9]+}}, w0, #0x145 %1 = and i1 %a, 146 ret i1 %147}48 49define zeroext i8 @and_ri_i8(i8 signext %a) {50; CHECK-LABEL: and_ri_i851; CHECK: and {{w[0-9]+}}, w0, #0xf52 %1 = and i8 %a, 1553 ret i8 %154}55 56define zeroext i16 @and_ri_i16(i16 signext %a) {57; CHECK-LABEL: and_ri_i1658; CHECK: and {{w[0-9]+}}, w0, #0xff59 %1 = and i16 %a, 25560 ret i16 %161}62 63define i32 @and_ri_i32(i32 %a) {64; CHECK-LABEL: and_ri_i3265; CHECK: and w0, w0, #0xff66 %1 = and i32 %a, 25567 ret i32 %168}69 70define i64 @and_ri_i64(i64 %a) {71; CHECK-LABEL: and_ri_i6472; CHECK: and x0, x0, #0xff73 %1 = and i64 %a, 25574 ret i64 %175}76 77define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {78; CHECK-LABEL: and_rs_i879; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #480; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}81 %1 = shl i8 %b, 482 %2 = and i8 %a, %183 ret i8 %284}85 86define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {87; CHECK-LABEL: and_rs_i1688; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #889; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}90 %1 = shl i16 %b, 891 %2 = and i16 %a, %192 ret i16 %293}94 95define i32 @and_rs_i32(i32 %a, i32 %b) {96; CHECK-LABEL: and_rs_i3297; CHECK: and w0, w0, w1, lsl #898 %1 = shl i32 %b, 899 %2 = and i32 %a, %1100 ret i32 %2101}102 103define i64 @and_rs_i64(i64 %a, i64 %b) {104; CHECK-LABEL: and_rs_i64105; CHECK: and x0, x0, x1, lsl #8106 %1 = shl i64 %b, 8107 %2 = and i64 %a, %1108 ret i64 %2109}110 111define i32 @and_mul_i32(i32 %a, i32 %b) {112; CHECK-LABEL: and_mul_i32113; CHECK: and w0, w0, w1, lsl #2114 %1 = mul i32 %b, 4115 %2 = and i32 %a, %1116 ret i32 %2117}118 119define i64 @and_mul_i64(i64 %a, i64 %b) {120; CHECK-LABEL: and_mul_i64121; CHECK: and x0, x0, x1, lsl #2122 %1 = mul i64 %b, 4123 %2 = and i64 %a, %1124 ret i64 %2125}126 127; OR128define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {129; CHECK-LABEL: or_rr_i1130; CHECK: orr [[REG:w[0-9]+]], w0, w1131 %1 = or i1 %a, %b132 ret i1 %1133}134 135define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {136; CHECK-LABEL: or_rr_i8137; CHECK: orr [[REG:w[0-9]+]], w0, w1138; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff139 %1 = or i8 %a, %b140 ret i8 %1141}142 143define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {144; CHECK-LABEL: or_rr_i16145; CHECK: orr [[REG:w[0-9]+]], w0, w1146; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff147 %1 = or i16 %a, %b148 ret i16 %1149}150 151define i32 @or_rr_i32(i32 %a, i32 %b) {152; CHECK-LABEL: or_rr_i32153; CHECK: orr w0, w0, w1154 %1 = or i32 %a, %b155 ret i32 %1156}157 158define i64 @or_rr_i64(i64 %a, i64 %b) {159; CHECK-LABEL: or_rr_i64160; CHECK: orr x0, x0, x1161 %1 = or i64 %a, %b162 ret i64 %1163}164 165define zeroext i8 @or_ri_i8(i8 %a) {166; CHECK-LABEL: or_ri_i8167; CHECK: orr [[REG:w[0-9]+]], w0, #0xf168; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff169 %1 = or i8 %a, 15170 ret i8 %1171}172 173define zeroext i16 @or_ri_i16(i16 %a) {174; CHECK-LABEL: or_ri_i16175; CHECK: orr [[REG:w[0-9]+]], w0, #0xff176; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff177 %1 = or i16 %a, 255178 ret i16 %1179}180 181define i32 @or_ri_i32(i32 %a) {182; CHECK-LABEL: or_ri_i32183; CHECK: orr w0, w0, #0xff184 %1 = or i32 %a, 255185 ret i32 %1186}187 188define i64 @or_ri_i64(i64 %a) {189; CHECK-LABEL: or_ri_i64190; CHECK: orr x0, x0, #0xff191 %1 = or i64 %a, 255192 ret i64 %1193}194 195define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {196; CHECK-LABEL: or_rs_i8197; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4198; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}199 %1 = shl i8 %b, 4200 %2 = or i8 %a, %1201 ret i8 %2202}203 204define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {205; CHECK-LABEL: or_rs_i16206; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #8207; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}208 %1 = shl i16 %b, 8209 %2 = or i16 %a, %1210 ret i16 %2211}212 213define i32 @or_rs_i32(i32 %a, i32 %b) {214; CHECK-LABEL: or_rs_i32215; CHECK: orr w0, w0, w1, lsl #8216 %1 = shl i32 %b, 8217 %2 = or i32 %a, %1218 ret i32 %2219}220 221define i64 @or_rs_i64(i64 %a, i64 %b) {222; CHECK-LABEL: or_rs_i64223; CHECK: orr x0, x0, x1, lsl #8224 %1 = shl i64 %b, 8225 %2 = or i64 %a, %1226 ret i64 %2227}228 229define i32 @or_mul_i32(i32 %a, i32 %b) {230; CHECK-LABEL: or_mul_i32231; CHECK: orr w0, w0, w1, lsl #2232 %1 = mul i32 %b, 4233 %2 = or i32 %a, %1234 ret i32 %2235}236 237define i64 @or_mul_i64(i64 %a, i64 %b) {238; CHECK-LABEL: or_mul_i64239; CHECK: orr x0, x0, x1, lsl #2240 %1 = mul i64 %b, 4241 %2 = or i64 %a, %1242 ret i64 %2243}244 245; XOR246define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {247; CHECK-LABEL: xor_rr_i1248; CHECK: eor [[REG:w[0-9]+]], w0, w1249 %1 = xor i1 %a, %b250 ret i1 %1251}252 253define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {254; CHECK-LABEL: xor_rr_i8255; CHECK: eor [[REG:w[0-9]+]], w0, w1256; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff257 %1 = xor i8 %a, %b258 ret i8 %1259}260 261define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {262; CHECK-LABEL: xor_rr_i16263; CHECK: eor [[REG:w[0-9]+]], w0, w1264; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff265 %1 = xor i16 %a, %b266 ret i16 %1267}268 269define i32 @xor_rr_i32(i32 %a, i32 %b) {270; CHECK-LABEL: xor_rr_i32271; CHECK: eor w0, w0, w1272 %1 = xor i32 %a, %b273 ret i32 %1274}275 276define i64 @xor_rr_i64(i64 %a, i64 %b) {277; CHECK-LABEL: xor_rr_i64278; CHECK: eor x0, x0, x1279 %1 = xor i64 %a, %b280 ret i64 %1281}282 283define zeroext i8 @xor_ri_i8(i8 signext %a) {284; CHECK-LABEL: xor_ri_i8285; CHECK: eor [[REG:w[0-9]+]], w0, #0xf286; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff287 %1 = xor i8 %a, 15288 ret i8 %1289}290 291define zeroext i16 @xor_ri_i16(i16 signext %a) {292; CHECK-LABEL: xor_ri_i16293; CHECK: eor [[REG:w[0-9]+]], w0, #0xff294; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff295 %1 = xor i16 %a, 255296 ret i16 %1297}298 299define i32 @xor_ri_i32(i32 %a) {300; CHECK-LABEL: xor_ri_i32301; CHECK: eor w0, w0, #0xff302 %1 = xor i32 %a, 255303 ret i32 %1304}305 306define i64 @xor_ri_i64(i64 %a) {307; CHECK-LABEL: xor_ri_i64308; CHECK: eor x0, x0, #0xff309 %1 = xor i64 %a, 255310 ret i64 %1311}312 313define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {314; CHECK-LABEL: xor_rs_i8315; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #4316; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}317 %1 = shl i8 %b, 4318 %2 = xor i8 %a, %1319 ret i8 %2320}321 322define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {323; CHECK-LABEL: xor_rs_i16324; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #8325; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}326 %1 = shl i16 %b, 8327 %2 = xor i16 %a, %1328 ret i16 %2329}330 331define i32 @xor_rs_i32(i32 %a, i32 %b) {332; CHECK-LABEL: xor_rs_i32333; CHECK: eor w0, w0, w1, lsl #8334 %1 = shl i32 %b, 8335 %2 = xor i32 %a, %1336 ret i32 %2337}338 339define i64 @xor_rs_i64(i64 %a, i64 %b) {340; CHECK-LABEL: xor_rs_i64341; CHECK: eor x0, x0, x1, lsl #8342 %1 = shl i64 %b, 8343 %2 = xor i64 %a, %1344 ret i64 %2345}346 347define i32 @xor_mul_i32(i32 %a, i32 %b) {348; CHECK-LABEL: xor_mul_i32349; CHECK: eor w0, w0, w1, lsl #2350 %1 = mul i32 %b, 4351 %2 = xor i32 %a, %1352 ret i32 %2353}354 355define i64 @xor_mul_i64(i64 %a, i64 %b) {356; CHECK-LABEL: xor_mul_i64357; CHECK: eor x0, x0, x1, lsl #2358 %1 = mul i64 %b, 4359 %2 = xor i64 %a, %1360 ret i64 %2361}362 363